CN104756614A - 基板以及基板的制造方法 - Google Patents

基板以及基板的制造方法 Download PDF

Info

Publication number
CN104756614A
CN104756614A CN201380056539.2A CN201380056539A CN104756614A CN 104756614 A CN104756614 A CN 104756614A CN 201380056539 A CN201380056539 A CN 201380056539A CN 104756614 A CN104756614 A CN 104756614A
Authority
CN
China
Prior art keywords
metal level
substrate
solder
groove portion
electronic unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201380056539.2A
Other languages
English (en)
Inventor
尾崎公教
小池靖弘
浅野裕明
志满津仁
川口茂树
浅井智朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Industries Corp
Original Assignee
Toyoda Automatic Loom Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Automatic Loom Works Ltd filed Critical Toyoda Automatic Loom Works Ltd
Publication of CN104756614A publication Critical patent/CN104756614A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/273Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/2732Screen printing, i.e. using a stencil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29012Shape in top view
    • H01L2224/29013Shape in top view being rectangular or square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29017Shape in side view being non uniform along the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29018Shape in side view comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/83815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0373Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09427Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09745Recess in conductor, e.g. in pad or in metallic substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827Tapered, e.g. tapered hole, via or groove
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2072Anchoring, i.e. one structure gripping into another
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0104Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0108Male die used for patterning, punching or transferring
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/0465Shape of solder, e.g. differing from spherical shape, different shapes due to different solder pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3442Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

本发明提供一种基板以及基板的制造方法,基板具备:绝缘基板;金属层,该金属层形成于上述绝缘基板的一面;以及电子部件,该电子部件钎焊于上述金属层的表面。上述金属层由金属板形成。上述金属层的表面具有钎焊区域以及位于该钎焊区域的外周的槽部。

Description

基板以及基板的制造方法
技术领域
本发明的技术涉及基板以及该基板的制造方法,上述基板具备:绝缘基板;形成于绝缘基板的一面的金属层;以及通过钎焊而安装于金属层的表面的电子部件。
背景技术
在通过钎焊将电子部件安装于形成在绝缘基板的一面的金属层的表面的情况下,需要抑制钎料在金属层的表面过度地浸润扩展的情况。通过抑制钎料的浸润扩展而使钎料充分存积在规定的范围内,钎焊的可靠性提高。例如,公知有如下技术:通过将钎焊区域的整体形成为比其他部分低的钎料存积部,抑制钎料从钎焊区域的浸润扩展(参照专利文献1)。
专利文献1:日本特开2011-151368号公报
然而,在通过钎焊将电子部件安装于金属层的表面的情况下,一般使用如下方法:在将具有规定的开口部的掩模重叠于金属层的表面并涂布膏状的钎料后,取下掩模并将电子部件安装在所涂布的钎料上。然而,在相对于将钎焊区域的整体形成为钎料存积部的金属层采用上述安装方法的情况下,在取下掩模时,存在钎料与掩模一起从金属层剥离的情况。
发明内容
本发明的目的在于提供一种能够使用掩模在金属层的表面容易地涂布钎料、且能够抑制钎料的浸润扩展的基板以及该基板的制造方法。
用于达成上述目的的基板具备:绝缘基板;金属层,该金属层形成于上述绝缘基板的一面;以及电子部件,该电子部件钎焊于上述金属层的表面。上述金属层由金属板形成。上述金属层的表面具有:钎焊区域;以及位于该钎焊区域的外周的槽部。
用于达成上述目的的基板的制造方法是制造如下基板的制造方法,该基板具备:绝缘基板;金属层,该金属层形成于上述绝缘基板的一面,且由金属板形成;以及电子部件,该电子部件通过钎焊安装于上述金属层的表面,其中,上述基板的制造方法具有如下步骤:使用掩模在设定于上述金属层的表面的涂布部涂布钎料的步骤;以及在上述钎料上安装上述电子部件的步骤。作为上述金属层,使用在上述涂布部的外侧形成有槽部的金属层。
附图说明
图1是实施方式的基板的俯视图。
图2是沿着图1的2-2线的剖视图。
图3是槽部的放大图。
图4是示出安装电子部件的方法的图。
具体实施方式
以下,根据附图对一个实施方式的基板进行说明。
如图1以及图2所示,基板10具备:绝缘基板11;在绝缘基板11的上表面隔开规定的间隔粘合的一对金属层12;以及以横跨一对金属层12的上表面的方式安装的电子部件13。
金属层12是由具有规定的图案形状的金属板形成的部分,通过利用冲床从金属板材料冲裁出规定的图案形状(冲压加工)而成型。作为形成金属层12的金属板,能够使用铜板、由在钎焊部分镀敷处理的铝等导电性金属材料形成的金属板。金属板的厚度优选为0.4~2.0mm,更优选为0.5~1.0mm。此外,在本实施方式中,使用厚度为0.5mm的铜板。
如图1以及图2所示,在金属层12的上表面设置有俯视观察时呈四边框状的槽部20。槽部20呈环状,换言之呈无接头状。如图3所示,槽部20具有:底面21;内周侧的侧面亦即第1侧面22;以及外周侧的侧面亦即第2侧面23。底面21是与金属层12的上表面平行的平面,第1侧面22以及第2侧面23是将底面21与金属层12的上表面连接的倾斜面。槽部20例如能够通过下述方法形成:在通过冲压加工而形成金属层12时,将具有与槽部20对应的突部的成型模具按压于金属板的上表面,从而使金属板的上表面局部地凹陷。
如图3所示,金属层12的上表面与第1侧面22之间的夹角α、以及金属层12的上表面与第2侧面23之间的夹角β优选分别设定为95~150度的范围。在本实施方式中,将角度α设为135度,并将角度β设为95度,使角度α比角度β大。另外,在本实施方式中,将槽部20的深度设为0.12mm。
如图1以及图2所示,在金属层12上表面的由槽部20包围的区域涂布有钎料30。换言之,沿着涂布于金属层12的钎料30的外周、即金属层12上表面的施有钎料的区域(钎焊区域)的外周,以包围该钎焊区域的方式设置有槽部20。而且,经由钎料30而在金属层12的上表面安装有半导体元件等电子部件13。
接下来,对通过钎焊将电子部件13安装于金属层12的上表面的方法进行说明,并对本实施方式的基板10的作用进行说明。
如图4所示,在粘合于绝缘基板11的上表面的金属层12的上表面,设定有涂布钎料的涂布部R(图4中的虚线内侧的区域),槽部20形成为包围涂布部R的无接头状。另外,槽部20沿涂布部R的边缘延伸,并且以与涂布部R的边缘隔开间隔的方式配置。
将具有与涂布部R对应的形状的开口部41的掩模40重叠于该金属层12的上表面(在图4中,用点划线示出掩模40)。此时,形成于涂布部R的外侧的槽部20被掩模40覆盖。而且,在使用刮刀等从掩模40的开口部41对金属层12的上表面涂布膏状的钎料后,将掩模40从金属层12取下。由此,对金属层12的涂布部R的上表面涂布钎料。
在本实施方式中,在涂布钎料的部位亦即涂布部R并未设置槽部20。因此,能够确保平坦的涂布部R的上表面与钎料之间的粘合面,钎料与金属层12充分地粘合。因此,能够抑制钎料与掩模40一同从金属层12剥离的情况。
接下来,将电子部件13载置在涂布于金属层12的涂布部R的钎料上。然后,在对基板10进行加热而使钎料熔融后,进行冷却而使钎料固化。由此,电子部件13通过钎焊被安装于金属层12的上表面。
在钎料熔融时,钎料向涂布部R的外侧浸润扩展,但能够利用设置于涂布部R的周围的槽部20抑制钎料越过槽部20浸润扩展的情况。此外,虽然先于钎料流动的助焊剂容易越过槽部20而扩展至金属层12上,但钎料的浸润扩展由槽部20限制,存在钎料存积于槽部20的内侧的倾向。另外,在金属层12的上表面,钎料从涂布部R浸润扩展至涂布部R与槽部20之间的区域内,结果,由槽部20包围的区域整体成为钎焊区域。而且,槽部20位于该钎焊区域的外周。
根据本实施方式,能够得到以下所记载的效果。
(1)基板10具备:绝缘基板11;金属层12,该金属层12形成于绝缘基板11的上表面;以及电子部件13,该电子部件13通过钎焊安装于金属层12的上表面。金属层12由金属板形成。在金属层12上表面的钎焊区域的外周设置有槽部20。
根据上述结构,并不在钎焊区域本身、而是在钎焊区域的外周设置有槽部20,因此,在使用掩模将钎料涂布于金属层12的表面时,能够确保金属层12的钎焊区域(涂布部R)与钎料之间的粘合面,从而金属层12与钎料充分地粘合。因此,在取下掩模时,所涂布的钎料难以剥离,能够容易地涂布钎料。
另外,在对基板10进行加热以使钎料熔融时,能够抑制钎料越过槽部20而浸润扩展的情况,并且钎料存积于槽部20的内侧。由此,能够在金属层12与电子部件13之间确保足够量的钎料,钎焊的可靠性提高。
(2)槽部20形成为包围钎焊区域的无接头状。换言之,槽部20在钎焊区域的周围整体连续地延伸。根据上述结构,能够抑制钎料30从钎焊区域朝向所有方位的浸润扩展。
(3)槽部20具有:平坦的底面21;内周侧(接近钎焊区域的一方)的侧面亦即第1侧面22;以及外周侧(远离钎焊区域的一方)的侧面亦即第2侧面23。
在通过将具有与槽部20对应的突部的成型模具按压于金属层12而形成槽部20的情况下,伴随着成型模具的反复使用,会在成型模具的突部的前端产生圆角、缺口等缺损。如上,若将槽部20形成为具有平坦的底面21的形状,则设置于成型模具的突部的前端也同样形成为平坦的形状。由此,在形成槽部20时,作用于成型模具的突部的前端的应力得到缓和,从而难以在突部的前端产生缺损。
(4)将槽部20的金属层12的表面与第1侧面22之间的夹角α处于95~150度的范围,并使金属层12的表面与第2侧面23之间的夹角β处于95~150度的范围。
根据上述结构,能够适当地抑制越过槽部20的钎料30的浸润扩展。另外,通过设定为上述角度,在将成型模具按压于金属层12而形成槽部20时,能够抑制金属层12与成型模具之间的咬合,从而使得成型模具从金属层12的脱模性良好。
(5)使金属层12的表面与第1侧面22之间的夹角α比金属层12的表面与第2侧面23之间的夹角β大。根据上述结构,位于外侧的第2侧面23成为更加接近垂直的斜面形状,由此,能够更加适当地抑制越过槽部20的钎料30的浸润扩展。
此外,上述实施方式也可以如下地进行变更。
槽部20并不限定于无接头状、换言之并不限定于连续的槽部,也可以是有端状、换言之为不连续的槽部。例如,存在与金属层12的图案形状等对应而在金属层12的上表面存在多个允许钎料的浸润扩展的部位与不允许钎料的浸润扩展的部位的情况。在这样的情况下,也能够仅在不允许钎料的浸润扩展的部位与钎焊区域(涂布部R)之间设置槽部20。
槽部20的截面形状没有特别限定。例如,也可以将底面21形成为凹曲面状,在这种情况下也能够得到上述(3)的效果。另外,也可以形成为无底面21的截面倒三角形状的槽部20。
也可以使金属层12的表面与第1侧面22之间的夹角α、和金属层12的表面与第2侧面23之间的夹角β相同。另外,也可以使上述角度α比上述角度β小。
在上述实施方式中,以横跨离开配置的两个金属层12的上表面的方式安装有电子部件13,但是也可以仅在一方的金属层12的上表面安装有电子部件13。
基板10也可以是在绝缘基板11的下表面粘合有另外的金属层的双面基板,也可以是还具有内层的多层基板,上述内层具有规定的图案。

Claims (5)

1.一种基板,其特征在于,具备:
绝缘基板;
金属层,该金属层形成于所述绝缘基板的一面;以及
电子部件,所述电子部件钎焊于所述金属层的表面,
所述金属层由金属板形成,
所述金属层的表面具有钎焊区域以及位于所述钎焊区域的外周的槽部。
2.根据权利要求1所述的基板,其特征在于,
所述槽部形成为包围所述钎焊区域的无接头状。
3.根据权利要求2所述的基板,其特征在于,
所述槽部具有底面、第1侧面以及第2侧面,所述第1侧面位于所述钎焊区域与所述第2侧面之间,
所述金属层的表面与所述第1侧面之间的夹角处于95~150度的范围,
所述金属层的表面与所述第2侧面之间的夹角处于95~150度的范围。
4.根据权利要求3所述的基板,其特征在于,
所述金属层的表面与所述第1侧面之间的夹角比所述金属层的表面与所述第2侧面之间的夹角大。
5.一种基板的制造方法,所述基板具备:绝缘基板;形成于所述绝缘基板的一面的由金属板形成的金属层;以及通过钎焊安装于所述金属层的表面的电子部件,
所述基板的制造方法的特征在于,
所述基板的制造方法具有如下步骤:
使用掩模在设定于所述金属层的表面的涂布部涂布钎料的步骤;以及
在所述钎料上安装所述电子部件的步骤,
作为所述金属层,使用在所述涂布部的外侧形成有槽部的金属层。
CN201380056539.2A 2012-11-01 2013-10-23 基板以及基板的制造方法 Pending CN104756614A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2012241898A JP5516696B2 (ja) 2012-11-01 2012-11-01 基板
JP2012-241898 2012-11-01
PCT/JP2013/078704 WO2014069305A1 (ja) 2012-11-01 2013-10-23 基板及び基板の製造方法

Publications (1)

Publication Number Publication Date
CN104756614A true CN104756614A (zh) 2015-07-01

Family

ID=50627214

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380056539.2A Pending CN104756614A (zh) 2012-11-01 2013-10-23 基板以及基板的制造方法

Country Status (7)

Country Link
US (1) US9655240B2 (zh)
EP (1) EP2916630A4 (zh)
JP (1) JP5516696B2 (zh)
KR (1) KR20150064224A (zh)
CN (1) CN104756614A (zh)
BR (1) BR112015009213A2 (zh)
WO (1) WO2014069305A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017195290A (ja) * 2016-04-21 2017-10-26 スタンレー電気株式会社 基板構造

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879211B2 (en) 2016-06-30 2020-12-29 R.S.M. Electron Power, Inc. Method of joining a surface-mount component to a substrate with solder that has been temporarily secured
FR3056073B1 (fr) * 2016-09-09 2018-08-17 Valeo Systemes De Controle Moteur Unite electronique, convertisseur de tension la comprenant et equipement electrique comprenant un tel convertisseur de tension
WO2020003908A1 (ja) * 2018-06-29 2020-01-02 日本電産株式会社 配線基板および電子部品実装基板
WO2020003907A1 (ja) * 2018-06-29 2020-01-02 日本電産株式会社 配線基板および電子部品実装基板
CN110094624B (zh) * 2019-05-17 2020-12-18 北京深醒科技有限公司 一种门禁机安装容错机构

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06112634A (ja) * 1992-09-29 1994-04-22 Taiyo Yuden Co Ltd 厚膜回路基板の製造方法
JPH07263849A (ja) * 1994-03-24 1995-10-13 Mitsubishi Electric Corp 印刷回路基板
US6246587B1 (en) * 1998-12-03 2001-06-12 Intermedics Inc. Surface mounted device with grooves on a termination lead and methods of assembly
JP2003110205A (ja) * 2001-09-28 2003-04-11 Dowa Mining Co Ltd 金属−セラミックス回路基板
US20030073349A1 (en) * 2001-10-16 2003-04-17 Yazaki Corporation Structure of joining chip part to bus bars
JP2004006454A (ja) * 2002-05-31 2004-01-08 Nippon Mektron Ltd 回路基板のランド構造
JP2004140226A (ja) * 2002-10-18 2004-05-13 Yazaki Corp チップ部品のバスバーへの接合構造
CN101295820A (zh) * 2007-04-25 2008-10-29 株式会社电装 金属布线板
US20120119868A1 (en) * 2009-07-27 2012-05-17 Kabushiki Kaisha Toyota Jidoshokki Wiring substrate and manufacturing method for wiring substrate

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07254775A (ja) * 1994-03-16 1995-10-03 Sankyo Seiki Mfg Co Ltd 回路基板
US6448507B1 (en) * 2000-06-28 2002-09-10 Advanced Micro Devices, Inc. Solder mask for controlling resin bleed
JP2006114587A (ja) * 2004-10-13 2006-04-27 Tohoku Ricoh Co Ltd プリント配線基板
JP5153574B2 (ja) * 2007-11-05 2013-02-27 パナソニック株式会社 実装構造体
JP5666891B2 (ja) 2009-12-24 2015-02-12 古河電気工業株式会社 射出成形基板と実装部品との取付構造
JP5641230B2 (ja) 2011-01-28 2014-12-17 株式会社豊田自動織機 電子機器

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06112634A (ja) * 1992-09-29 1994-04-22 Taiyo Yuden Co Ltd 厚膜回路基板の製造方法
JPH07263849A (ja) * 1994-03-24 1995-10-13 Mitsubishi Electric Corp 印刷回路基板
US6246587B1 (en) * 1998-12-03 2001-06-12 Intermedics Inc. Surface mounted device with grooves on a termination lead and methods of assembly
JP2003110205A (ja) * 2001-09-28 2003-04-11 Dowa Mining Co Ltd 金属−セラミックス回路基板
US20030073349A1 (en) * 2001-10-16 2003-04-17 Yazaki Corporation Structure of joining chip part to bus bars
JP2004006454A (ja) * 2002-05-31 2004-01-08 Nippon Mektron Ltd 回路基板のランド構造
JP2004140226A (ja) * 2002-10-18 2004-05-13 Yazaki Corp チップ部品のバスバーへの接合構造
CN101295820A (zh) * 2007-04-25 2008-10-29 株式会社电装 金属布线板
US20120119868A1 (en) * 2009-07-27 2012-05-17 Kabushiki Kaisha Toyota Jidoshokki Wiring substrate and manufacturing method for wiring substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017195290A (ja) * 2016-04-21 2017-10-26 スタンレー電気株式会社 基板構造

Also Published As

Publication number Publication date
KR20150064224A (ko) 2015-06-10
BR112015009213A2 (pt) 2017-07-04
EP2916630A1 (en) 2015-09-09
JP2014093360A (ja) 2014-05-19
US9655240B2 (en) 2017-05-16
US20150289371A1 (en) 2015-10-08
WO2014069305A1 (ja) 2014-05-08
EP2916630A4 (en) 2016-07-13
JP5516696B2 (ja) 2014-06-11

Similar Documents

Publication Publication Date Title
CN104756614A (zh) 基板以及基板的制造方法
US20180047507A1 (en) Electrical connection contact for a ceramic component, a ceramic component, and a component arrangement
JP6499007B2 (ja) チップ抵抗器
JP2008288489A5 (zh)
WO2015016289A1 (ja) 配線基板および電子装置
TWI451817B (zh) 配線板及配線板的製造方法
WO2018113741A1 (zh) 一种二极管的封装方法及二极管
US10892201B2 (en) Electronic device comprising a support substrate and an encapsulating cover for an electronic component
CN103972618A (zh) Tm模介质滤波器
CN107550233A (zh) 一种铝锅及其新复底工艺
JP2010251619A (ja) 配線基板、配線基板接合体、配線基板および配線基板接合体の製造方法
CN208081071U (zh) 一种铝锅
JP6272052B2 (ja) 電子素子搭載用基板及び電子装置
KR101957479B1 (ko) 인쇄회로기판의 쉴드캔 접합방법 및 접합구조
JP6214030B2 (ja) 回路基板、回路モジュール、回路基板の製造方法及び回路モジュールの製造方法
TWI496226B (zh) 防止金屬焊墊被刮傷的電路板結構及製造方法
CN203057695U (zh) 陶瓷电路基板
CN203057702U (zh) 多层陶瓷电路基板
JP6264150B2 (ja) パワーモジュール用基板及びヒートシンク付パワーモジュール用基板
JP5713093B1 (ja) 基板
CN106216791A (zh) Lccc器件的一种底部空隙焊装方法
JP2011073194A (ja) 金属−セラミックス接合基板およびその製造方法
JP6680634B2 (ja) 半導体素子実装用基板および半導体装置
JP5807670B2 (ja) 配線板
JP5686017B2 (ja) スパッタリングターゲットの製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20150701

WD01 Invention patent application deemed withdrawn after publication