CN104600051A - 半导体模块 - Google Patents

半导体模块 Download PDF

Info

Publication number
CN104600051A
CN104600051A CN201410520494.6A CN201410520494A CN104600051A CN 104600051 A CN104600051 A CN 104600051A CN 201410520494 A CN201410520494 A CN 201410520494A CN 104600051 A CN104600051 A CN 104600051A
Authority
CN
China
Prior art keywords
base plate
insulated substrate
semiconductor module
location
module according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410520494.6A
Other languages
English (en)
Other versions
CN104600051B (zh
Inventor
大月高实
米山玲
山下秋彦
木村义孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN104600051A publication Critical patent/CN104600051A/zh
Application granted granted Critical
Publication of CN104600051B publication Critical patent/CN104600051B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/049Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being perpendicular to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54426Marks applied to semiconductor devices or parts for alignment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486Located on package parts, e.g. encapsulation, leads, package substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48799Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48847Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905Shape
    • H01L2224/49051Connectors having different shapes
    • H01L2224/49052Different loop heights
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/37Effects of the manufacturing process
    • H01L2924/3701Effects of the manufacturing process increased through put

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Dispersion Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

功率模块具有:基座板(3),其在表面(3a)设置有定位用导线接合部(20a~20d);绝缘基板(8),其在与基座板(3)相对的背面(8b)侧,设置有对定位用导线接合部(20)进行收容的孔部(21a~21d),孔部(21a~21d)对定位用导线接合部(20)进行收容,从而该绝缘基板(8)在相对于基座板(3)被定位的状态下,固定在基座板(3)上;以及半导体芯片,其在绝缘基板(8)中配置在与背面(8b)相反的表面侧。

Description

半导体模块
技术领域
本发明涉及一种半导体模块。
背景技术
在功率半导体模块中,通过焊料接合而在金属基座板上搭载绝缘基板及半导体芯片等。例如在日本特开2000-031358号公报、日本特开平01-281760号公报中,提出有下述技术,即,在将利用铜箔进行了电路配置的绝缘基板搭载于金属基座板上而形成的半导体模块中,为了绝缘基板的定位而在金属基座板上的规定位置处设置凹凸部。
在上述日本特开2000-031358号公报以及日本特开平01-281760号公报中提出的半导体模块中,存在下述问题,即,为了在基座板上设置凹凸部,需要向该基座板另外实施加工,因此工时增加,制造效率降低。另外,在使用模具等设置凹凸部的情况下,对该凹凸部的形成部位、数量进行变更时,由于还需要模具自身的设计变更,所以难以用于多品种的少量生产。
发明内容
本发明就是鉴于上述课题而提出的,其目的在于提供一种半导体模块,该半导体模块抑制制造效率的降低,在基座板上高精度地定位绝缘基板。
本发明所涉及的半导体模块具有:基座板,其在表面设置有定位用导线接合部;绝缘基板,其在与基座板相对的背面侧,设置对定位用导线接合部进行收容的收容部,通过由上述收容部对定位用导线接合部进行收容,从而该绝缘基板在相对于基座板被定位的状态下,固定在基座板上;以及半导体芯片,其在绝缘基板中配置在与上述背面相反的表面侧。
根据本发明所涉及的半导体模块,能够提供一种半导体模块,其抑制制造效率的降低,相对于基座板高精度地定位绝缘基板。
通过结合附图进行理解而对本发明做出的详细说明,使本发明的上述内容及其它目的、特征、方案以及优点变得明确。
附图说明
图1是表示实施方式1所涉及的半导体模块的构造的概略剖面图。
图2是用于说明实施方式1所涉及的半导体模块的构造的概略斜视图。
图3是用于说明实施方式1所涉及的半导体模块的第1变形例的构造的概略斜视图。
图4是用于说明实施方式1所涉及的半导体模块的第2变形例的构造的概略斜视图。
图5是用于说明实施方式1所涉及的半导体模块的第3变形例的构造的概略斜视图。
图6是用于说明实施方式1所涉及的半导体模块的第4变形例的构造的概略斜视图。
图7是表示实施方式2所涉及的半导体模块的构造的概略剖面图。
具体实施方式
下面,基于附图,对本发明的实施方式进行说明。此外,对于在以下的附图中相同或者相当的部分,标注相同的参照标号,不重复其说明。
(实施方式1)
首先,对作为本发明的一个实施方式的实施方式1进行说明。首先,对本实施方式所涉及的半导体模块的构造进行说明。参照图1,作为本实施方式所涉及的半导体模块的功率模块1,主要具有壳体2、基座板3、电力端子4、信号端子5、电力配线4a及信号配线5a(接合导线)、绝缘基板8、半导体芯片10、硅凝胶12、封装树脂13。
壳体2配置在基座板3的表面3a上,与基座板3一起构成用于收容半导体芯片10的内部空间。电力端子4由金属构成,沿壳体2的内表面,以接近半导体芯片10的方式弯曲并延伸。电力端子4经由电力配线4a与形成在绝缘基板8的表面(正面)8a上的图案层7连接。
信号端子5由金属构成,沿壳体2的内表面,以接近半导体芯片10的方式延伸。信号端子5配置为,在壳体2的内部空间中与电力端子4相对,在与电力端子4之间夹着半导体芯片10。信号端子5经由信号配线5a与半导体芯片10连接。
绝缘基板8具有表面(正面)8a以及背面8b,在该表面8a以及背面8b上分别形成有图案层7、9。图案层7、9例如由铜箔等构成,具有大于或等于0.1mm而小于或等于0.5mm的厚度。绝缘基板8以相对于基座板3进行了定位的状态,利用焊料层6固定在该基座板3上。焊料层6的厚度是例如大于或等于0.1mm而小于或等于0.5mm。对于绝缘基板8相对于基座板3的定位机构,在后面记述。
半导体芯片10配置在绝缘基板8的表面8a侧,利用焊料层11固定在绝缘基板8上。半导体芯片10是例如MOSFET(Metal OxideSemiconductor Field Effect Transistor)、IGBT(Insulated Gate BipolarTransistor)或者二极管等半导体元件。此外,在图1中,在绝缘基板8上仅固定有1个半导体芯片10,但也可以将多个上述半导体元件在绝缘基板8上排列固定。
硅凝胶12填充在壳体2的内部空间中,包覆半导体芯片10。封装树脂13配置在硅凝胶12上。如上述所示,半导体芯片10在壳体2的内部空间中由硅凝胶12以及封装树脂13封装。
下面,参照图1及图2,说明绝缘基板8相对于基座板3的定位机构。图2示出了在功率模块1(图1)中将基座板3以及绝缘基板8分解后的状态。参照图2,在基座板3的表面3a上设置有多个定位用导线接合部20(20a~20d)。定位用导线接合部20利用与将电力配线4a以及信号配线5a(图1)等向半导体芯片10、端子进行固定的方法相同的方法,固定在基座板3上。更具体地说,通过向设置在基座板3的表面3a上的导线施加热量、超声波或者压力等,从而在表面3a上设置定位用导线接合部20。
定位用导线接合部20由与电力配线4a以及信号配线5a相同的金属构成,例如由铝、铜等金属材料构成。定位用导线接合部20的直径例如大于或等于0.1mm而小于或等于1.0mm。定位用导线接合部20也可以如图2所示分别设置在四边形的四角,但其数量、配置方法并没有特别地限定。
在形成于绝缘基板8的背面8b(与基座板3相对的面)上的图案层9上,设置有用于分别收容定位用导线接合部20a~20d的多个孔部21a~21d(收容部)。更具体地说,定位用导线接合部20a~20d分别能够向各个孔部21a~21d插入,由此将绝缘基板8相对于基座板3进行定位。
孔部21也可以如图2所示,设置在成为图案层9的外周形状的矩形形状中的角部(四角),但并不限定于此,可以与定位用导线接合部20的数量、配置方法相对应而适当选择。例如孔部21也可以设置在与上述矩形形状的边相邻的部分处。
上述功率模块1可以以下述方式制造。参照图1,首先,在基座板3的表面3a上,通过焊接而对形成有图案层7、9的绝缘基板8以及半导体芯片10进行固定。然后,使半导体芯片10以及图案层7经由电力配线4a、信号配线5a而与电力端子4、信号端子5等连接。然后,将硅凝胶12以及封装树脂13依次封入,对半导体芯片10进行封装。这样得到上述功率模块1。
下面,在对本实施方式所涉及的功率模块1的特征进行说明的基础上,对其作用效果进行说明。功率模块1具有:基座板3,其在表面3a上设置有定位用导线接合部20;绝缘基板8,其在与基座板3相对的背面8b侧,设置对定位用导线接合部20进行收容的孔部21(收容部),在使该孔部21收容定位用导线接合部20而相对于基座板3进行了定位的状态下,固定于基座板3上;以及半导体芯片10,其在绝缘基板8上,配置在与背面8b相反的表面8a侧。
在上述功率模块1中,能够在定位用导线接合部20被收容于孔部21中而将绝缘基板8相对于基座板3进行了定位的状态下,将该绝缘基板8固定在基座板3上。由此,与对基座板自身进行加工而形成凹凸部等,并利用该凹凸部对绝缘基板8进行定位的情况相比,使得工序更简化,提高制造效率。另外,定位用导线接合部20可以使用与在连接电力配线4a、信号配线5a时使用的设备相同的设备进行制作,从而可以与各品种相对应而容易地变更固定位置、导线的种类。另外,由于在基座板中,还能够省略绝缘基板的定位用保护层的形成,因此还能够实现基座板的标准化。
在上述功率模块1中,在基座板3的表面3a上设置有多个定位用导线接合部20a~20d。另外,在绝缘基板8的背面8b侧,设置有用于收容多个定位用导线接合部20a~20d的多个孔部21a~21d(收容部)。由此,能够将绝缘基板8相对于基座板3更高精度地定位。
在上述功率模块1中,在形成于绝缘基板8的背面8b上的图案层9上设置有孔部21(收容部)。并且,通过向孔部21中插入定位用导线接合部20,从而将绝缘基板8相对于基座板3定位。由此,能够将绝缘基板8相对于基座板3更高精度地定位。
(第1变形例)
下面,对本实施方式所涉及的功率模块1的第1变形例进行说明。图3示出了本变形例中的绝缘基板8以及图案层9的构造。参照图3,在本变形例中,在形成于绝缘基板8的背面8b上的图案层9的端部处,形成有多个切口部22(22a~22d)(收容部)。更具体地说,图案层9的外周形状由矩形形状构成,在该矩形形状中的4个角部分别形成有切口部22a~22d。并且,通过使定位用导线接合部20a~20d(图2)位于各切口部22a~22d中,从而将绝缘基板8相对于基座板3进行定位。由此,使图案层9的加工变得更容易,因此能够进一步提高生产性。
(第2变形例)
下面,对本实施方式所涉及的功率模块1的第2变形例进行说明。图4示出了本变形例中的绝缘基板8以及图案层9的构造。参照图4,在本变形例中,形成有切口部22a、22d,该切口部22a、22d是在成为图案层9的外周形状的矩形形状中的相对的2个角部处形成切口后的部分。并且,通过使定位用导线接合部20a、20d(图2)位于各切口部22a、22d中,从而将绝缘基板8相对于基座板3进行定位。由此,使图案层9的形状更简化,进一步提高生产性。另外,通过在上述矩形形状中相对的2个角部(最远离的2个角部)处形成切口部22a、22d,从而能够进一步提高绝缘基板8相对于基座板3的定位精度。
(第3变形例)
下面,对本实施方式所涉及的功率模块1的第3变形例进行说明。图5示出了本变形例中的绝缘基板8以及图案层9的构造。参照图5,在本变形例中,除了在成为图案层9的外周形状的矩形形状中的相对的2个角部处形成切口后的切口部22a、22d之外,还形成有在与上述2个角部不同的1个角部处形成切口后的部分即切口部22c。并且,通过使定位用导线接合部20a、20c、20d(图2)位于各切口部22a、22c、22d中,从而将绝缘基板8相对于基座板3定位。由此,抑制绝缘基板8相对于基座板3倾斜的情况,进一步提高绝缘基板8相对于基座板3的定位精度。
(第4变形例)
下面,对本实施方式所涉及的功率模块1的第4变形例进行说明。图6示出了本变形例中的绝缘基板8以及图案层9的构造。参照图6,在本变形例中,形成有切口部23a~23d,该切口部23a~23d是在成为图案层9的外周形状的矩形形状的边处形成切口后的部分。并且,通过使定位用导线接合部20位于各切口部23a~23d中,从而将绝缘基板8相对于基座板3定位。由此,对于收容于各切口部23a~23d中的定位用导线接合部20,可以设置大于或等于2个的接合部分。其结果,能够设置导线形状不会因接合而变化的部位,能够在基座板3和绝缘基板8之间,更可靠地确保与导线直径相当的距离。
(实施方式2)
下面,对作为本发明的其他实施方式的实施方式2进行说明。本实施方式所涉及的半导体模块具有与上述实施方式1所涉及的半导体模块基本相同的结构,并且具有相同的效果。但是,本实施方式所涉及的半导体模块还具有用于对半导体芯片进行驱动的控制电路,这一点与上述实施方式1所涉及的半导体模块不同。
参照图7,作为本实施方式所涉及的半导体模块的功率模块1A,在上述实施方式1所涉及的功率模块1(图1)的结构的基础上,还具有由中继端子14、印刷基板15、多个SMT(Surface MountTechnology)部件16以及接口17构成的控制电路。能够利用该控制电路对半导体芯片10进行驱动。
中继端子14以接近半导体芯片10的方式延伸,利用控制配线14a与半导体芯片10连接。印刷基板15配置在硅凝胶12上,在其表面上排列配置有多个SMT部件16。接口17的一个端部与印刷基板15连接,另一个端部延伸至壳体2的外部。如上述所示,本实施方式所涉及的功率模块1A成为具有用于对半导体芯片10进行驱动的控制电路的智能功率模块(IPM:Intelligent Power Module)。
本发明的半导体模块能够特别有利地适用于下述半导体模块,即,要求抑制制造效率的降低,并相对于基座板高精度地定位绝缘基板。
针对本发明的实施方式进行了说明,但应当认为本次公开的实施方式的所有方式都是例示且并不是限制性的内容。本发明的范围由权利要求书表示,包含与权利要求书等同的含义以及范围内的全部变更。

Claims (9)

1.一种半导体模块,其具有:
基座板,其在表面设置有定位用导线接合部;
绝缘基板,其在与所述基座板相对的背面侧,设置用于收容所述定位用导线接合部的收容部,通过由所述收容部对所述定位用导线接合部进行收容,从而所述绝缘基板在相对于所述基座板被定位的状态下,固定在所述基座板上;以及
半导体芯片,其在所述绝缘基板中,配置在与所述背面相反的表面侧。
2.根据权利要求1所述的半导体模块,其中,
在所述基座板的所述表面,设置有多个所述定位用导线接合部,
在所述绝缘基板的所述背面侧,设置有对多个所述定位用导线接合部分别进行收容的多个所述收容部。
3.根据权利要求1所述的半导体模块,其中,
所述收容部是在形成于所述绝缘基板的所述背面上的图案层上设置的孔部,
所述绝缘基板通过使所述定位用导线接合部向所述孔部插入,从而相对于所述基座板进行定位。
4.根据权利要求3所述的半导体模块,其中,
所述孔部设置在成为所述图案层的外周形状的矩形形状中的角部处或者与所述矩形形状的边相邻的部分处。
5.根据权利要求1所述的半导体模块,其中,
所述收容部是在形成于所述绝缘基板的所述背面上的图案层的端部处设置的切口部,
所述绝缘基板通过使所述定位用导线接合部位于所述切口部中,从而相对于所述基座板进行定位。
6.根据权利要求5所述的半导体模块,其中,
所述切口部包含有在成为所述图案层的外周形状的矩形形状中的相对的2个角部处形成切口后的部分。
7.根据权利要求6所述的半导体模块,其中,
所述切口部还包含有在与所述2个角部不同的1个角部处形成切口后的部分。
8.根据权利要求5所述的半导体模块,其中,
所述切口部还包含有在成为所述图案层的外周形状的矩形形状的边处形成切口后的部分。
9.根据权利要求1所述的半导体模块,其中,
还具有控制电路,该控制电路对所述半导体芯片进行驱动。
CN201410520494.6A 2013-10-31 2014-09-30 半导体模块 Active CN104600051B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-226731 2013-10-31
JP2013226731A JP6165025B2 (ja) 2013-10-31 2013-10-31 半導体モジュール

Publications (2)

Publication Number Publication Date
CN104600051A true CN104600051A (zh) 2015-05-06
CN104600051B CN104600051B (zh) 2017-11-24

Family

ID=52811971

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410520494.6A Active CN104600051B (zh) 2013-10-31 2014-09-30 半导体模块

Country Status (4)

Country Link
US (1) US9159676B2 (zh)
JP (1) JP6165025B2 (zh)
CN (1) CN104600051B (zh)
DE (1) DE102014218389B4 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111406316A (zh) * 2017-10-26 2020-07-10 新电元工业株式会社 电子部件
CN111883435A (zh) * 2019-05-02 2020-11-03 奥迪股份公司 用于制造半导体模块的方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5852609B2 (ja) * 2013-06-10 2016-02-03 長野計器株式会社 センサ
JP6299120B2 (ja) * 2013-09-05 2018-03-28 富士電機株式会社 半導体モジュール
CN112133654B (zh) * 2016-07-18 2024-07-09 圆益Ips股份有限公司 对齐模块

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11186331A (ja) * 1997-12-19 1999-07-09 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2012227362A (ja) * 2011-04-20 2012-11-15 Mitsubishi Materials Corp ヒートシンク付パワーモジュール用基板ユニットおよびその製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01281760A (ja) 1988-05-07 1989-11-13 Mitsubishi Electric Corp 半導体装置
JPH02266557A (ja) * 1989-04-06 1990-10-31 Mitsubishi Electric Corp 半導体装置
JPH10321651A (ja) * 1997-05-19 1998-12-04 Mitsubishi Electric Corp 半導体装置
JP2000031358A (ja) 1998-07-08 2000-01-28 Sansha Electric Mfg Co Ltd 電力用半導体モジュール
JP2000068446A (ja) * 1998-08-25 2000-03-03 Hitachi Ltd パワー半導体モジュール
JP3619708B2 (ja) * 1999-06-02 2005-02-16 株式会社日立製作所 パワー半導体モジュール
US6774465B2 (en) * 2001-10-05 2004-08-10 Fairchild Korea Semiconductor, Ltd. Semiconductor power package module
DE102009002992B4 (de) * 2009-05-11 2014-10-30 Infineon Technologies Ag Leistungshalbleitermodulanordnung mit eindeutig und verdrehsicher auf einem Kühlkörper montierbarem Leistungshalbleitermodul und Montageverfahren
CN102804368B (zh) * 2009-06-10 2015-12-02 丰田自动车株式会社 半导体装置
JP5716637B2 (ja) * 2011-11-04 2015-05-13 住友電気工業株式会社 半導体モジュール及び半導体モジュールの製造方法
JP2013161961A (ja) * 2012-02-06 2013-08-19 Calsonic Kansei Corp 半導体モジュールの製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11186331A (ja) * 1997-12-19 1999-07-09 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2012227362A (ja) * 2011-04-20 2012-11-15 Mitsubishi Materials Corp ヒートシンク付パワーモジュール用基板ユニットおよびその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111406316A (zh) * 2017-10-26 2020-07-10 新电元工业株式会社 电子部件
CN111883435A (zh) * 2019-05-02 2020-11-03 奥迪股份公司 用于制造半导体模块的方法
CN111883435B (zh) * 2019-05-02 2023-12-05 奥迪股份公司 用于制造半导体模块的方法

Also Published As

Publication number Publication date
US9159676B2 (en) 2015-10-13
JP6165025B2 (ja) 2017-07-19
US20150115478A1 (en) 2015-04-30
CN104600051B (zh) 2017-11-24
JP2015088654A (ja) 2015-05-07
DE102014218389B4 (de) 2021-06-17
DE102014218389A1 (de) 2015-04-30

Similar Documents

Publication Publication Date Title
US9887142B2 (en) Power semiconductor device
US9734944B2 (en) Electronic package structure comprising a magnetic body and an inductive element and method for making the same
US9107331B2 (en) Intelligent power module and related assembling method
EP3226292B1 (en) Lead frame, semiconductor device, method for manufacturing lead frame, and method for manufacturing semiconductor device
CN104600051A (zh) 半导体模块
JP6107362B2 (ja) 半導体装置の製造方法及び半導体装置
KR101123827B1 (ko) 반도체 장치
CN103370788B (zh) 半导体装置及其制造方法
EP2725610B1 (en) Semiconductor device and method for producing semiconductor device
US20070052074A1 (en) Optical coupling element, method for producing the optical coupling element, and electronic device equipped with the optical coupling element
CN104008980A (zh) 半导体器件
CN104517913A (zh) 半导体装置及其制造方法
KR101243136B1 (ko) 반도체 장치 및 그 제조 방법
CN105225971A (zh) 半导体装置的制造方法
CN102903693A (zh) 功率器件封装模块及其制造方法
CN103378025B (zh) 半导体装置
CN104952854B (zh) 电子封装结构及其封装方法
CN103392230A (zh) 半导体装置及半导体装置的制造方法
CN111430343A (zh) 一种垂直式集成封装组件及其封装方法
JP2015037103A (ja) 半導体装置及び半導体装置の製造方法
US20230115068A1 (en) Led Lighting Base, Led Lighting Bead, and Led Lighting Strip
CN111406311A (zh) 电子模块以及电子模块的制造方法
WO2024190397A1 (ja) 電子装置
JP5233973B2 (ja) モールドパッケージの製造方法
JP2008053515A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant