CN104347525B - 电子装置 - Google Patents

电子装置 Download PDF

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Publication number
CN104347525B
CN104347525B CN201410366595.2A CN201410366595A CN104347525B CN 104347525 B CN104347525 B CN 104347525B CN 201410366595 A CN201410366595 A CN 201410366595A CN 104347525 B CN104347525 B CN 104347525B
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device chip
substrate
electronic installation
circuit board
expansion
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CN104347525A (zh
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山内基
川内治
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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Abstract

本发明提供了一种电子装置,该电子装置包括:布线基板;多个器件芯片,该多个器件芯片通过凸起倒装地安装在所述布线基板的上表面,在所述器件芯片与所述布线基板的上表面之间具有使所述凸起露出的间隙,并且所述多个器件芯片包括具有热膨胀系数大于所述布线基板的热膨胀系数的基板的至少一个器件芯片;接合基板,该接合基板被接合到所述多个器件芯片,并且热膨胀系数等于或小于所述至少一个器件芯片中包括的所述基板的热膨胀系数;以及密封部,该密封部覆盖所述接合基板,并且密封所述多个器件芯片。

Description

电子装置
技术领域
本发明的特定方面涉及一种电子装置,例如,涉及一种将多个器件芯片倒装地安装在布线基板上的电子装置。
背景技术
近年来,要求电子装置的小型化和低成本。对于这种需求,已经开发了一种通过凸起将多个器件芯片倒装地安装在布线基板上并且密封这些器件芯片的技术(参见例如日本专利申请第2003-347483号公报和国际专利申请的日本第2006-513564号国家公报)。
当器件芯片例如用树脂密封时,气密性和散热性劣化,因此损坏可靠性。而且,当在器件芯片与布线基板之间存在使凸起露出的间隙时,因为布线基板、器件芯片和密封单元各自的热膨胀系数彼此不同,所以在与各个器件芯片对应的凸起中出现应力,因此损坏了可靠性。
发明内容
根据本发明的一个方面,提供了一种电子装置,该电子装置包括:布线基板;多个器件芯片,该多个器件芯片通过凸起倒装地安装在所述布线基板的上表面,在所述器件芯片与所述布线基板的上表面之间具有使所述凸起露出的间隙,并且包括具有热膨胀系数大于所述布线基板的热膨胀系数的基板的至少一个器件芯片;接合基板,该接合基板被接合到所述多个器件芯片,并且具有的热膨胀系数等于或小于所述至少一个器件芯片中包括的所述基板的热膨胀系数;以及密封部,该密封部覆盖所述接合基板,并且密封所述多个器件芯片。
附图说明
图1A是例示根据第一实施方式的电子装置的俯视图;
图1B是沿图1A的线A-A截取的截面图;
图2是例示根据比较例1的电子装置的截面图;
图3A是例示根据第二实施方式的电子装置的俯视图;
图3B是沿图3A的线A-A截取的截面图;
图4A至图4D是例示根据第二实施方式的电子装置的制造方法的截面图;
图5A至图5D是例示根据第二实施方式的电子装置的另一制造方法的截面图;
图6A是例示执行模拟的、根据第一实施方式的电子装置的俯视图;
图6B是沿图6A的线A-A截取的截面图;
图7A是例示执行模拟的、根据第二实施方式的电子装置的俯视图;
图7B是沿图7A的线A-A截取的截面图;
图8是例示根据第一实施方式的电子装置的模拟结果的图;
图9是例示根据第二实施方式的电子装置的模拟结果的图;
图10A是例示根据第三实施方式的电子装置的俯视图;
图10B是沿图10A的线A-A截取的截面图;
图11A至图11D是例示根据第三实施方式的电子装置的制造方法的截面图;以及
图12是例示根据第三实施方式的第一变型例的电子装置的截面图。
具体实施方式
将参照附图描述实施方式。
(第一实施方式)
图1A是例示根据第一实施方式的电子装置的俯视图,并且图1B是沿图1A中的线A-A截取的截面图。这里,图1A透过密封单元26和多个器件芯片12例示了凸起14。如图1A和图1B所示,器件芯片12经由凸起14倒装地安装在由绝缘体(如陶瓷)构成的布线基板10的上表面。在布线基板10的上表面与器件芯片12之间形成有间隙28,并且凸起14在间隙28中露出。虽然凸起14例如由焊料构成,但是可以将金(Au)用作凸起14。器件芯片12包括表面声波(SAW:surface acoustic wave)器件芯片12a和半导体器件芯片12b。例如,SAW器件芯片12a通过位于四个角的凸起14倒装地安装在布线基板10的上表面。例如,半导体器件芯片12b通过排布为点阵形状的凸起14倒装地安装在布线基板10的上表面。
SAW器件芯片12a包括:压电基板16,该压电基板16由诸如钽酸锂(LiTaO3;下文称作“LT”)或铌酸锂(LiNbO3;下文称作“LN”)等的压电物质构成;以及设置在压电基板的与布线基板10相对的一侧的表面上的金属膜(未示出)(诸如IDT(叉指式换能器)和反射器等)。半导体器件芯片12b包括由半导体(诸如硅(Si)或砷化镓(GaAs))构成的半导体基板18。
过孔布线(via-wiring)20设置在布线基板10的内部。虽然图1B仅例示了沿水平方向延伸的过孔布线20,但是也存在沿垂直方向延伸的过孔布线20。器件芯片12经由过孔布线20电连接到设置在布线基板10的下表面的外部端子22。
金属图案24设置在布线基板10的上表面且处于器件芯片12的外侧。金属图案24环状地形成,以便围绕器件芯片12。用于密封器件芯片12的密封单元26通过连接到金属图案24并覆盖器件芯片12而形成。密封单元26由诸如焊料等的金属构成。期望的是,将具有适用于构成密封单元26的材料的可湿性的金属用于金属图案24。例如,期望的是将具有适合于焊料的可湿性的金属用于金属图案24。
根据第一实施方式,如图1B所示,通过凸起14倒装地安装在布线基板10的上表面的器件芯片12用由金属构成的密封单元26进行密封。由此,因为器件芯片12用由金属构成的密封单元26密封,所以与例如将树脂用作密封单元的情况相比,可以提高器件芯片12的气密性和散热性。因此,可以提高可靠性。
而且,根据第一实施方式,可以实现电子装置小型化和电子装置的高度减小。通过将第一实施方式的电子装置与比较例1的电子装置进行比较,来解释该效果。图2是例示根据比较例1的电子装置的截面图。如图2所示,分开封装SAW器件芯片52a和半导体器件芯片52b的封装60和80分别安装在布线基板50的上表面。
各个封装60包括:SAW器件芯片52a,该SAW器件芯片52a通过凸起64倒装地安装在基板62的上表面;以及密封SAW器件芯片52a的密封单元66和盖68。SAW器件芯片52a通过基板62中的过孔布线70电连接到设置在基板62的下表面的外部端子72。封装80包括通过凸起84倒装地安装在基板82的上表面的半导体器件芯片52b。半导体器件芯片52b通过基板82中的过孔布线(未示出)电连接到设置在基板82的下表面的外部端子86。SAW器件芯片52a和半导体器件芯片52b通过外部端子72和86以及布线基板50中的过孔布线54(这些元件仅沿水平方向例示,并且省略沿垂直方向的例示)电连接到设置在布线基板50的下表面的外部端子56。
填充树脂(mold resin)58被设置为覆盖封装60和80。这里,代替填充树脂58,可以设置树脂顶板,该树脂顶板在封装60和80上延伸。
根据比较例1,分开封装SAW器件芯片52a和半导体器件芯片52b的封装60和80分别安装在布线基板50的上表面。在这种构造中,电子装置变大并且电子装置的高度增大。相反,在第一实施方式中,如图1B所示,多个器件芯片12倒装地安装在布线基板10的上表面。将理解的是,凭借这种构造,与比较例1的图2相比,可以实现电子装置的小型化和电子装置的高度减小。
在SAW器件芯片12a中,形成用于经由IDT激发声波的间隙。当异物、水分等粘附到IDT时,出现频率特性的变化和腐蚀。因此,当SAW器件芯片12a包括在器件芯片12中时,如第一实施方式中提到的,期望的是,器件芯片12通过凸起14倒装地安装在布线基板10的上表面并且用由金属构成的密封单元26密封。由此,如图1B所示,用于经由IDT激发声波的间隙28可以形成在器件芯片12与布线基板10之间,可以提高SAW器件芯片12a的气密性,并且可以控制异物、水分等的粘附。
密封单元26可以是除了焊料之外的金属,并且考虑到气密性、电屏蔽效果、容易密封等,期望的是,密封单元26由焊料构成。而且,除了SAW器件芯片12a之外,器件芯片12还可以包括声波器件芯片。例如,器件芯片12可以包括FBAR(薄膜腔声波谐振器:Film BulkAcoustic Resonator)或SMR(固态安装谐振器:Solidly Mounted Resonator)的压电薄膜谐振器器件芯片。
(第二实施方式)
图3A是例示根据第二实施方式的电子装置的俯视图。图3B是沿图3A的线A-A截取的截面图。在图3A中,透过密封单元32、接合基板30和多个器件芯片12例示凸起14。如图3A和图3B所示,器件芯片12包括SAW器件芯片12a和半导体器件芯片12b。布线基板10例如由诸如HTCC(高温共烧陶瓷:High Temperature Co-fired Ceramics)等的陶瓷构成,并且各个SAW器件芯片12a的压电基板16例如由LT构成。因为陶瓷的热膨胀系数是大约6.5-7.5ppm/℃,并且LT的热膨胀系数是大约10-16ppm/℃,所以SAW器件芯片12a的压电基板16具有的热膨胀系数大于布线基板10的热膨胀系数。即,具有热膨胀系数大于布线基板10的热膨胀系数的压电基板16的SAW器件芯片12a包括在器件芯片12中。
接合基板30在器件芯片12的、位于与布线基板10相对的器件芯片12的面的背面的表面处,接合到器件芯片12。即,单个接合基板30接合到多个器件芯片12。接合基板30具有的外形(form)大于上面设置器件芯片12的区域。期望的是,接合基板30在器件芯片12的、位于与布线基板10相对的器件芯片12的面的背面的整个表面处,接合到所有的器件芯片12,但是接合基板30可以在器件芯片12的、位于与布线基板10相对的器件芯片12的面的背面上的部分表面处,接合到所有的器件芯片12。接合基板30具有的热膨胀系数等于或小于压电基板16的热膨胀系数,压电基板16的热膨胀系数大于布线基板10的热膨胀系数。当压电基板16由例如LT构成时,蓝宝石(5.0ppm/℃)、硅(2.3ppm/℃)、玻璃(大约3ppm/℃)、陶瓷(大约6.5-7.5ppm/℃)、LN(大约15-20ppm/℃)、LT等可以用作接合基板30。这里,各个括号中的数值是热膨胀系数。
设置对器件芯片12进行密封的密封单元32,以便覆盖接合基板30。密封单元32由例如诸如焊料等的金属构成,并且诸如树脂等的绝缘体可以用作密封单元32。因为其他构造与第一实施方式的图1A和图1B的相同,所以省略其描述。
将描述根据第二实施方式的电子装置的制造方法。图4A至图4D是例示根据第二实施方式的电子装置的制造方法的截面图。如图4A所示,将预先制造的SAW制造芯片12a和半导体器件芯片12b接合到接合基板30的一个表面。例如,诸如树脂等的粘合剂可以用于接合。这里,在SAW器件芯片12a和半导体器件芯片12b接合到接合基板30之前,可以减小SAW器件芯片12a和半导体器件芯片12b的厚度。这是因为接合基板30充当支撑基板。通过减小厚度,SAW器件芯片12a和半导体器件芯片12b的厚度可以是20μm。在这种情况下,接合基板30比SAW器件芯片12a和半导体器件芯片12b厚,例如,可以是130μm。
如图4B所示,凸起14形成在SAW器件芯片12a和半导体器件芯片12b的上表面。这里,在图4A中,SAW器件芯片12a和半导体器件芯片12b的、上面预先形成有凸起14的上表面可以接合到接合基板30。然后,将接合基板30划分为期望的单元。接合基板30的划分可以利用例如切割、激光、刻蚀等来执行。
如图4C所示,通过利用凸起14将接合到接合基板30的SAW器件芯片12a和半导体器件芯片12b倒装地安装在预先制备的布线基板10的上表面。
如图4D所示,密封单元32形成在布线基板10上,以便覆盖接合基板30,并且密封器件芯片12。通过在接合基板30上排布焊片并且在270℃加热焊片,可以形成密封单元32。将通过加热焊片而熔融的焊料润湿地涂抹在布线基板10上所设置的金属图案24上,然后固化,并且接合到金属图案24。由此,形成密封单元32,该密封单元对器件芯片12进行密封。根据第二实施方式的电子装置可以通过包括这种制造过程来形成。
接着,将描述根据第二实施方式的电子装置的另一个制造方法。图5A至图5D是例示根据第二实施方式的电子装置的另一个制造方法的截面图。如图5A所示,上面形成有SAW器件芯片的金属膜(未示出)(诸如IDT)和凸起14的压电基板16接合到接合基板30的一个表面。例如,表面活性化接合、经由树脂的接合或经由形成在接合面上的金属膜进行的金属接合可以用作对压电基板16的接合。
如图5B所示,对压电基板16进行切割并分别将该压电基板16分离成SAW器件芯片12a。对接合基板16的切割可以利用例如分割、激光、刻蚀等来执行。如图5C所示,上面形成有凸起14的半导体器件芯片12b接合到接合基板30。如图5D所示,将接合基板30划分为期望的单元。然后,执行由图4C和图4D解释的制造过程。根据第二实施方式的电子装置可以通过包括这种制造过程来形成。
在第一实施方式中,因为用由金属构成的密封单元26来密封器件芯片12,所以可以提高气密性和散热性。因为布线基板10、SAW器件芯片12a、半导体器件芯片12b和密封单元26的热膨胀系数彼此不同,所以对于所有方向(垂直、水平和对角方向)的热膨胀和热收缩的量分别不同。当布线基板10是陶瓷(大约6.5-7.5ppm/℃),SAW器件芯片12a的压电基板16是LT(大约10-16ppm/℃),并且密封单元26由焊料(大约20ppm/℃)构成时,SAW器件芯片12a的热膨胀和热收缩的量相对于布线基板10变大。这里,括号中的数值是热膨胀系数。因为用于倒装安装的凸起14暴露于形成在布线基板10的上表面与器件芯片12之间的间隙28,所以应力施加于凸起14。因此,担心损坏凸起14的接合可靠性。第二实施方式的目标是提高接合可靠性。
将描述对根据第一实施方式和第二实施方式的电子装置执行的模拟,以便说明第二实施方式的效果。图6A是例示执行模拟的、根据第一实施方式的电子装置的俯视图。图6B是沿图6A的线A-A截取的截面图。图7A是例示执行模拟的、根据第二实施方式的电子装置的俯视图。图7B是沿图7A的线A-A截取的截面图。
如图6A和图6B所示,在执行模拟的电子装置中,八个SAW器件芯片12a和一个半导体器件芯片12b倒装地安装在布线基板10的上表面。八个SAW器件芯片12a每四个SAW器件芯片,相对于一个半导体器件芯片12b对称排布。SAW器件芯片12a经由六个凸起14倒装地安装,并且半导体器件芯片12b经由排布为点阵形状的二十四个凸起14倒装地安装。SAW器件芯片12a的压电基板16是厚度为150μm的LT基板。半导体器件芯片12b的半导体基板18是厚度为150μm的Si基板。布线基板10是由厚度为170μm的HTCC构成的陶瓷基板。凸起14是厚度为20μm的金凸起。密封单元26是Sn-Ag焊料。
如图7A和图7B所示,在执行模拟的电子装置中,SAW器件芯片12a的压电基板16是厚度为20μm的LT基板。半导体器件芯片12b的半导体基板18是厚度为20μm的Si基板。接合基板30是厚度为130μm的蓝宝石基板。密封单元32是Sn-Ag焊料。其他构造与图6A和图6B的相同。
假定根据第一实施方式和第二实施方式的这种电子装置在制造之后返回到正常温度,并通过模拟来计算因凸起14而上升的应力的值。图8例示根据第一实施方式的电子装置的模拟结果,并且图9例示根据第二实施方式的电子装置的模拟结果。
应当理解,如图8所示,在第一实施方式中,在SAW器件芯片12a和半导体器件芯片12b中的各芯片中,施加于凸起14的应力出现变化。在各个器件芯片中,将比施加于位于另一个位置的凸起14的应力大的大约8.2x108–1.8x109Pa的应力施加于例如位于四个角的凸起14。认为在各个器件芯片中施加于凸起14的应力出现变化的原因是各个器件芯片单独执行热膨胀和热收缩,因此各个器件芯片受布线基板10和密封单元26的热膨胀和热收缩的影响。
由此,在第一实施方式中,在各个器件芯片中,施加于凸起14的应力出现变化。认为当各个器件芯片的芯片外形和凸起14的排布结构不同时,施加于凸起14的应力的变化趋势针对各个器件芯片而不同。因此,在第一实施方式中,难以控制凸起14的接合可靠性。
将理解,在第二实施方式中,如图9所示,施加于位于用长短交替的虚线围绕的中央区域中的凸起14的应力小,并且变化受到控制。而且,将理解,例如,大约3.8-4.4x109Pa的大应力施加于位于用一长两短交替的短虚线围绕的外周区域中的凸起14。认为在凸起14中出现这种应力的原因如下。即,因为接合基板30接合到多个器件芯片,所以各个器件芯片的热膨胀和热收缩受接合基板30的热膨胀和热收缩的束缚。因此,认为整个器件芯片(即,接合基板30)受布线基板10和密封单元32的热膨胀和热收缩的影响。由此,认为均匀且小的应力施加于位于用长短交替的虚线围绕的中央区域中的凸起14,而大应力施加于位于用一长两短交替的虚线围绕的外周区域中的凸起14。应当理解,因为整个器件芯片(即,接合基板30)受布线基板10和密封单元32的热膨胀和热收缩的影响,所以施加于凸起14的应力可以通过控制接合基板30的尺寸和物理特性(诸如热膨胀系数)而容易地被控制。
即使如图9所示大应力施加于位于用一长两短交替的虚线围绕的外周区域中的凸起14,这些凸起14也被密封单元32按压(因为这些凸起14排布在密封单元32附近),并且由此,使损坏接合可靠性受到控制。而且,因为大应力未施加于位于用长短交替的虚线围绕的中央区域中的凸起14,所以使也损坏关于这些凸起14的接合可靠性受到控制。由此,根据第二实施方式,可以提高接合可靠性。
根据第二实施方式,热膨胀系数等于或小于压电基板16的热膨胀系数的接合基板30接合到包括SAW器件芯片12a的多个器件芯片12,各个SAW器件芯片12a具有压电基板16,该压电基板16具有的热膨胀系数大于布线基板10的热膨胀系数。设置覆盖接合基板30并密封多个器件芯片12的密封单元32。凭借这种构造,如图9所解释,可以提高关于凸起14的接合的可靠性。
接合基板30具有的热膨胀系数应当恰好等于或小于压电基板16的热膨胀系数,压电基板16的热膨胀系数大于布线基板10的热膨胀系数。然而,从提高凸起14的可靠性的观点看,期望的是接合基板30具有的热膨胀系数小于压电基板16的热膨胀系数。
而且,当器件芯片12包括热膨胀系数大于布线基板10的热膨胀系数的两种或更多种基板时,接合基板30具有的热膨胀系数应当恰好等于或小于两种或更多种基板中的至少一种基板的热膨胀系数。期望的是接合基板30具有的热膨胀系数等于或小于所有两种或更多种基板的热膨胀系数。
期望的是接合基板30具有的热导率大于多个器件芯片12中的至少一个器件芯片的基板的热导率。更加期望的是接合基板30具有的热导率大于所有器件芯片的基板的热导率。由此,可以提高散热性。当器件芯片12包括SAW器件芯片12a(各个SAW器件芯片12a具有由LT或LN构成的压电基板16)时,蓝宝石或硅可以用作接合基板30。
期望的是如图9所示,接合基板30大于上面设置有器件芯片12的区域,以便将均匀且小的应力施加于位于中央区域的凸起14并且将大应力施加于位于外周区域的凸起14。
期望的是接合基板30具有的介电常数小于SAW器件芯片12a的压电基板16的介电常数。由此,如日本专利申请第2010-74418号公报中所描述的,可以提高特性。当压电基板16由LT或LN构成时,蓝宝石、硅、陶瓷或玻璃可以用作接合基板30。
即使在密封单元32由诸如焊料等的金属构成或由诸如树脂等的绝缘体构成时,也可以提高关于凸起14的接合的可靠性。如由第一实施方式解释的,考虑到气密性和散热性,期望的是密封单元32由金属构成。而且,考虑到气密性、电屏蔽效果、密封的容易性等,期望的是密封单元32由焊料构成。
当器件芯片12包括SAW器件芯片12a(各个SAW器件芯片12a具有由LT或LN构成的压电基板16)时,因为LT或LN的热膨胀系数较大,所以担心凸起14的接合可靠性。因此,在这种情况下,如第二实施方式中所描述的,期望的是接合基板30接合到多个器件芯片12。
当器件芯片12包括SAW器件芯片12a(各个SAW器件芯片12a具有压电基板16,该压电基板16的热膨胀系数大于布线基板10的热膨胀系数)和半导体器件芯片12b(该半导体器件芯片12b具有半导体基板18,该半导体基板18具有的热膨胀系数小于布线基板10的热膨胀系数)时,期望的是热膨胀系数等于或小于压电基板16的热膨胀系数且等于或大于半导体基板18的热膨胀系数的材料被选作接合基板30的材料。
(第三实施方式)
图10A是例示根据第三实施方式的电子装置的俯视图。图10B是沿图10A的线A-A截取的截面图。在图10A中,透过密封单元32、接合基板30和多个器件芯片12例示凸起14。如图10A和图10B所示,多个器件芯片12可以仅包括SAW器件芯片12a,而不包括半导体器件芯片12b。
图11A至图11D是例示根据第三实施方式的电子装置的制造方法的截面图。如图11A所示,压电基板16接合到接合基板30的一个表面。然后,SAW器件芯片的诸如IDT等的金属膜(未示出)形成在压电基板16的上表面。
如图11B所示,凸起14形成在压电基板16的上表面。如图11C所示,切割压电基板16并分别分离成SAW器件芯片12a。如图11D所示,将接合基板30划分为期望的单元。然后,执行由图4C和图4D解释的制造过程。根据第三实施方式的电子装置可以通过包括这种制造过程形成。
第三实施方式说明了在第二实施方式的电子装置中,多个器件芯片12仅包括SAW器件芯片12a的情况。而且,在第一实施方式的电子装置中,多个电子装置12可以仅包括声波器件芯片。
图12是例示根据第三实施方式的第一变型例的电子装置的截面图。如图12所示,由柯伐合金(Kovar)构成的顶板34例如可以设置在密封单元32上,并且镍(Ni)膜36可以设置为覆盖密封单元32和顶板34。类似地,第一实施方式和第二实施方式中,也可以设置顶板34和镍膜36。
尽管已经详细描述了本发明的实施方式,但是应该理解,在不脱离本发明的精神和范围的情况下,可对这些实施方式进行各种改变、替换和变型。

Claims (7)

1.一种电子装置,该电子装置的特征在于包括:
布线基板;
多个器件芯片,该多个器件芯片通过凸起倒装地安装在所述布线基板的上表面,在所述器件芯片与所述布线基板的上表面之间具有使所述凸起露出的空气间隙,并且所述多个器件芯片包括具有热膨胀系数大于所述布线基板的热膨胀系数的基板的至少一个器件芯片;
单个接合基板,该接合基板被接合到所述多个器件芯片,并且热膨胀系数等于或小于所述至少一个器件芯片中包括的所述基板的热膨胀系数;以及
密封部,该密封部覆盖所述单个接合基板,并且接合到所述布线基板以围绕所述多个器件芯片,并且密封所述多个器件芯片,
其中,所述单个接合基板在所述多个器件芯片的、位于与所述布线基板相对的所述多个器件芯片的面的背面的表面处,接合到所述多个器件芯片中的所有的器件芯片,并且
所述多个器件芯片在彼此之间具有空气间隙。
2.根据权利要求1所述的电子装置,其特征在于,
所述接合基板的热导率大于所述多个器件芯片中的至少一个器件芯片的基板的热导率。
3.根据权利要求1所述的电子装置,其特征在于,
所述接合基板大于设置有所述多个器件芯片的区域。
4.根据权利要求1所述的电子装置,其特征在于,
所述密封部由金属构成。
5.根据权利要求1所述的电子装置,其特征在于,
所述多个器件芯片包括表面声波器件芯片,该表面声波器件芯片包括由钽酸锂或铌酸锂构成的压电基板。
6.根据权利要求4所述的电子装置,其特征在于,
所述密封部由焊料构成。
7.根据权利要求1至6中任意一项所述的电子装置,其特征在于,
所述布线基板由陶瓷构成。
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