CN103959475B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN103959475B
CN103959475B CN201280006360.1A CN201280006360A CN103959475B CN 103959475 B CN103959475 B CN 103959475B CN 201280006360 A CN201280006360 A CN 201280006360A CN 103959475 B CN103959475 B CN 103959475B
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添野明高
山本敏雅
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Toyota Motor Corp
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Abstract

本发明提供一种半导体装置，具备：第一导电型的漂移层；第二导电型的主体层；第一导电型的源极层；第一导电型的漏极层；沟槽栅极，贯通主体层而到达漂移层；第二导电型的第一半导体层，包围沟槽栅极的底部，通过漂移层而与主体层分离；第一导电型的第二半导体层，沿着沟槽栅极的长度方向上的端部设置，该第一导电型的第二半导体层的一端部与主体层相接且另一端部与第一半导体层相接；及连接层，该连接层的一端部与主体层连接且另一端部与第一半导体层连接，并且，该连接层与第二半导体层相接，通过第二半导体层而与沟槽栅极的长度方向上的端部相隔离。

Description

半导体装置
技术领域
本说明书所记载的技术涉及半导体装置。
背景技术
在动力设备用的绝缘栅极型半导体装置中，一般而言，无法同时兼顾高耐压化和低导通电阻化。在沟槽底部设置成浮动结构的MOSFET（Metal-Oxide-Semiconductor Field-Effect Transistor：金氧半场效晶体管）存在高耐压但导通电阻特性低的问题。相对于此，在专利文献1中设置成，将对p型的主体层和沟槽底部的浮动结构进行连接的低浓度的p层沿着沟槽的长度方向上的端部相接。低浓度的p层在栅极电压断开时变为高电阻而维持浮动结构并确保高耐压，另一方面，在栅极电压导通时变为从主体层向浮动结构的载流子供给路径，改善导通电阻特性。
专利文献1：日本特开2007-242852号公报
发明内容
在如专利文献1那样沿着沟槽的长度方向上的端部设置低浓度的p层的情况下，若低浓度的p层与沟槽的长度方向上的端部相接，则在栅极绝缘膜的形成等的半导体装置的制造工序中，有时低浓度的p层会损坏而发生损耗，因而需要较大地确保工艺余量。而且，在检查工序中通过电子显微镜、SIMS来确认低浓度的p层的情况下，若低浓度的p层沿着沟槽的长度方向上的端部接触，则由于沟槽的边缘效应而难以确认低浓度的p层。
本说明书提供一种半导体装置，具备：第一导电型的漂移层；第二导电型的主体层，与漂移层的表面相接，并且，该第二导电型的主体层的一部分露出于半导体基板的表面；第一导电型的源极层，设于主体层的表面的一部分，露出于半导体基板的表面，并通过主体层而与漂移层分离；第一导电型的漏极层，与漂移层的背面相接，并且，露出于半导体基板的背面；沟槽栅极，贯通主体层而到达漂移层；第二导电型的第一半导体层，包围沟槽栅极的底部，并通过漂移层而与主体层分离；第一导电型的第二半导体层，沿着沟槽栅极的长度方向上的端部，该第一导电型的第二半导体层的一端部与主体层相接且另一端部与第一半导体层相接；及连接层，该连接层的一端部与主体层连接且另一端部与第一半导体层连接，该连接层与第二半导体层相接，并通过第二半导体层而与沟槽栅极的长度方向上的端部相隔离。
在上述半导体装置中，在其两端部分别与主体层及第一半导体层连接的连接层通过第二半导体层而与沟槽栅极的长度方向上的端部相隔离。因此，可抑制连接层在半导体装置的制造工序中损坏。而且，不会受到沟槽的边缘效应的影响，能够通过检查来确认连接层的大小等。能够稳定地形成从主体层向浮动结构的载流子供给路径即连接层，能够提供导通电阻特性良好、成品率良好的半导体装置。
连接层也可以是第二导电型的半导体层。第二半导体层的第二导电型的杂质浓度也可以高于漂移层的第二导电型的杂质浓度。
附图说明
图1是实施例1所涉及的半导体装置的纵向剖视图。
图2是沿着图1的Ⅱ-Ⅱ线的剖视图。
图3是沿着图1的Ⅲ-Ⅲ线的剖视图。
图4是表示实施例1所涉及的半导体装置的制造工序的图。
图5是表示实施例1所涉及的半导体装置的制造工序的图。
图6是表示实施例1所涉及的半导体装置的制造工序的图。
图7是表示实施例1所涉及的半导体装置的制造工序的图。
图8是变形例所涉及的半导体装置的纵向剖视图。
图9是以与图3相同的剖面观察变形例所涉及的半导体装置而得到的剖视图。
具体实施方式
本说明书所公开的半导体装置中，只要连接层是具有作为从主体层向浮动结构的载流子供给路径的功能的层即可，可以是第二导电型的半导体层，也可以是导电层。具体而言，除第二导电型的半导体层之外，还能够例示钨等的金属层、导电性的多晶硅层等。
在连接层是第二导电型的半导体层的情况下，该第二导电型的杂质浓度可以低于第一半导体层的第二导电型的杂质浓度，可以高于第一半导体层的第二导电型的杂质浓度，也可以是相同程度。在连接层的第二导电型的杂质浓度较低的情况下，栅极电极导通时的载流子的移动度变小，另一方面，栅极电极断开时的连接层的耗尽化变快，第一半导体层容易变为浮动状态。在连接层的第二导电型的杂质浓度较高的情况下，栅极电极导通时的载流子的移动度变大，另一方面，栅极电极断开时的连接层的耗尽化略微变慢。但是，本说明书所公开的半导体装置中，连接层与第一导电型的第二半导体层相接，连接层的耗尽化也从连接层与第二半导体层的界面进行，因此与现有的半导体装置相比，第一半导体层容易变为浮动状态。
第二半导体层可以是与漂移层不同的层，也可以是与漂移层一体形成的层。而且，第二半导体层的第一导电型的杂质浓度可以高于漂移层的第一导电型的杂质浓度，可以低于漂移层的第一导电型的杂质浓度，也可以是相同程度。在第二半导体层的第一导电型的杂质浓度高于漂移层的第一导电型的杂质浓度的情况下，在栅极电极断开时，第二导电型的半导体层即连接层的耗尽化被进一步促进。而且，也可以在漂移层内的与第二半导体层相反的一侧且与连接层相接的区域形成第一导电型的杂质浓度较高的层。由此，栅极电极断开时的第二导电型的半导体层即连接层的耗尽化被进一步促进。
（实施例1）
图1是实施例1所涉及的半导体装置10。半导体装置10具备：半导体基板100；沟槽栅极120，形成于半导体基板100的表面侧（z轴的正向侧）；及周边沟槽130。半导体基板100以碳化硅为材料。
在半导体基板100上形成有纵向型的MOSFEF。如图1、图2所示，半导体基板100具备：n型的漏极层101；n型的漂移层103；p型的主体层104；n型的源极层109；p型的第一半导体层105；p型的半导体层106；p型的连接层107；及n型的第二半导体层110。主体层104与漂移层103的表面相接，该主体层104的一部分露出于半导体基板100的表面。源极层109设于主体层104的表面的一部分，并且，露出于半导体基板100的表面，通过主体层104而与漂移层103分离。漏极层101与漂移层103的背面相接，并且，露出于半导体基板100的背面。源极层109及主体层104与未图示的源极电连接，漏极层101与未图示的漏极电连接。
第一半导体层105包围沟槽栅极120的底部，通过漂移层103而与主体层104分离。半导体层106包围周边沟槽130的底部，通过漂移层103而从主体层104分离。
第二半导体层110沿着沟槽栅极120的长度方向（x方向）上的端部设置。第二半导体层110的z轴的正方向上的端部与主体层104相接且z轴的负方向上的端部与第一半导体层105相接。而且，第二半导体层110与沟槽栅极120的长度方向（x方向）上的端部相接。
连接层107中，其z轴的正方向上的端部与主体层104连接且其z轴的负方向上的端部与第一半导体层105连接。连接层107在x方向上的一侧与漂移层103相接，并且，在另一侧与第二半导体层110相接，通过第二半导体层110而与沟槽栅极120的长度方向上的端部隔离。连接层107的p型的杂质浓度低于第一半导体层105的p型的杂质浓度。
图3表示与包含第二半导体层110和连接层107在内的xy平面平行的剖面。该剖面中，第二半导体层110和连接层107为岛状。第二半导体层110在x方向上的一侧与沟槽栅极120的侧面相接，在另一侧与连接层107相接，在y方向上与漂移层103相接。
沟槽栅极120具备：沟槽121，从半导体基板100的表面贯通主体层104直至漂移层103；栅极绝缘膜122，形成于沟槽121的内壁面；及栅极电极123，被栅极绝缘膜122覆盖而填充于沟槽121内。栅极电极123经由栅极绝缘膜122而与源极层109和将源极层109与漂移层103分离的范围的主体层104相向。
在栅极电压断开时，耗尽层从连接层107与第二半导体层110及漂移层103之间的pn接合面扩宽，连接层107变为高电阻，第一半导体层105变为浮动状态。在栅极电压断开时对连接层107的p型的杂质浓度、形状及大小进行调整，使得连接层107在半导体基板100的厚度方向（z方向）上的至少一部分比第一半导体层105先被耗尽。第一半导体层105变为浮动状态而使电场强度的峰值分散，因此半导体装置10形成高耐压化。
在耗尽层扩宽的状态下，当将半导体装置10从断开转换为导通时，耗尽层变窄，连接层107变为从主体层104向第一半导体层105的载流子的供给路径。接收来自主体层104的载流子的供给而使第一半导体层105的耗尽层快速变窄，从而降低半导体装置10的导通电阻。
如上所述，根据半导体装置10，能够同时实现以往并无法同时兼顾的高耐压化和低导通电阻化。而且，在半导体装置10中，连接层107与漂移层103和第二半导体层110这双方相接，连接层107的耗尽化不仅从连接层107与漂移层103的pn接合部进行，还从连接层107与第二半导体层110的pn接合部进行。因此，与现有的半导体装置相比，在栅极电压断开时第一半导体层105快速地变为浮动状态。
图4～图7表示半导体装置10的制造方法的一个示例。在该制造方法中，首先，如图4所示，准备以碳化硅为材料的半导体晶片500，该半导体晶片500具备：n层503（成为漂移层103的层）；形成于n层503的表面的p层504（成为主体层104的层）；及形成于p层504的表面的一部分的n层（成为源极层109的层。图4～图7中未图示）。接着，在半导体晶片500的表面形成掩模551，在半导体晶片500的表面侧，通过蚀刻形成贯通p层504而到达n层503的沟槽521、531。接着，在沟槽521、531的底部，沿半导体晶片500的深度方向（z方向）注入p型的杂质离子，形成第一半导体层505（成为第一半导体层105的层）及半导体层506（成为半导体层106的层）。
接着，如图5所示，从半导体晶片500的表面侧沿倾斜方向地向与沟槽521的x方向上的内壁面略微偏离的位置的n层503内注入p型的杂质离子。注入杂质离子的角度是与z方向形成角度θ的方向。根据沟槽521的深度（z方向的宽度）及长度方向（x方向）的宽度来适当调整角度θ。例如，调整角度θ以避免如下情况：由于杂质离子与半导体晶片500的表面（未形成沟槽的面）接触而未到达沟槽521的x方向上的内壁面。
对于作为图5中与x方向相反的一侧的沟槽521的内壁面，也沿倾斜方向进行离子注入，如图6所示，在注入杂质离子的位置形成p层507（成为连接层107的层），在沟槽521和p层507之间形成n层510（成为第二半导体层110的层）。接着，在去除掩模511后，以1700℃左右的温度进行活性化退火。
接着，在通过CVD等向沟槽521、531内填充硅氧化膜之后，对残留于底部附近而不需要的硅氧化膜进行凹蚀而去除。而且，在通过牺牲氧化而在沟槽521、531的内壁面形成硅氧化膜之后，以1300℃左右的温度进行氧化后退火（POA：Post Oxidation Annealing）。而且，向沟槽521、531内填充多晶硅。由此，如图7所示，向沟槽521内填充以多晶硅为材料的栅极电极523而形成沟槽栅极520（成为沟槽栅极120），其中，该栅极电极523处于被以硅氧化物为材料的栅极绝缘膜522覆盖的状态。同时，向沟槽531内填充以多晶硅为材料的导电层533而形成周边沟槽530（成为周边沟槽130），其中，该导电层533处于被以硅氧化物为材料的绝缘膜532覆盖的状态。另外，通过凹蚀去除形成于半导体晶片500的表面等的多余的硅氧化膜及多晶硅。而且，向半导体晶片500的背面注入n型的杂质离子，通过激光退火法进行退火而形成作为漏极层的n层，从而能够制造图1所示的半导体装置10。
如上所述，在半导体装置10的制造方法中，为了形成连接层107等而以1700℃的温度对离子注入后的半导体晶片500进行退火。在以碳化硅为材料的半导体装置10中，为了使注入的离子活性化而需要以高温进行退火，因此需要将制造沟槽栅极120等的工序设为形成连接层107的工序的后工序。因此，在形成沟槽栅极120等的工序中，有时半导体晶片500从沟槽120的内壁面发生损耗。在半导体装置10中，连接层107通过第二半导体层110与沟槽栅极120的长度方向（x方向）上的端部隔离而未与沟槽栅极120相接，因此即使在制造沟槽栅极120等的工序中半导体晶片500发生损耗，连接层107也不会发生损耗。而且，在所制造的半导体装置10的检查工序中，不会受到沟槽121的边缘效应的影响，能够通过检查来确认连接层107的大小等。半导体装置10的导通电阻特性良好，有利于成品率。
（变形例）
为了形成第二半导体层110，可以向靠近沟槽521的x方向的内壁面的位置注入n型的杂质离子。而且，如图8所示，也可以在相对于连接层107而沿x方向与第二半导体层110相向的位置进一步设置n型的半导体层112。n型的半导体层112例如能够如下形成：在向半导体晶片500照射图5所示的p型的杂质离子的工序之前，同样地，从半导体晶片500的表面侧沿倾斜方向地向与沟槽521的x方向上的内壁面略微偏离的位置的n层503内注入n型的杂质离子。而且，如图9所示，也可以使第一半导体层210被连接层207包围而与漂移层103隔离。
而且，连接层107的p型的杂质浓度也可以是与第一半导体层105相同的程度或比第一半导体层105高的浓度。连接层107与漂移层103及第二半导体层110相接，连接层107的耗尽化从与这双方的pn接合面进行。因此，即使在连接层107的p型的杂质浓度较高的情况下，第一半导体层105也容易变为浮动状态。而且，也可以取代连接层107而使用多晶硅层、钨等金属层等导电层作为连接层。此时，连接层也可以埋入于漂移层。在将连接层埋入于漂移层而形成的情况下，第二半导体层也可以是漂移层的一部分。
以上，对本发明的实施例详细地进行了说明，但这些只是例示，并未限定权利要求。权利要求所记载的技术中，包含对以上所例示的具体例进行的各种变形、变更。
本说明书或附图所说明的技术要素可单独或通过各种组合来发挥技术上的实用性，并不限于申请时权利要求记载的组合。而且，本说明书或附图所例示的技术可同时实现多个目的，实现其中一个目的本身具有技术上的实用性。

Claims (3)

1.一种半导体装置，具备半导体基板，所述半导体装置的特征在于，具备：
第一导电型的漂移层，设于所述半导体基板；
第二导电型的主体层，设于所述半导体基板，该主体层与所述漂移层的表面相接，并且一部分露出于所述半导体基板的表面；
第一导电型的源极层，设于所述半导体基板，该源极层设于所述主体层的表面的一部分，露出于所述半导体基板的表面，并通过所述主体层而与所述漂移层分离；
第一导电型的漏极层，设于所述半导体基板，该漏极层与所述漂移层的背面相接，并且露出于所述半导体基板的背面；
沟槽栅极，从所述半导体基板的表面贯通所述主体层而到达所述漂移层；
第二导电型的第一半导体层，设于所述半导体基板，该第一半导体层包围所述沟槽栅极的底部，并通过所述漂移层而与所述主体层分离；
第一导电型的第二半导体层，设于所述半导体基板，该第二半导体层沿着所述沟槽栅极的长度方向上的端部设置，且，一端部与所述主体层相接，而另一端部则与所述第一半导体层相接；及
连接层，设于所述半导体基板，该连接层的一端部与所述主体层连接，而另一端部则与所述第一半导体层连接，且，该连接层与所述第二半导体层相接，并通过所述第二半导体层而与所述沟槽栅极的长度方向上的端部相隔离。
2.根据权利要求1所述的半导体装置，其中，
连接层是第二导电型的半导体层。
3.根据权利要求1或2所述的半导体装置，其中，
第二半导体层的第一导电型的杂质浓度高于漂移层的第一导电型的杂质浓度。
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