CN113782609A - 一种衬底电荷耦合的1200v体硅ldmos及其制备方法 - Google Patents

一种衬底电荷耦合的1200v体硅ldmos及其制备方法 Download PDF

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CN113782609A
CN113782609A CN202111055507.3A CN202111055507A CN113782609A CN 113782609 A CN113782609 A CN 113782609A CN 202111055507 A CN202111055507 A CN 202111055507A CN 113782609 A CN113782609 A CN 113782609A
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张龙
崔永久
马杰
王肖娜
袁帅
祝靖
孙伟锋
时龙兴
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Southeast University-Wuxi Institute Of Integrated Circuit Technology
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Abstract

本发明是一种衬底电荷耦合的1200V体硅LDMOS及其制备方法，在P型衬底上设有N型SN埋层，在N型SN埋层上方且靠近漏极侧设有N型DN埋层，在N型SN埋层上方且靠近源极侧设有5个P型BP埋层。P型BP埋层和N型DN埋层上方设有P型P‑well体区、N型漂移区和N型N‑well缓冲层。漂移区上方设有场氧化层、多晶硅栅、二氧化硅氧化层和金属场板，其中金属场板横跨于场氧化层上方，多晶硅栅自源极N型重掺杂区上方经过P型P‑well体区，延伸至场氧化层上方。源极N型重掺杂区和源极P型重掺杂区通过源极金属和源极相连，漏极N型重掺杂区通过漏极金属和漏极相连。本发明结构在低衬底电阻率的衬底材料下即可实现1200V的耐压需求。

Description

一种衬底电荷耦合的1200V体硅LDMOS及其制备方法
技术领域
本发明涉及功率半导体器件技术领域，涉及一种衬底电荷耦合的1200V体硅LDMOS(横向双扩散MOS晶体管)及其制备方法。
背景技术
随着功率半导体技术的发展，高压集成电路被广泛应用于电源开关、电机驱动、汽车电子和新能源发电等领域。而高压集成路中很关键的一项技术设计就是高压LDMOS器件的设计。高压体硅LDMOS由于其工艺相对简单且与其他工艺相兼容的优点，在高压集成电路中得到了广泛的应用。对于1200V的高压集成电路，就需要耐压等级为1200V的LDMOS来实现电平移位的功能。由于1200V耐压等级的LDMOS耐压要求高，因此在设计1200V时的时需要从横向耐压和纵向耐压两个方面来考虑。对于横向耐压的设计要求，可以通过采用场板、RESURF技术和场限环等终端技术来提高耐压。对于纵向耐压的设计，目前最常见的技术还是增加衬底电阻率来满足纵向耐压的需求。但是高衬底电阻率的衬底材料又有价格昂贵和均匀性差的缺点。因此具有高耐压能力的1200V体硅LDMOS急需被研究。
发明内容
技术问题：本发明针对上述问题，提出一种衬底电荷耦合的1200V体硅LDMOS及其制备方法，用于制备具有高耐压能力的1200V体硅LDMOS。
技术方案：本发明的一种衬底电荷耦合的1200V体硅LDMOS包括P型衬底，在P型衬底中设有N型SN埋层，在N型SN埋层上方且靠近漏极侧设有N型DN埋层，在N型SN埋层上方且靠近源极侧设有5个P型BP埋层，P型BP埋层和N型DN埋层上方设有P型P-well体区、N型漂移区和N型N-well缓冲层，其中P型P-well体区内设有源极N型重掺杂区和源极P型重掺杂区，N型N-well缓冲层内设有漏极N型重掺杂区；N型漂移区上方设有场氧化层、多晶硅栅、二氧化硅氧化层和金属场板，其中金属场板横跨于场氧化层上方，多晶硅栅自源极N型重掺杂区上方经过P型P-well体区延伸至场氧化层上方；源极N型重掺杂区和源极P型重掺杂区通过源极金属和源极相连，漏极N型重掺杂区通过漏极金属和漏极相连。
所述的N型SN埋层通过两次外延离子注入形成，两次外延的厚度分别为6.0～8.0um。
所述的N型SN埋层的离子注入的窗口宽度为2.0～2.5um，相邻离子注入窗口的间距为16.0～18.0um。
本发明的一种衬底电荷耦合的1200V体硅LDMOS的制备方法的具体步骤如下：
步骤1：在P型衬底进行N型离子注入后，第一次生长厚度为8um的P型外延层；
步骤2：在第一次生长的P型外延层进行N型离子注入后，第二次生长厚度为8um的P型外延层；
步骤3：在第二次生长的P型外延层进行N型离子注入后，退火形成N型SN埋层，接着第三次生长厚度为6um的P型外延层；
步骤4：在第三次生长的P型外延层进行N型离子注入后，退火形成N型DN埋层，在第三次生长的P型外延层进行P型离子注入后，退火形成P型BP埋层，接着第四次生长厚度为6um的P型外延层；
步骤5：在第四次生长的P型外延层进行N型离子注入后，退火形成N型漂移区，接着继续进行N型离子注入，退火形成N型N-well缓冲层；
步骤6：在第四次生长的P型外延层进行P型离子注入后，退火形成P型P-well体区；
步骤7：在硅区表面氧化刻蚀形成场氧化层，氧化刻蚀形成栅氧化层，淀积刻蚀形成多晶硅栅；
步骤8：在硅区表面自对准N型离子注入形成源极N型重掺杂区和漏极N型重掺杂区；在硅区表面自对准P型离子注入形成源极P型重掺杂区；
步骤9：在硅区表面氧化生长二氧化硅氧化层，刻蚀二氧化硅氧化层形成接触孔，然后淀积金属铝，刻蚀金属铝形成器件的漏极接触、源极接触和金属场板；
步骤10：在硅区表面继续氧化生长二氧化硅氧化层，刻蚀二氧化硅氧化层形成接触孔，然后淀积金属铝，刻蚀金属铝形成器件的漏极接触与源极接触；
步骤11：在二氧化硅氧化层上淀积金属铝，刻蚀金属铝形成器件的漏极与源极。
有益效果：与现有技术相比，本发明结构具有如下优点：
1.本发明通过衬底电荷耦合结构，在低衬底电阻率衬底材料下，即可实现1200V的耐压需求。在低衬底电阻率衬底材料下，器件的纵向耐压(BVV)小于1200V，虽然通过拉长器件的漂移区长度和采用终端技术可以提高器件的横向耐压(BVL)，使BVL的值大于1200V，但是BVV<1200V<BVL，因此器件在不到1200V时就在体内击穿，使器件最终的BV<1200V，因此要使体硅LDMOS的BV＞1200V，就需要采用高衬底电阻率的衬底材料。通过采用具有电荷耦合作用的SN埋层，可以在低衬底电阻率的基础上，使漏端纵向电场分布从三角形分布往矩形分布变化，进而提高器件的纵向耐压。因此，本发明结构在低衬底电阻率的衬底材料下即可实现1200V的耐压需求。
2.本发明方案通过使用低衬底电阻率的衬底材料，降低了衬底材料的成本，提高了衬底材料的均匀性。同时本发明方案和目前的工艺完全兼容，没有增加制造工艺的难度。
附图说明
图1所示为本发明的1200V体硅LDMOS结构图。
图2所示为本发明结构和传统结构漏端纵向电场分布示意图。
图3所示为本发明结构和传统机构击穿特性图。
图中有：P型衬底1、P型BP埋层2、N型DN埋层3、P型P-well体区4、源极P型重掺杂区5、源极N型重掺杂区6、N型N-well缓冲层7、漏极N型重掺杂区8、N型漂移区9、源极金属10、多晶硅栅11、金属场板12、二氧化硅氧化层13、场氧化层14、漏极金属15、N型SN埋层16。
具体实施方式
下面结合附图，对本发明做详细说明。
本发明的一种衬底电荷耦合的1200V体硅LDMOS，包括P型衬底1，在P型衬底1上设有N型SN埋层16，在N型SN埋层16上方且靠近漏极侧设有N型DN埋层3，在N型SN埋层16上方且靠近源极侧设有5个P型BP埋层2。P型BP埋层2和N型DN埋层3上方设有P型P-well体区4、N型漂移区9和N型N-well缓冲层7，其中P型P-well体区4内设有源极N型重掺杂区6和源极P型重掺杂区5，N型N-well缓冲层7内设有漏极N型重掺杂区8。N型漂移区9上方设有场氧化层14、多晶硅栅11、二氧化硅氧化层14和金属场板12，其中金属场板12横跨于场氧化层14上方，多晶硅栅11自源极N型重掺杂区6上方经过P型P-well体区4，延伸至场氧化层14上方。源极N型重掺杂区6和源极P型重掺杂区5通过源极金属10和源极相连，漏极N型重掺杂区8通过漏极金属15和漏极相连。
所述的N型SN埋层16通过两次外延离子注入形成，两次外延的厚度都为8um。
所述的N型SN埋层16的离子注入的窗口宽度为2.0～2.5um，相邻离子注入窗口的间距为16.0～18.0um。
本发明的一种衬底电荷耦合的1200V体硅LDMOS的制备方法具体步骤如下：
步骤1：在P型衬底1进行N型离子注入后，第一次生长厚度为8um的P型外延层；
步骤2：在第一次生长的P型外延层进行N型离子注入后，第二次生长厚度为8um的P型外延层；
步骤3：在第二次生长的P型外延层进行N型离子注入后，退火形成N型SN埋层16，接着第三次生长厚度为6um的P型外延层；
步骤4：在第三次生长的P型外延层进行N型离子注入后，退火形成N型DN埋层3，在第三次生长的P型外延层进行P型离子注入后，退火形成P型BP埋层2，接着第四次生长厚度为6um的P型外延层；
步骤5：在第四次生长的P型外延层进行N型离子注入后，退火形成N型漂移区9，接着继续进行N型离子注入，退火形成N型N-well缓冲层7；
步骤6：在第四次生长的P型外延层进行P型离子注入后，退火形成P型P-well体区4；
步骤7：在硅区表面氧化刻蚀形成场氧化层14，氧化刻蚀形成栅氧化层，淀积刻蚀形成多晶硅栅11；
步骤8：在硅区表面自对准N型离子注入形成源极N型重掺杂区6和漏极N型重掺杂区8；在硅区表面自对准P型离子注入形成源极P型重掺杂区5；
步骤9：在硅区表面氧化生长二氧化硅氧化层13，刻蚀二氧化硅形成接触孔，然后淀积金属铝，刻蚀金属铝形成器件的漏极接触、源极接触和金属场板；
步骤10：在硅区表面继续氧化生长二氧化硅氧化层13，刻蚀二氧化硅形成接触孔，然后淀积金属铝，刻蚀金属铝形成器件的漏极接触与源极接触；
步骤11：在二氧化硅氧化层13上淀积金属铝，刻蚀金属铝形成器件的漏极与源极。
下面结合附图对本发明做进一步说明。
对于1200V体硅LDMOS，其耐压由纵向耐压(BVV)和横向耐压(BVL)两部分组成。当BVV<1200V<BVL时，此时器件的击穿电压BV<1200V，且此时的击穿点位于器件体内。当BVL<1200V<BVV时，此时器件的击穿电压BV<1200V，且此时的击穿点位于器件表面。因此要使器件的击穿电压BV>1200V，需要满足BVV>1200V且BVL>1200V。对于器件的纵向耐压，主要由衬底的电阻率决定，且衬底的电阻率越高，器件的纵向耐压越高。本发明提出的衬底电荷耦合的1200V体硅LDMOS在传统1200V体硅LDMOS的基础上，增加了由三次离子注入形成的N型SN埋层16。SN埋层16的引入，可以辅助P型衬底1和SN埋层16之间的耗尽，促使纵向电场的分布由三角形电场分布往矩形电场分布过渡。图2所示为本发明结构和传统结构漏端的电场分布示意图，如图所示，本发明结构的纵向电场分布和传统结构相比，更加趋近于矩形分布，电场分布围成的线下面积更大，因此本发明结构具有更高的纵向耐压。在保持漂移区长度以及终端设计不变的情况下，本发明结构由于纵向耐压的提高，器件的击穿电压得到明显的提升。如图3所示，在相同的衬底电阻率情况下，本发明结构的击穿电压为1529V，传统结构的击穿电压为1094V，同比提高39.7％。
同时SN埋层采用的外延离子注入技术和目前的生产工艺完全兼容，可以直接利用目前的生产工艺，并没有增加生产工艺的难度，具有一定的可行性。

Claims (4)

1.一种衬底电荷耦合的1200V体硅LDMOS，其特征在于，该LDMOS包括P型衬底(1)，在P型衬底(1)中设有N型SN埋层(16)，在N型SN埋层(16)上方且靠近漏极侧设有N型DN埋层(3)，在N型SN埋层(16)上方且靠近源极侧设有5个P型BP埋层(2)，P型BP埋层(2)和N型DN埋层(3)上方设有P型P-well体区(4)、N型漂移区(9)和N型N-well缓冲层(7)，其中P型P-well体区(4)内设有源极N型重掺杂区(6)和源极P型重掺杂区(5)，N型N-well缓冲层(7)内设有漏极N型重掺杂区(8)；N型漂移区(9)上方设有场氧化层(14)、多晶硅栅(11)、二氧化硅氧化层(13)和金属场板(12)，其中金属场板(12)横跨于场氧化层(14)上方，多晶硅栅(11)自源极N型重掺杂区(6)上方经过P型P-well体区(4)延伸至场氧化层(14)上方；源极N型重掺杂区(6)和源极P型重掺杂区(5)通过源极金属(10)和源极相连，漏极N型重掺杂区(8)通过漏极金属(15)和漏极相连。
2.根据权利要求1所述的一种衬底电荷耦合的1200V体硅LDMOS，其特征在于，所述的N型SN埋层(16)通过两次外延离子注入形成，两次外延的厚度分别为6.0～8.0um。
3.根据权利要求1或2所述的一种衬底电荷耦合的1200V体硅LDMOS，其特征在于，所述的N型SN埋层(16)的离子注入的窗口宽度为2.0～2.5um，相邻离子注入窗口的间距为16.0～18.0um。
4.一种如权利要求1所述的一种衬底电荷耦合的1200V体硅LDMOS的制备方法，其制备方法的具体步骤如下：
步骤1：在P型衬底(1)进行N型离子注入后，第一次生长厚度为8um的P型外延层；
步骤2：在第一次生长的P型外延层进行N型离子注入后，第二次生长厚度为8um的P型外延层；
步骤3：在第二次生长的P型外延层进行N型离子注入后，退火形成N型SN埋层(16)，接着第三次生长厚度为6um的P型外延层；
步骤4：在第三次生长的P型外延层进行N型离子注入后，退火形成N型DN埋层(3)，在第三次生长的P型外延层进行P型离子注入后，退火形成P型BP埋层(2)，接着第四次生长厚度为6um的P型外延层；
步骤5：在第四次生长的P型外延层进行N型离子注入后，退火形成N型漂移区(9)，接着继续进行N型离子注入，退火形成N型N-well缓冲层(7)；
步骤6：在第四次生长的P型外延层进行P型离子注入后，退火形成P型P-well体区(4)；
步骤7：在硅区表面氧化刻蚀形成场氧化层(14)，氧化刻蚀形成栅氧化层，淀积刻蚀形成多晶硅栅(11)；
步骤8：在硅区表面自对准N型离子注入形成源极N型重掺杂区(6)和漏极N型重掺杂区(8)；在硅区表面自对准P型离子注入形成源极P型重掺杂区(5)；
步骤9：在硅区表面氧化生长二氧化硅氧化层(13)，刻蚀二氧化硅氧化层形成接触孔，然后淀积金属铝，刻蚀金属铝形成器件的漏极接触、源极接触和金属场板；
步骤10：在硅区表面继续氧化生长二氧化硅氧化层(13)，刻蚀二氧化硅氧化层形成接触孔，然后淀积金属铝，刻蚀金属铝形成器件的漏极接触与源极接触；
步骤11：在二氧化硅氧化层(13)上淀积金属铝，刻蚀金属铝形成器件的漏极与源极。
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