CN105226101A - 结型场效应晶体管及其制造方法 - Google Patents

结型场效应晶体管及其制造方法 Download PDF

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CN105226101A
CN105226101A CN201410307930.1A CN201410307930A CN105226101A CN 105226101 A CN105226101 A CN 105226101A CN 201410307930 A CN201410307930 A CN 201410307930A CN 105226101 A CN105226101 A CN 105226101A
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CN105226101B (zh
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韩广涛
孙贵鹏
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CSMC Technologies Fab2 Co Ltd
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Wuxi CSMC Semiconductor Co Ltd
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Priority to PCT/CN2015/082761 priority patent/WO2016000600A1/zh
Priority to US15/318,857 priority patent/US9947785B2/en
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Abstract

本发明涉及一种结型场效应晶体管，包括衬底，衬底内的埋层，埋层上的第一阱区和第二阱区，第一阱区内的源极引出区、漏极引出区、第一栅极引出区，以及第二阱区内的第二栅极引出区；所述第一阱区的表面设有肖特基结面，所述肖特基结面位于所述第一栅极引出区和所述漏极引出区之间，并通过隔离结构与所述第一栅极引出区和漏极引出区进行隔离。本发明还涉及一种结型场效应晶体管的制造方法。本发明利用设于N阱上方的肖特基结面，在N阱的N型漂移区内形成空乏区，使得漂移区被耗尽，从而达到提高崩溃电压的目的。

Description

结型场效应晶体管及其制造方法
技术领域
本发明涉及半导体器件，特别是涉及一种结型场效应晶体管，还涉及一种结型场效应晶体管的制造方法。
背景技术
结型场效应晶体管(JFET)是电路中常用的一种元器件。在部分应用场合，需要JFET具有较高的崩溃电压。
发明内容
基于此，有必要提供一种具高崩溃电压的结型场效应晶体管。
一种结型场效应晶体管，包括衬底，衬底内的埋层，埋层上的第一阱区和第二阱区，第一阱区内的源极引出区、漏极引出区、第一栅极引出区，以及第二阱区内的第二栅极引出区；所述衬底为第二掺杂类型，所述埋层包括第二掺杂类型埋层，所述第一阱区为第一掺杂类型，所述第二阱区为第二掺杂类型，所述第一栅极引出区和第二栅极引出区为第二掺杂类型，所述源极引出区和漏极引出区为第一掺杂类型，所述第一掺杂类型和第二掺杂类型的导电类型相反；所述第一阱区的表面设有肖特基结面，所述肖特基结面位于所述第一栅极引出区和所述漏极引出区之间，并通过隔离结构与所述第一栅极引出区和漏极引出区进行隔离。
在其中一个实施例中，所述第一掺杂类型为N型，所述第二掺杂类型为P型。
在其中一个实施例中，所述第二掺杂类型埋层包括埋层P阱和P型岛，所述埋层P阱从第二阱区下方延伸至第一阱区下方，所述P型岛位于所述第一阱区下方、与埋层P阱之间被所述衬底隔开。
在其中一个实施例中，所述P型岛和所述埋层P阱通过同一光刻和离子注入步骤形成。
在其中一个实施例中，还包括位于所述第一阱区内的第二掺杂类型注入区，所述第一栅极引出区位于所述第二掺杂类型注入区内。
在其中一个实施例中，所述肖特基结面是与金属或金属硅化物直接接触形成。
在其中一个实施例中，所述隔离结构是场氧结构。
还有必要提供一种结型场效应晶体管的制造方法。
一种结型场效应晶体管的制造方法，包括下列步骤：提供衬底；通过离子注入在衬底内形成埋层；通过外延工艺在埋层上形成外延层；通过离子注入和推阱在外延层内形成第一阱区和第二阱区；在第一阱区和第二阱区表面形成隔离结构，作为后续栅极、源极及漏极注入的对准基础；形成栅极结构，包括第一阱区内的第一栅极引出区、第二阱区内的第二栅极引出区、第一栅极引出区和第二栅极引出区上的栅氧及栅氧上的多晶硅栅极；通过离子注入在第一阱区内形成源极引出区和漏极引出区；通过热退火对注入的离子进行激活；在第一阱区上形成金属或合金结构，所述隔离结构中位于第一栅极引出区和漏极引出区之间的部分为不连续的结构，使得位于这一区域的所述金属或合金结构与下方的第一阱区直接接触形成肖特基结面；其中，所述衬底为第二掺杂类型，所述埋层包括第二掺杂类型埋层，所述第一阱区为第一掺杂类型，所述第二阱区为第二掺杂类型，所述第一栅极引出区和第二栅极引出区为第二掺杂类型，所述源极引出区和漏极引出区为第一掺杂类型，所述第一掺杂类型和第二掺杂类型的导电类型相反。
在其中一个实施例中，所述第一掺杂类型为N型，所述第二掺杂类型为P型。
在其中一个实施例中，所述通过离子注入在衬底内形成埋层的步骤，是光刻定义出埋层P阱和P型岛的注入窗口后，通过离子注入形成第一阱区下方的P型岛和从第二阱区下方延伸至第一阱区下方的埋层P阱，所述P型岛与埋层P阱之间被所述衬底隔开。
在其中一个实施例中，所述在第一阱区和第二阱区表面形成隔离结构的步骤之后，所述通过离子注入在第一阱区内形成源极引出区、在第二阱区内形成漏极引出区的步骤之前，还包括通过离子注入在第一阱区内形成第二掺杂类型注入区的步骤，所述第一栅极引出区位于所述第二掺杂类型注入区内。
在其中一个实施例中，所述隔离结构是场氧结构。
上述结型场效应晶体管，利用设于N阱上方的肖特基结面，在N阱的N型漂移区内形成空乏区，使得漂移区被耗尽，从而达到提高崩溃电压的目的。
附图说明
图1是一实施例中结型场效应晶体管的结构示意图；
图2是一实施例中结型场效应晶体管的制造方法的流程图。
具体实施方式
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
图1一实施例中结型场效应晶体管的结构示意图，包括衬底10，衬底10内的埋层，埋层上的第一阱区32和第二阱区34，第一阱区32内的第一栅极引出区42、源极引出区50及漏极引出区60，以及第二阱区内34的第二栅极引出区44。在本实施例中，埋层包括埋层P阱22，第一阱区32为N阱，第二阱区34为P阱，第一栅极引出区42和第二栅极引出区44为P+引出区，源极引出区50和漏极引出区60为N+引出区。第一阱区32的表面设有肖特基结面70，具体是位于第一栅极引出区42和漏极引出区60之间，并通过隔离结构(例如场氧)与第一栅极引出区42和漏极引出区60进行隔离。在本实施例中，第一阱区32是深N阱，作为耐高压的N型漂移区，两端分别通过N+的源极引出区50和漏极引出区60引出作为源极、漏极。
上述结型场效应晶体管，利用设于N阱上方的肖特基结面70，在N阱的N型漂移区内形成空乏区，使得漂移区被耗尽，从而达到提高崩溃电压的目的。肖特基结面70可以设置多个，相互之间通过隔离结构隔离，并通过调整肖特基结面70的个数、尺寸大小及间距，使N型漂移区能够有效耗尽。
肖特基结面70可以采用习知的能够与N型硅形成肖特基结面的金属或金属硅化物(包括Salicide、Silicide及Polycide)，例如铝、硅化钴(cobaltsilicide)等。
在设置了肖特基结面70的情况下，若N型漂移区仍不能完全耗尽，还可以在第一阱区32的下方通过离子注入形成P型岛24。P型岛24和埋层P阱22可以利用同一光刻和离子注入步骤形成，无需额外增加光刻/离子注入步骤，以节约成本。P型岛24主要设于第一阱区32下方靠近漏极引出区60的位置附近，与埋层P阱22相互分隔，并可以依需求设置多个，多个P型岛24之间也相互分隔。通过合理设计埋层P阱光刻的光刻版，调整P型岛24的个数、尺寸大小及间距，注入形成合适的岛状，从而调整P型岛24的有效浓度，并与肖特基结面70共同使N型漂移区完全耗尽，满足高崩溃电压的需求。
在图1所示实施例中，结型场效应晶体管还包括位于第一阱区32内的P型注入区43，第一栅极引出区42位于P型注入区43内。设置P型注入区43可以起到调整夹断电压的效果。
本发明还提供一种上述结型场效应晶体管的制造方法，包括下列步骤：
S110，提供衬底。
在本实施例中是提供P型衬底。
S120，通过离子注入在衬底内形成埋层。
在本实施例中，埋层包括埋层P阱和P型岛。通过光刻定义出埋层P阱和P型岛的注入窗口后，通过注入P型离子形成埋层P阱和P型岛，P型岛与埋层P阱之间被衬底隔开。
S130，通过外延工艺在埋层上形成外延层。
S140，通过离子注入和推阱在外延层内形成第一阱区和第二阱区。
光刻后分别注入N型离子和P型离子，推阱后形成N阱作为第一阱区、P阱作为第二阱区。步骤S120中形成的埋层P阱从器件内部结构上来看，是从N阱下方延伸至P阱下方，P型岛位于N阱下方。
S150，在第一阱区和第二阱区表面形成隔离结构。
隔离结构可以作为后续栅极、源极及漏极注入的对准基础。在本实施例中，使用场氧作为隔离结构。
S160，形成栅极结构。
在本实施例中，包括通过离子注入形成N阱内P+的第一栅极引出区、P阱内P+的第二栅极引出区，通过热氧化在第一栅极引出区和第二栅极引出区上形成栅氧，通过淀积在栅氧上形成多晶硅栅极。在本实施例中，还包括在多晶硅栅极的侧壁形成侧墙结构(Spacer)。
S170，通过离子注入在第一阱区内形成源极引出区和漏极引出区。
N+的源极引出区与第一栅极引出区、与第二栅极引出区之间都有隔离结构将其隔离。N+的漏极引出区与第一栅极引出区之间同样被隔离结构隔离，但漏极引出区与P+的第一栅极引出区之间的隔离结构是不连续的，中间的部分N阱未被隔离结构所覆盖。
S180，通过热退火对注入的离子进行激活。
S190，在第一阱区上形成金属或合金结构，并与下方的第一阱区直接接触形成肖特基结面。
形成于漏极引出区与第一栅极引出区之间的隔离结构上方的金属/合金结构，与露出的部分N阱直接接触从而形成肖特基结面。该金属或合金结构可以采用习知的能够与N型硅形成肖特基结面的金属或金属硅化物(包括Salicide、Silicide及Polycide)，例如铝、硅化钴(cobaltsilicide)等。
上述结型场效应晶体管的制造方法，JFET中与肖特基结面共同作用使N型漂移区完全耗尽的P型岛，是与P型埋层在同一光刻和离子注入步骤中形成，S190步骤中形成的金属或合金结构也无需额外增加工艺步骤，因此在提高了崩溃电压的基础上，无需增加光刻成本。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (12)

1.一种结型场效应晶体管，包括衬底，衬底内的埋层，埋层上的第一阱区和第二阱区，第一阱区内的源极引出区、漏极引出区、第一栅极引出区，以及第二阱区内的第二栅极引出区；所述衬底为第二掺杂类型，所述埋层包括第二掺杂类型埋层，所述第一阱区为第一掺杂类型，所述第二阱区为第二掺杂类型，所述第一栅极引出区和第二栅极引出区为第二掺杂类型，所述源极引出区和漏极引出区为第一掺杂类型，所述第一掺杂类型和第二掺杂类型的导电类型相反；其特征在于，所述第一阱区的表面设有肖特基结面，所述肖特基结面位于所述第一栅极引出区和所述漏极引出区之间，并通过隔离结构与所述第一栅极引出区和漏极引出区进行隔离。
2.根据权利要求1所述的结型场效应晶体管，其特征在于，所述第一掺杂类型为N型，所述第二掺杂类型为P型。
3.根据权利要求2所述的结型场效应晶体管，其特征在于，所述第二掺杂类型埋层包括埋层P阱和P型岛，所述埋层P阱从第二阱区下方延伸至第一阱区下方，所述P型岛位于所述第一阱区下方、与埋层P阱之间被所述衬底隔开。
4.根据权利要求3所述的结型场效应晶体管，其特征在于，所述P型岛和所述埋层P阱通过同一光刻和离子注入步骤形成。
5.根据权利要求1所述的结型场效应晶体管，其特征在于，还包括位于所述第一阱区内的第二掺杂类型注入区，所述第一栅极引出区位于所述第二掺杂类型注入区内。
6.根据权利要求1所述的结型场效应晶体管，其特征在于，所述肖特基结面是与金属或金属硅化物直接接触形成。
7.根据权利要求1所述的结型场效应晶体管，其特征在于，所述隔离结构是场氧结构。
8.一种结型场效应晶体管的制造方法，包括下列步骤：
提供衬底；
通过离子注入在衬底内形成埋层；
通过外延工艺在埋层上形成外延层；
通过离子注入和推阱在外延层内形成第一阱区和第二阱区；
在第一阱区和第二阱区表面形成隔离结构，作为后续栅极、源极及漏极注入的对准基础；
形成栅极结构，包括第一阱区内的第一栅极引出区、第二阱区内的第二栅极引出区、第一栅极引出区和第二栅极引出区上的栅氧及栅氧上的多晶硅栅极；
通过离子注入在第一阱区内形成源极引出区和漏极引出区；
通过热退火对注入的离子进行激活；
在第一阱区上形成金属或合金结构，所述隔离结构中位于第一栅极引出区和漏极引出区之间的部分为不连续的结构，使得位于这一区域的所述金属或合金结构与下方的第一阱区直接接触形成肖特基结面；其中，
所述衬底为第二掺杂类型，所述埋层包括第二掺杂类型埋层，所述第一阱区为第一掺杂类型，所述第二阱区为第二掺杂类型，所述第一栅极引出区和第二栅极引出区为第二掺杂类型，所述源极引出区和漏极引出区为第一掺杂类型，所述第一掺杂类型和第二掺杂类型的导电类型相反。
9.根据权利要求8所述的结型场效应晶体管的制造方法，其特征在于，所述第一掺杂类型为N型，所述第二掺杂类型为P型。
10.根据权利要求9所述的结型场效应晶体管的制造方法，其特征在于，所述通过离子注入在衬底内形成埋层的步骤，是光刻定义出埋层P阱和P型岛的注入窗口后，通过离子注入形成第一阱区下方的P型岛和从第二阱区下方延伸至第一阱区下方的埋层P阱，所述P型岛与埋层P阱之间被所述衬底隔开。
11.根据权利要求8所述的结型场效应晶体管的制造方法，其特征在于，所述在第一阱区和第二阱区表面形成隔离结构的步骤之后，所述通过离子注入在第一阱区内形成源极引出区、在第二阱区内形成漏极引出区的步骤之前，还包括通过离子注入在第一阱区内形成第二掺杂类型注入区的步骤，所述第一栅极引出区位于所述第二掺杂类型注入区内。
12.根据权利要求8所述的结型场效应晶体管的制造方法，其特征在于，所述隔离结构是场氧结构。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111463258A (zh) * 2019-01-18 2020-07-28 新唐科技股份有限公司 晶体管元件
CN111599861A (zh) * 2019-02-20 2020-08-28 新唐科技股份有限公司 半导体结构及其制造方法
CN111697058A (zh) * 2020-06-09 2020-09-22 杰华特微电子（杭州）有限公司 半导体器件
CN111696984A (zh) * 2020-06-09 2020-09-22 杰华特微电子（杭州）有限公司 半导体器件及其制作方法
CN111900197A (zh) * 2020-07-29 2020-11-06 杰华特微电子（杭州）有限公司 结型场效应管及其制作方法、半导体芯片
CN111969050A (zh) * 2019-05-20 2020-11-20 三菱电机株式会社 半导体装置及其驱动方法
CN113782609A (zh) * 2021-09-09 2021-12-10 东南大学 一种衬底电荷耦合的1200v体硅ldmos及其制备方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10784372B2 (en) * 2015-04-03 2020-09-22 Magnachip Semiconductor, Ltd. Semiconductor device with high voltage field effect transistor and junction field effect transistor
KR101975630B1 (ko) * 2015-04-03 2019-08-29 매그나칩 반도체 유한회사 접합 트랜지스터와 고전압 트랜지스터 구조를 포함한 반도체 소자 및 그 제조 방법
CN106483758B (zh) 2015-09-02 2019-08-20 无锡华润上华科技有限公司 光学邻近效应修正方法和系统
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CN106816468B (zh) 2015-11-30 2020-07-10 无锡华润上华科技有限公司 具有resurf结构的横向扩散金属氧化物半导体场效应管
CN105679820B (zh) * 2016-03-16 2018-08-21 上海华虹宏力半导体制造有限公司 Jfet及其制造方法
CN107465983B (zh) 2016-06-03 2021-06-04 无锡华润上华科技有限公司 Mems麦克风及其制备方法
TWI748301B (zh) * 2019-12-09 2021-12-01 新唐科技股份有限公司 接面場效電晶體及其製造方法
CN112002692B (zh) * 2020-08-06 2022-10-25 杰华特微电子股份有限公司 用于静电防护的晶体管及其制造方法
CN112397507B (zh) * 2020-11-16 2022-05-10 杰华特微电子股份有限公司 横向双扩散晶体管及其制造方法
KR102401162B1 (ko) * 2021-05-20 2022-05-24 주식회사 키파운드리 폴리-실리콘 접합 전계 효과 트랜지스터를 포함하는 반도체 소자 및 이의 제조 방법

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070228422A1 (en) * 2006-03-31 2007-10-04 Sanken Electric Co., Ltd. Monolithic integrated circuit of a field-effect semiconductor device and a diode
CN101350351A (zh) * 2007-07-16 2009-01-21 台湾积体电路制造股份有限公司 半导体结构及其形成方法
CN102751277A (zh) * 2011-08-22 2012-10-24 成都芯源系统有限公司 集成有肖特基二极管的功率器件及其制造方法
US20120267715A1 (en) * 2011-04-20 2012-10-25 Chou Wei-Chun High voltage semiconductor device and method for fabricating the same
CN103296082A (zh) * 2012-02-27 2013-09-11 无锡华润上华半导体有限公司 金属氧化层半导体场效应晶体管
CN103811490A (zh) * 2012-11-07 2014-05-21 飞思卡尔半导体公司 带有由二极管电路互连的有源器件和隔离结构的半导体器件和驱动电路及制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8207559B2 (en) * 2008-07-14 2012-06-26 Texas Instruments Incorporated Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures
US7928509B2 (en) * 2009-05-21 2011-04-19 Richtek Technology Corporation Integrated JFET and schottky diode
CN102842596B (zh) 2011-06-22 2015-05-20 旺宏电子股份有限公司 半导体结构及其制造方法
CN103178093B (zh) 2011-12-26 2015-10-14 上海华虹宏力半导体制造有限公司 高压结型场效应晶体管的结构及制备方法
US8735950B2 (en) * 2012-09-06 2014-05-27 Freescale Semiconductor, Inc. Tunable schottky diode with depleted conduction path

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070228422A1 (en) * 2006-03-31 2007-10-04 Sanken Electric Co., Ltd. Monolithic integrated circuit of a field-effect semiconductor device and a diode
CN101350351A (zh) * 2007-07-16 2009-01-21 台湾积体电路制造股份有限公司 半导体结构及其形成方法
US20120267715A1 (en) * 2011-04-20 2012-10-25 Chou Wei-Chun High voltage semiconductor device and method for fabricating the same
CN102751277A (zh) * 2011-08-22 2012-10-24 成都芯源系统有限公司 集成有肖特基二极管的功率器件及其制造方法
CN103296082A (zh) * 2012-02-27 2013-09-11 无锡华润上华半导体有限公司 金属氧化层半导体场效应晶体管
CN103811490A (zh) * 2012-11-07 2014-05-21 飞思卡尔半导体公司 带有由二极管电路互连的有源器件和隔离结构的半导体器件和驱动电路及制造方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111463258A (zh) * 2019-01-18 2020-07-28 新唐科技股份有限公司 晶体管元件
CN111599861A (zh) * 2019-02-20 2020-08-28 新唐科技股份有限公司 半导体结构及其制造方法
CN111599861B (zh) * 2019-02-20 2023-12-26 新唐科技股份有限公司 半导体结构及其制造方法
CN111969050A (zh) * 2019-05-20 2020-11-20 三菱电机株式会社 半导体装置及其驱动方法
CN111969050B (zh) * 2019-05-20 2023-12-22 三菱电机株式会社 半导体装置及其驱动方法
CN111697058A (zh) * 2020-06-09 2020-09-22 杰华特微电子（杭州）有限公司 半导体器件
CN111696984A (zh) * 2020-06-09 2020-09-22 杰华特微电子（杭州）有限公司 半导体器件及其制作方法
CN111697058B (zh) * 2020-06-09 2023-06-23 杰华特微电子股份有限公司 半导体器件
CN111696984B (zh) * 2020-06-09 2023-06-23 杰华特微电子股份有限公司 半导体器件及其制作方法
CN111900197A (zh) * 2020-07-29 2020-11-06 杰华特微电子（杭州）有限公司 结型场效应管及其制作方法、半导体芯片
CN111900197B (zh) * 2020-07-29 2023-06-23 杰华特微电子股份有限公司 结型场效应管及其制作方法、半导体芯片
CN113782609A (zh) * 2021-09-09 2021-12-10 东南大学 一种衬底电荷耦合的1200v体硅ldmos及其制备方法

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