CN103843143A - 用于非平坦晶体管的钨栅极 - Google Patents

用于非平坦晶体管的钨栅极 Download PDF

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CN103843143A
CN103843143A CN201180073728.1A CN201180073728A CN103843143A CN 103843143 A CN103843143 A CN 103843143A CN 201180073728 A CN201180073728 A CN 201180073728A CN 103843143 A CN103843143 A CN 103843143A
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work function
function material
nmos
gate
grid
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CN103843143B (zh
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S·S·普拉丹
D·B·伯格斯特龙
J-S·全
J·邱
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Sony Corp
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Intel Corp
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Abstract

本说明书涉及制造具有非平坦晶体管的微电子器件的领域。本说明书的实施方案涉及在非平坦NMOS晶体管内形成栅极，其中NMOS功函数材料，例如铝、钛和碳的组合物，可以结合含钛的栅极填充阻挡物一起用于促进将含钨导电材料用于形成非平坦NMOS晶体管栅极的栅极电极。

Description

用于非平坦晶体管的钨栅极
技术领域
本说明书的实施方案一般涉及微电子器件制造领域，并且更具体地涉及非平坦晶体管内的钨栅极的制造。
附图说明
在本说明书的总结部分特别指出了本公开的主题，并且明确要求权利。参考附图，根据以下的说明及随附的权利要求，本公开的上述及其它特征将进一步变得清楚。可理解的是，附图仅描绘了根据本公开的几个实施方案，因此，不应认为是对其范围的限制。通过使用附图，以附加的特征和细节描述本公开，使得更容易确定本公开的优点，其中：
图1是根据本说明书的一个实施方案的非平坦晶体管的透视图。
图2示出了在微电子基底之中或之上形成的非平坦晶体管鳍(fin)的侧面剖视图。
图3示出了根据本说明书的一个实施方案，在图2的非平坦晶体管鳍的上面沉积的牺牲材料的侧面剖视图。
图4示出了根据本说明书的一个实施方案，在牺牲材料中形成的沟道(trench)的侧面剖视图，沉积牺牲材料以暴露图3的非平坦晶体管鳍的一部分。
图5示出了根据本说明书的一个实施方案，在图4的沟道中形成的牺牲栅极的侧面剖视图。
图6示出了根据本说明书的一个实施方案，在去除图5的牺牲材料之后的牺牲栅极的侧面剖视图。
图7示出了根据本说明书的一个实施方案，在图6的牺牲栅极和微电子基底上沉积的共形介电层的侧面剖视图。
图8示出了根据本说明书的一个实施方案，由图7的共形介电层形成的栅极间隔件的侧面剖视图。
图9示出了根据本说明书的一个实施方案，在图8的栅极间隔件的各面上的非平坦晶体管鳍中形成的源极区和漏极区的侧面剖视图。
图10示出了根据本说明书的一个实施方案，在图9的栅极间隔件、牺牲栅极、非平坦晶体管鳍和微电子基底上沉积的第一介电材料的侧面剖视图。
图11示出了根据本说明书的一个实施方案，在使第一介电材料平坦化以暴露牺牲栅极的上表面之后，图10结构的侧面剖视图。
图12示出了根据本说明书的一个实施方案，去除牺牲栅极以形成栅极沟道之后，图11结构的侧面剖视图。
图13示出了根据本说明书的一个实施方案，在邻近栅极间隔件之间的非平坦晶体管鳍的栅极介电体形成之后，图12结构的侧面剖视图。
图14示出了根据本说明书的一个实施方案，在栅极沟道内形成NMOS功函数材料之后，图13结构的侧面剖视图。
图15示出了根据本说明书的一个实施方案，在NMOS功函数材料上沉积的栅极填充阻挡物(gate fill barrier)形成之后，图14结构的侧面剖视图。
图16示出了根据本说明书的一个实施方案，在图15的栅极沟道中沉积的导电栅极材料的侧面剖视图。
图17示出了根据本说明书的一个实施方案，在去除过量的导电栅极材料以形成非平坦晶体管栅极之后，图16结构的侧面剖视图。
图18示出了根据本说明书的一个实施方案，在蚀刻去除一部分非平坦晶体管栅极以形成下凹的非平坦晶体管栅极之后，图17结构的侧面剖视图。
图19示出了根据本说明书的一个实施方案，将帽盖(capping)介电材料沉积入形成下凹的非平坦晶体管栅极的形成所致的凹陷之后，图18结构的侧面剖视图。
图20示出了根据本说明书的一个实施方案，在去除过量的帽盖介电材料以在非平坦晶体管栅极上形成帽盖结构之后，图19结构的侧面剖视图。
图21示出了根据本说明书的一个实施方案，在图20的第一介电材料层、栅极间隔件和牺牲栅极上表面上沉积的第二介电材料的侧面剖视图。
图22示出了根据本说明书的一个实施方案，在图21的第二介电材料上形成图案化的蚀刻掩模的侧面剖视图。
图23示出了根据本说明书的一个实施方案，通过图22的第一和第二介电材料层形成的接触开口的侧面剖视图。
图24示出了根据本说明书的一个实施方案，在去除蚀刻掩模之后的图23结构的侧面剖视图。
图25示出了根据本说明书的一个实施方案，在图24的接触开口中沉积的导电接触材料的侧面剖视图。
图26示出了根据本说明书的一个实施方案，在去除过量的导电接触材料以形成源/漏极触点之后，图25结构的侧面剖视图。
图27是根据本说明书的一个实施方案，形成非平坦晶体管的工艺流程图。
图28是根据本说明书的一个实施方案，形成非平坦晶体管的工艺流程图。
具体实施方式
在以下的详细说明中参考附图，其以示例方式显示了可以实施所要求权利的主题的具体实施方案。对这些实施方案足够详细地进行说明，使本领域技术人员能够实施该主题。可理解的是，尽管各个实施方案不同，但并不一定互相排斥。例如，本文所述的有关一个实施方案的具体特征、结构或特性可以在其它实施方案内实施，而不会背离所要求权利的主题的精神和范围。本文所指的“一个实施方案”或“实施方案”是指有关该实施方案描述的具体特征、结构、或特性包括在本发明涵盖的至少一个实施方案中。因此，使用术语“一个实施方案”或“实施方案”不一定指相同的实施方案。此外，可理解的是，每个所公开的实施方案内的单个要素的位置或布置可以被修改，而不会背离所要求权利的主题的精神和范围。因此，以下的详细说明不应从限制意义上理解，主题范围仅由随附的权利要求所限定，与随附的权利要求所具有的全部等同范围一起进行合理解释。在附图中，类似的数字在几个视图中是指相同或类似的元件或功能，其中描绘的要素不一定互相合乎比例，而是单独要素可以放大或缩小，以便在本说明书的情境中更容易理解该要素。
在非平坦晶体管，例如三栅极晶体管和FinFET的制造中，非平坦半导体本体可以用以形成能够以非常小的栅极长度(例如低于约30nm)完全耗尽的晶体管。这些半导体本体通常为鳍状，因此，通常被称为晶体管“鳍”。例如在三栅极晶体管中，晶体管鳍具有上表面和两个相反的侧壁，所述侧壁形成在块状半导体的基底或绝缘体上硅的基底上。栅极介电体可以形成在半导体本体的上表面和侧壁上，栅极电极可以形成在半导体本体上表面上的栅极介电体上，并且邻近于半导体本体侧壁上的栅极介电体。由此，由于栅极介电体和栅极电极邻近于半导体本体的三个表面，可以形成三个独立的通道和栅极。由于形成有三个独立的沟道，当晶体管开启时半导体本体可以完全地耗尽。对于finFET晶体管，栅极材料和电极只接触半导体本体的侧壁，使得形成两个独立的沟道(而不是三栅极晶体管中的三个)。
本说明书的实施方案涉及在非平坦晶体管内形成栅极，其中NMOS功函数材料，例如铝、钛和碳的组合物可结合含钛的栅极填充阻挡物一起用于促进含钨导电材料在形成非平坦晶体管栅极的栅极电极中的使用。
图1是非平坦晶体管100的透视图，其包括形成在至少一个晶体管鳍的上面的至少一个栅极，其形成在微电子基底102上。在本公开的一个实施方案中，微电子基底102可以是单晶硅基底。微电子基底102还可以是其它类型的基底，例如绝缘体上硅(“SOI”)、锗、砷化镓、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、锑化镓等，其中任一种可与硅组合。
显示为三栅极晶体管的非平坦晶体管可以包括至少一个非平坦晶体管鳍112。非平坦晶体管鳍112可具有上表面114和一对侧向相反的侧壁，其分别为侧壁116和相反的侧壁118。
如图1另外显示的，至少一个非平坦晶体管栅极122可以形成在非平坦晶体管鳍112上。非平坦晶体管栅极122可通过在非平坦晶体管鳍的上表面114之上或邻近处、以及在非平坦晶体管鳍侧壁116和相反的非平坦晶体管鳍侧壁118之上或邻近处形成栅极介电层124。栅极电极126可以形成在栅极介电层124之上或邻近处。在本公开的一个实施方案中，非平坦晶体管鳍112可以沿基本上垂直于非平坦晶体管栅极122的方向延伸。
栅极介电层124可通过任何熟知的栅极介电材料形成，其包括但不限于二氧化硅(SiO2)、氮氧化硅(SiOxNy)、氮化硅(Si3N4)和高k介电材料，例如氧化铪、铪硅氧化物、氧化镧、镧铝氧化物、氧化锆、锆硅氧化物、氧化钽、氧化钛、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化物和铌锌酸铅。栅极介电层124可通过熟知的方法，例如通过共形沉积栅极介电材料而形成，然后用熟知的光刻法和蚀刻技术对栅极介电材料图案化，这是本领域技术人员将会理解的。
栅极电极126可通过如将讨论的本发明的各个实施方案形成。
源极区和漏极区(图1中未显示)可以形成在栅极电极126的相反侧上的非平坦晶体管鳍112中。在一个实施方案中，源极区和漏极区可通过掺杂非平坦晶体管鳍112而形成，这是本领域技术人员将会理解的。在另一个实施方案中，源极区和漏极区可通过去除部分非平坦晶体管鳍112，并且用适当的材料替代这些部分而形成源极区和漏极区，这是本领域技术人员将会理解的。在另一个实施方案中，源极区和漏极区可通过使掺杂或未掺杂的应力层在鳍112上外延性生长而形成。
图2-26示出了制造非平坦晶体管的一个实施方案的侧剖面图，其中图2-5为沿着图1的箭头A-A和B-B的视图，图6-15为沿着图1的箭头A-A的视图，图16-26为沿着图1的箭头C-C的视图。
如图2所示，非平坦晶体管鳍112可通过蚀刻微电子基底102或通过本领域已知的任何技术在微电子基底102上形成非平坦晶体管鳍112而形成。如图3中示出的，牺牲材料132可以沉积在非平坦晶体管鳍112之上(如图3所示)，沟道134可以在牺牲材料132中形成以暴露部分非平坦晶体管鳍112(如图4所示)。牺牲材料132可以为本领域中任何合适的材料，沟道134可通过本领域中已知的任何技术形成，其包括但不限于光刻掩模和蚀刻。
如图5所示，牺牲栅极136可以在沟道134中形成(参见图4)。牺牲栅极136可以为任何合适的材料，例如多晶硅材料等，并且可通过本领域中已知的任何技术沉积在沟道134中(参见图4)，其包括但不限于化学气相沉积(“CVD”)和物理气相沉积(“PVD”)。
如图6所示，可通过本领域中已知的任何技术去除图5的牺牲材料132，例如选择性地蚀刻牺牲材料132以暴露牺牲栅极136。如图7所示，共形介电层142可以沉积在牺牲栅极136和微电子基底102之上。共形介电层142可以为任何合适的材料，其包括但不限于氮化硅(Si3N4)和碳化硅(SiC)，并且可通过任何合适的技术形成，其包括但不限于原子层沉积(“ALD”)。
如图8所示，图7的共形介电层142可以被蚀刻，例如用合适的蚀刻剂定向蚀刻以在牺牲栅极136的侧壁146上形成成对的栅极间隔件144，同时基本上去除邻近微电子基底102和牺牲栅极136上表面148的共形介电材料层142。可理解的是，鳍间隔件(未显示)可以在栅极间隔件144形成过程中同时形成在非平坦晶体管鳍112的侧壁116和118上(参见图1)。
如图9所示，源极区150a和漏极区150b可以在栅极间隔件144的每一侧上形成。在一个实施方案中，源极区150a和漏极区150b可通过N型离子掺杂剂注入(implantation)在非平坦晶体管鳍112中形成。如本领域技术人员将会理解的，掺杂剂注入是为了改变其导电性和电子性能的目的而将杂质引入半导体材料中的工艺。其通常通过P型离子(如硼)或N型离子(如磷)(总称为“掺杂剂”)的离子注入而实现。在另一个实施方案中，部分非平坦晶体管鳍112可通过本领域中已知的任何技术，例如蚀刻而被去除，而源极区150a和漏极区150b可以替代被去除的部分而形成。在又一个实施方案中，源极区和漏极区可通过使掺杂或未掺杂的应力层在鳍112上外延性生长而形成。源极区150a和漏极区将在下文中总称为“源/漏极区150”。如本领域技术人员将会理解的，具有P型源极和漏极的晶体管被称为“PMOS”或“p-沟道金属氧化物半导体”晶体管，具有N型源极和漏极的晶体管被称为“NMOS”或“n-沟道金属氧化物半导体”晶体管。本说明书涉及NMOS晶体管。因此，源/漏极区150可以为N型。
如图10所示，第一介电材料层152可以沉积在栅极间隔件144、牺牲栅极的上表面148、非平坦晶体管鳍112和微电子基底102之上。第一介电材料层152可进行平坦化以暴露牺牲栅极的上表面148(如图11所示)。通过本领域中已知的任何技术可以实现第一介电材料层152的平坦化，其包括但不限于化学机械抛光(CMP)。
如图12所示，可以去除图11的牺牲栅极136而形成栅极沟道154。可通过本领域中已知的任何技术，例如选择性蚀刻来去除牺牲栅极136。如图13所示，可以形成栅极介电层124(另如图1所示)，其与非平坦晶体管鳍112邻接，这是如前面所讨论的。形成栅极电极124的材料和方法已经在前面讨论。
如图14所示，NMOS功函数材料156可以共形沉积在栅极沟道154内。NMOS功函数材料156可以包含包括铝、钛和碳的组合物。在一个实施方案中，NMOS功函数材料156可以包括约20-40重量%的铝、约30-50重量%的钛和约10-30重量%的碳。在另一个实施方案中，NMOS功函数材料156可以包括约33重量%的铝、约43重量%的钛和约24重量%的碳。NMOS功函数材料156可通过ALD工艺进行共形沉积以提供良好的非平坦晶体管鳍112的覆盖，并且在栅极沟道154周围实现均匀的阈电压，这是本领域技术人员将会理解的。另外可理解的是，可以调节铝与钛的比例以调节非平坦晶体管100的功函数，而碳可以是ALD方法的人造产物，而不是加入的组分。
如图15所示，栅极填充阻挡物158可以共形沉积在NMOS功函数材料156上。栅极填充阻挡物158可以是含钛的材料，其包括但不限于基本上纯的钛和氮化钛等。栅极填充阻挡物158可以由任何已知的技术形成。在一个实施方案中，栅极填充阻挡物158可以是通过化学气相沉积工艺形成的氮化钛，包括在约400℃下用等离子体致密化的四(二甲氨基)钛(TDMAT)的分解。在另一个实施方案中，栅极填充阻挡物158可以是通过原子层沉积工艺形成的氮化钛，包括在约300℃下的氯化钛(TiCl)和氨(NH3)的脉冲。在另一个实施方案中，栅极填充阻挡物158可以是钛和氮化钛的双层，其中钛层可通过物理气相沉积形成，而氮化钛可以如以上所讨论地形成。栅极阻挡物层158可以允许在随后的步骤中使用六氟化钨来沉积钨，以防止氟侵蚀。在钛/氮化钛双层中使用钛层可以对可能通过氮化钛层扩散的任何氟起吸气剂的作用。
如图16所示，钨栅极填充材料162可以沉积在栅极填充阻挡物158上。钨栅极填充材料162可通过本领域中已知的任何技术形成。在一个实施方案中，可以形成成核层，如在约300℃下经脉冲的二硼烷和六氟化钨，随后在约395℃下通过六氟化钨与氢反应而生长块状钨(bulk tungsten)。在一个实施方案中，钨栅极填充材料162为含钨材料。在另一个实施方案中，钨栅极填充材料162为基本上纯的钨。
如图17所示，可以去除过量的钨栅极填充材料162(例如不在图16的栅极沟道154内的钨栅极填充材料162)而形成非平坦晶体管栅极电极126(参见图1)。通过本领域中已知的任何技术可以去除过量的钨栅极填充材料162，其包括但不限于化学机械抛光(CMP)、蚀刻等。
如图18所示，可以去除一部分非平坦晶体管栅极电极126而形成凹陷164和下凹的非平坦晶体管栅极166。可通过任何已知的技术实现去除，其包括但不限于湿法刻蚀或干法刻蚀。在一个实施方案中，可以结合干法蚀刻和湿法蚀刻产生形成凹陷。例如，钨栅极填充材料162可以用六氟化硫的干法蚀刻产生凹陷，而NMOS功函数材料156可以用随后的湿法蚀刻产生凹陷。
如图19所示，可以沉积帽盖介电材料168以填充图18的凹陷164。帽盖介电材料168可以是任何合适的材料，其包括但不限于氮化硅(Si3N4)和碳化硅(SiC)，并且可通过任何合适的沉积技术形成。帽盖介电材料168可被平坦化以去除过量的帽盖介电材料168(例如不在图16的凹陷内的帽盖介电材料168)，从而如图20所示，在下凹的非平坦晶体管栅极166上和栅极间隔件144之间形成帽盖介电结构170。通过本领域中已知的任何技术可以去除过量的帽盖介电材料168，其包括但不限于化学机械抛光(CMP)、蚀刻等。
如图21所示，第二介电材料层172可以沉积在第一介电材料层152、栅极间隔件144和帽盖介电结构170之上。第二介电材料层172可通过任何已知的沉积技术由任何合适的介电材料形成，其包括但不限于二氧化硅(SiO2)、氮氧化硅(SiOxNy)和氮化硅(Si3N4)。如图22所示，蚀刻掩模174可以例如通过熟知的蚀刻方法用至少一个开口176在第二介电材料层172上图案化。
如图23所示，通过蚀刻穿过图24的蚀刻掩模开口176，通过第一介电材料层152和第二介电材料层172而形成接触开口182，从而暴露一部分源/漏极区150。如图24所示，然后可以去除图23的蚀刻掩模174。在一个实施方案中，第一介电材料层152和第二介电材料层172不同于栅极间隔件144和帽盖介电结构170两者的介电材料，使得第一介电材料层152和第二介电层172的蚀刻可以对栅极间隔件144和帽盖介电结构170有选择性(即蚀刻得更快)。本领域中称其为自排列(self-aligning)。
如图25所示，导电接触材料188可以沉积在图23的接触开口182中。导电接触材料188可以包括，但不限于多晶硅、钨、钌、钯、铂、钴、镍、铪、锆、钛、钽、铝、碳化钛、碳化锆、碳化钽、碳化铪、碳化铝、其它金属碳化物、金属氮化物和金属氧化物。可理解的是，各种粘合层、阻挡物层、硅化物层和/或导电层可以在导电接触材料188沉积之前共形布置或形成在图23的接触开口182中。
如图26所示，可以去除图27的过量导电接触材料188(例如不在图24的接触开口182内的导电接触材料188)以形成源/漏极触点190。通过本领域中已知的任何技术可以去除过量的导电接触材料188，其包括但不限于化学机械抛光(CMP)、蚀刻等。
如前面所讨论的，在一个实施方案中，第一介电材料层152和介电材料层168不同于栅极间隔件144和帽盖介电结构166两者的介电材料，使得第一介电材料层152和第二介电层168的蚀刻可以对栅极间隔件144和帽盖介电结构166有选择性(即蚀刻得更快)。由此，下凹的非平坦晶体管162在接触开口182的形成过程中受保护。这可以使得形成尺寸相对较大的源/漏极触点190，其可以增加晶体管驱动电流的性能，而没有在源/漏极触点190和下凹的非平坦晶体管栅极162之间短路的危险。
尽管本说明书涉及非平坦的NMOS晶体管，但可理解的是，结合非平坦NMOS晶体管的集成电路也可以包括非平坦的PMOS晶体管。因此，制造非平坦NMOS晶体管的工艺可以结合入整个集成电路制造工艺中。
在一个实施方案中，如图27中的流程图的工艺200所示，根据图2-13形成结构之后，如方框210中所述，PMOS功函数材料，例如氮化钛可被沉积在栅极沟道中。如方框220中所述，可以例如通过抗蚀剂图案化和蚀刻，在制造NMOS栅极的区域内去除一部分PMOS功函数材料，这是本领域已知的。然后可以从图14开始继续该工艺，例如在沉积NMOS功函数材料的同时，使图案化的抗蚀剂留在原位。
在一个实施方案中，如图28中的流程图的工艺300所示，根据图2-14形成结构之后，如本领域所知，可以例如通过抗蚀剂图案化和蚀刻，可以去除用于PMOS制造的区域内的一部分NMOS功函数材料。如方框310中所述，PMOS功函数材料，例如氮化钛可被沉积在栅极沟道中，如方框320中所述。然后可以从图15开始继续该工艺。可理解的是，可以不要求独立形成栅极填充阻挡物158(如图15所示)，因为沉积在方框310中的PMOS功函数也可以起栅极填充阻挡物158的作用。
可理解的是，本说明书的主题不必限于图1-28中所述的特定应用。所述主题可以应用于其它的微电子器件制造应用，正如本领域技术人员所能理解的。
虽然已经以详细的本发明实施方案进行描述，可理解的是，随附的权利要求所限定的本发明不受上述描述所阐述的具体细节的限制，因为其可以有许多明显的变化，而不会背离其精神和范围。

Claims (25)

1.一种晶体管栅极，其包括：
成对的栅极间隔件；和
布置在成对的栅极间隔件之间的栅极电极，其中所述栅极电极包括：
NMOS功函数材料，所述NMOS功函数材料邻近成对的栅极间隔件的至少一部分，并且包含铝、钛和碳；
含钛的栅极填充阻挡物，所述栅极填充阻挡物邻近NMOS功函数材料；以及
含钨的栅极填充材料，所述栅极填充材料邻近栅极填充阻挡物。
2.权利要求1的晶体管栅极，其中所述栅极电极是非平坦的。
3.权利要求1的晶体管栅极，其中所述NMOS功函数材料包含约20-40重量%的铝、约30-50重量%的钛、以及约10-30重量%的碳。
4.权利要求1的晶体管栅极，其中所述NMOS功函数材料包含约33重量%的铝、约43重量%的钛、以及约24重量%的碳。
5.权利要求1的晶体管栅极，其还包括帽盖介电结构，所述帽盖介电结构布置在非平坦栅极电极的邻近处，以及布置在成对的栅极间隔件之间。
6.一种制造晶体管栅极的方法，其包括：
形成成对的栅极间隔件；以及
形成布置在成对的栅极间隔件之间的栅极电极，其包括：
共形沉积NMOS功函数材料，所述NMOS功函数材料邻近成对的栅极间隔件，并包含铝、钛和碳；
共形沉积含钛的栅极填充阻挡物，所述栅极填充阻挡物邻近NMOS功函数材料；以及
沉积含钨的栅极填充材料，所述栅极填充材料邻近栅极填充阻挡物。
7.权利要求6的方法，其中共形沉积NMOS功函数材料包括共形沉积组成为约20-40重量%的铝、约30-50重量%的钛、以及约10-30重量%的碳的NMOS功函数材料。
8.权利要求7的方法，其中共形沉积NMOS功函数材料包括共形沉积组成为约33重量%的铝、约43重量%的钛、以及约24重量%的碳的NMOS功函数材料。
9.权利要求6的方法，其还包括：
共形沉积PMOS功函数材料，所述PMOS功函数材料邻近成对的栅极间隔件；以及
在沉积NMOS功函数材料之前，去除用于制造NMOS栅极电极的区域内的一部分PMOS功函数材料。
10.权利要求9的方法，其中共形沉积PMOS功函数材料包括共形沉积氮化钛PMOS功函数材料。
11.权利要求6的方法，其还包括：
去除用于制造PMOS栅极电极的区域内的一部分NMOS功函数材料；以及
共形沉积PMOS功函数材料，所述PMOS功函数材料邻近成对的栅极间隔件，并且在用于制造NMOS栅极电极的区域内的NMOS功函数材料之上。
12.权利要求11的方法，其中共形沉积PMOS功函数材料包括共形沉积氮化钛PMOS功函数材料。
13.权利要求6的方法，其还包括：
去除用于制造PMOS栅极电极的区域内的一部分NMOS功函数材料；以及
将含钛的层共形沉积作为邻近用于制造NMOS栅极电极的区域内的NMOS功函数材料的栅极填充阻挡物，以及作为用于制造PMOS栅极电极的区域内的PMOS功函数材料。
14.权利要求13的方法，其中所述共形沉积含钛的层包括共形沉积氮化钛层。
15.权利要求6的方法，其还包括形成帽盖介电结构，所述帽盖介电结构布置在非平坦的栅极电极的邻近处，以及布置在成对的栅极间隔件之间。
16.权利要求15的方法，其中所述帽盖介电结构布置在非平坦的栅极电极的邻近处及布置在成对的栅极间隔件之间的形成帽盖介电结构包括：
通过去除一部分栅极电极而在栅极间隔件之间形成凹陷；以及
在凹陷内沉积帽盖介电材料。
17.一种制造非平坦晶体管栅极的方法，其包括：
在非平坦晶体管鳍的上面形成牺牲性非平坦晶体管栅极；
在所述牺牲性非平坦晶体管栅极和非平坦晶体管鳍的上面沉积介电材料层；
由邻近所述牺牲性非平坦晶体管栅极的一部分介电材料层形成非平坦晶体管栅极间隔件；
形成源/漏极区；
去除所述牺牲性非平坦晶体管栅极，在非平坦晶体管栅极间隔件之间形成栅极沟道，以及暴露一部分非平坦晶体管鳍；
形成栅极介电体，所述栅极介电体邻近栅极沟道内的非平坦晶体管鳍；
形成布置在成对的栅极间隔件之间的栅极电极，其包括：
共形沉积NMOS功函数材料，所述NMOS功函数材料邻近成对的栅极间隔件，并且包含铝、钛和碳；
共形沉积含钛的栅极填充阻挡物，所述栅极填充阻挡物邻近NMOS功函数材料；以及
沉积含钨的栅极填充材料，所述栅极填充材料邻近栅极填充阻挡物；
去除一部分栅极电极而在非平坦晶体管栅极间隔件之间形成凹陷；
在凹陷内形成帽盖介电结构；
在源/漏极区、非平坦晶体管栅极间隔件和帽盖介电结构之上形成至少一个介电材料层；以及
形成通过至少一个介电材料的接触开口，以接触至少一部分的源/漏极区。
18.权利要求17的方法，其中共形沉积NMOS功函数材料包括共形沉积组成为约20-40重量%的铝、约30-50重量%的钛、以及约10-30重量%的碳的NMOS功函数材料。
19.权利要求17的方法，其中共形沉积NMOS功函数材料包括共形沉积组成为约33重量%的铝、约43重量%的钛、以及约24重量%的碳的NMOS功函数材料。
20.权利要求17的方法，其还包括：
共形沉积PMOS功函数材料，所述PMOS功函数材料邻近成对的栅极间隔件；以及
在沉积NMOS功函数材料之前，去除用于制造NMOS栅极电极的区域内的一部分PMOS功函数材料。
21.权利要求20的方法，其中共形沉积PMOS功函数材料包括共形沉积氮化钛PMOS功函数材料。
22.权利要求17的方法，其还包括：
去除用于制造PMOS栅极电极的区域内的一部分NMOS功函数材料；以及
共形沉积PMOS功函数材料，所述PMOS功函数材料邻近成对的栅极间隔件，并且在用于制造NMOS栅极电极的区域内的NMOS功函数材料之上。
23.权利要求22的方法，其中共形沉积PMOS功函数材料包括共形沉积氮化钛PMOS功函数材料。
24.权利要求17的方法，其还包括：
去除用于制造PMOS栅极电极的区域内的一部分NMOS功函数材料；以及
将含钛的层共形沉积作为邻近用于制造NMOS栅极电极的区域内的NMOS功函数材料的栅极填充阻挡物，以及作为用于制造PMOS栅极电极的区域内的PMOS功函数材料。
25.权利要求22的方法，其中共形沉积含钛的栅极填充阻挡物包括共形沉积氮化钛层。
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