TWI585980B - 用於非平面電晶體之鎢閘極技術（二） - Google Patents

用於非平面電晶體之鎢閘極技術（二） Download PDF

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TWI585980B
TWI585980B TW104131442A TW104131442A TWI585980B TW I585980 B TWI585980 B TW I585980B TW 104131442 A TW104131442 A TW 104131442A TW 104131442 A TW104131442 A TW 104131442A TW I585980 B TWI585980 B TW I585980B
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layer
dielectric
gate
pair
dielectric layer
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TW104131442A
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TW201614847A (en
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Sameer S Pradhan
Daniel B Bergstrom
Jin-Sung Chun
Julia Chiu
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Intel Corp
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    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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Description

用於非平面電晶體之鎢閘極技術(二) 發明領域
本發明係有關於用於非平面電晶體之鎢閘極技術。
發明背景
本說明之實施例一般而言有關於微電子裝置製造領域，且更具體而言，有關於在非平面電晶體內製造鎢閘極。
發明概要
依據本發明之一實施例，係特地提出一種裝置，其包含有：一基板，其中該基板包含一矽鰭(silicon fin)；在該基板上之一第一介電層，其中該第一介電層包含矽和氧；在該第一介電層上之一第二介電層，其中該第二介電層包含鉿和氧；在該基板上之一對閘極間隔物，其中該等閘極間隔物包含一介電材料；在該第二介電材料之上且在該對閘極間隔物之間的一NMOS金屬閘極電極，其中該NMOS金屬閘極電極包含：接近該對閘極間隔物且在該第 二介電層之上的一第一金屬層，其中該第一金屬層包含鋁、鈦和碳；及在該第一金屬層上之一第二金屬層，其中該第二金屬層包含鈦和氮；接近該對閘極間隔物之一者的一源極區，與接近該對閘極間隔物之另一者的一汲極區，其中該源極區和該汲極區包含一n型摻雜物；耦接至該源極區之一第一接點，其中該第一接點包含一鎢材料在一第一障蔽層之上；以及耦接至該汲極區之一第二接點，其中該第二接點包含一鎢材料在一第二障蔽層之上。
100‧‧‧非平面電晶體
102‧‧‧微電子基板
112‧‧‧非平面電晶體鰭/鰭
114‧‧‧頂面/非平面電晶體鰭頂面
116‧‧‧側壁/非平面電晶體鰭側壁
118‧‧‧相對的側壁/相對的非平面電晶體鰭側壁/側壁
122‧‧‧非平面電晶體閘極
124‧‧‧閘極介電層/閘極介電質
126‧‧‧閘極電極/非平面電晶體閘極電極
132‧‧‧犧牲材料
134‧‧‧溝槽
136‧‧‧犧牲閘極
142‧‧‧共形介電層/共形介電材料層
144‧‧‧閘極間隔物
146‧‧‧側壁
148‧‧‧頂面/犧牲閘極頂面
150‧‧‧源極/汲極區
150a‧‧‧源極區
150b‧‧‧汲極區
152‧‧‧第一介電材料層
154‧‧‧閘極溝槽
156‧‧‧NMOS功函數材料
158‧‧‧閘極填充障蔽/閘極障蔽層
162‧‧‧鎢閘極填充材料/凹入的非平面電晶體/凹入的非平面電晶體閘極
164‧‧‧凹口
166‧‧‧凹入的非平面電晶體閘極/覆蓋介電結構
168‧‧‧覆蓋介電材料/介電材料 層/第二介電層
170‧‧‧覆蓋介電結構
172‧‧‧第二介電材料層/第二介電層
174‧‧‧蝕刻遮罩176‧‧‧開口
182‧‧‧接觸開口
188‧‧‧導電接觸材料
190‧‧‧源極/汲極接點
200、300‧‧‧方法
210、220、310、320‧‧‧方塊
本揭露之標的在本說明書最後部分中被特別指出且被清楚地請求保護。本揭露之前述及其他特徵將由結合附圖的下述說明及所附申請專利範圍變得更加清楚。應理解的是，附圖僅描繪依據本揭露的若干實施例，且因此，不欲被視為限制其範圍。本揭露將透過使用附圖描述另外的特性及細節，使得本揭露之優勢可更容易確定，其中：圖1是依據本說明之一實施例的一非平面電晶體的一透視圖。
圖2繪示在一微電子基板中或在一微電子基板上形成的一非平面電晶體鳍部的一側截面圖。
圖3繪示依據本說明之一實施例，沈積在圖2之非平面電晶體鳍部上的一犧牲材料的一側截面圖。
圖4繪示依據本說明之一實施例，在沈積的犧牲材料中形成，以暴露圖3之非平面電晶體鳍部的一部分的一溝槽的一側截面圖。
圖5繪示依據本說明之一實施例，在圖4之溝槽中形成的一犧牲閘極的一側截面圖。
圖6繪示依據本說明之一實施例，在移除圖5之犧牲材料之後，犧牲閘極的一側截面圖。
圖7繪示依據本說明之一實施例，沈積在圖6之犧牲閘極及微電子基板上的一共形介電層的一側截面圖。
圖8繪示依據本說明之一實施例，由圖7之共形介電層形成之閘極間隔物的一側截面圖。
圖9繪示依據本說明之一實施例，在圖8之閘極間隔物任一側上的非平面電晶體鳍部中形成的一源極區及一汲極區的一側截面圖。
圖10繪示依據本說明之一實施例，沈積在圖9之閘極間隔物、犧牲閘極、非平面電晶體鳍部，及微電子基板上的第一介電材料的一側截面圖。
圖11繪示依據本說明之一實施例，在平面化第一介電材料以暴露犧牲閘極的一頂面之後，圖10之結構的一側截面圖。
圖12繪示依據本說明之一實施例，在移除犧牲閘極以形成一閘極溝槽之後，圖11之結構的一側截面圖。
圖13繪示依據本說明之一實施例，在形成與閘極間隔物之間的非平面電晶體鳍部相鄰的一閘極介電質之後，圖12之結構的一側截面圖。
圖14繪示依據本說明之一實施例，在閘極溝槽內形成一NMOS功函數材料之後，圖13之結構的一側截面圖。
圖15繪示依據本說明之一實施例，在形成沈積在NMOS功函數材料上的一閘極填充障蔽之後，圖14之結構的一側截面圖。
圖16繪示依據本說明之一實施例，沈積在圖15之閘極溝槽中的一導電閘極材料的一側截面圖。
圖17繪示依據本說明之一實施例，在移除過量的導電閘極材料以形成一非平面電晶體閘極之後，圖16之結構的一側截面圖。
圖18繪示依據本說明之一實施例，在蝕刻掉非平面電晶體閘極的一部分以形成一凹入的非平面電晶體閘極之後，圖17之結構的一側截面圖。
圖19繪示依據本說明之一實施例，在沈積一覆蓋介電材料到由形成凹入的非平面電晶體閘極所產生之凹口中之後，圖18之結構的一側截面圖。
圖20繪示依據本說明之一實施例，在移除過量的覆蓋介電材料以在非平面電晶體閘極上形成一覆蓋結構之後，圖19之結構的一側截面圖。
圖21繪示依據本說明之一實施例，沈積在圖20之第一介電材料層、閘極間隔物，及犧牲閘極頂面上的第二介電材料的一側截面圖。
圖22繪示依據本說明之一實施例，圖案形成在圖21之第二介電材料上的一蝕刻遮罩的一側截面圖。
圖23繪示依據本說明之一實施例，穿過圖22之第一及第二介電材料層所形成之一接觸開口的一側截面圖。
圖24繪示依據本說明之一實施例，在移除蝕刻遮罩之後，圖23之結構的一側截面圖。
圖25繪示依據本說明之一實施例，沈積在圖24之接觸開口中的一導電接觸材料的一側截面圖。
圖26繪示依據本說明之一實施例，在移除過量的導電接觸材料以形成一源極/汲極接點之後，圖25之結構的一側截面圖。
圖27是依據本說明之一實施例，形成一非平面電晶體的一方法的一流程圖。
圖28是依據本說明之另一實施例，形成一非平面電晶體的一方法的一流程圖。
較佳實施例之詳細說明
在以下詳細說明中，參考的附圖是以圖示方式繪示申請專利之標的可在其中被實施的特定實施例。這些實施例以充分的細節被描述以使熟於此技者能夠實施該標的。應理解的是，各種不同的實施例雖然各不相同，但不一定互斥。例如，在不背離所申請專利之標的之精神及範圍的情況下，連同一實施例在本文中描述的一特定特徵、結構，或特性可在其他實施例內實施。此說明書內提及「一個實施例」或「一實施例」意指連同該實施例所描述的一特定特徵、結構或特性被包括在本發明所包含的至少一實施中。因此，使用片語「一個實施例」或「在一實施例中」並不一定指同一實施例。除此之外，應理解的是，每一揭 露實施例內的個別元件之位置或配置可在不背離所申請專利之標的之精神及範圍下修改。因此，下述詳細說明不應被理解為具限制性意義，且標的之範圍僅藉由適當解讀的所附申請專利範圍，連同所附申請專利範圍享有權利之均等物的完整範圍來界定。在諸圖中，相同的數字在全部的幾個視圖中皆指相同或相似的元件或功能，且其中所描繪的元件不一定相互成比例，而是個別元件可被放大或縮小，以更易於理解本說明中的元件。
在製造非平面電晶體，諸如三閘電晶體及FinFET的過程中，非平面半導體本體可用以形成能夠完全耗盡、具有非常小的閘極長度(例如，小於約30nm)的電晶體。這些半導體本體一般是鰭形的，且因此，一般被稱作電晶體「鰭」。例如，在一三閘電晶體中，電晶體鰭具有在一塊體半導體基板或一絕緣體上覆矽基板上形成的一頂面及兩個相對側壁。一閘極介電質可在半導體本體之頂面及側壁上形成，且一閘極電極可在半導體本體頂面上的閘極介電質之上且鄰接半導體本體側壁上的閘極介電質被形成。因此，由於閘極介電質及閘極電極與半導體本體之三個表面相鄰，形成三個單獨的通道及閘極。因為形成了三個單獨的通道，當電晶體導通時，半導體本體可以完全耗盡。關於finFET電晶體，閘極材料及電極僅接觸半導體本體之側壁，使得二單獨通道形成(而非三閘電晶體中的三個)。
本說明之實施例有關於在非平面電晶體內形成閘極，其中一NMOS功函數材料，諸如鋁、鈦，及碳的組 成可與含鈦閘極填充障蔽結合使用以便於在形成非平面電晶體閘極之閘極電極中使用一含鎢導電材料。
圖1是一非平面電晶體100的一透視圖，非平面電晶體100包括在至少一電晶體鰭上形成的至少一閘極，該至少一電晶體鰭在一微電子基板102上形成。在本揭露之一實施例中，微電子基板102可以是一單晶矽基板。微電子基板102也可以是其他類型的基板，諸如絕緣體上覆矽(「SOI」)、鍺、砷化鎵、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵,銻化鎵等，它們中的任一者可與矽結合。
該非平面電晶體，繪示為一三閘電晶體，可包括至少一非平面電晶體鰭112。非平面電晶體鰭112可具有一頂面114及一對橫向相對的側壁，各別的側壁116與相對的側壁118。
如圖1中進一步所示，至少一非平面電晶體閘極122可在非平面電晶體鰭112上形成。非平面電晶體閘極122可藉由在非平面電晶體鰭頂面114上或與之相鄰，及在非平面電晶體鰭側壁116及相對的非平面電晶體鰭側壁118上或與之相鄰而形成一閘極介電層124被製作。一閘極電極126可在閘極介電層124上或與之相鄰而形成。在本揭露之一實施例中，非平面電晶體鰭112可延伸在一大體垂直於非平面電晶體閘極122的方向上。
閘極介電層124可由任一種已知的閘極介電材料形成，包括但並不限於，二氧化矽(SiO2)、氮氧化矽(SiOxNy)、氮化矽(Si3N4)，及高k介電材料，諸如氧化鉿、 矽酸鉿、氧化鑭、鋁酸鑭、氧化鋯、矽酸鋯、氧化鉭、氧化鈦、鈦酸鍶鋇、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、鉭酸鈧鉛及鈮鋅酸鉛。熟於此技者將理解的是，閘極介電層124可藉由已知的技術來形成，諸如藉由共形地沈積一閘極介電材料且接著用已知的光蝕刻法及蝕刻技術來使該閘極介電材料形成圖案。
閘極電極126可藉由將討論的本發明之各種不同的實施例來形成。
一源極區及一汲極區(圖1中未示)可在非平面電晶體鰭112中、閘極電極126的兩側形成。在一實施例中，熟於此技者將理解的是，源極及汲極區可藉由摻雜非平面電晶體鰭112而形成。在另一實施例中，熟於此技者將理解的是，源極及汲極區可藉由移除非平面電晶體鰭112的一部分且用(複數)形成源極及汲極區的適當材料替換這些部分而形成。在又一實施例中，源極及汲極區可藉由在鰭112上磊晶成長摻雜或未摻雜的應變層而形成。
圖2-26繪示製造一非平面電晶體之一實施例的側截面圖，其中圖2-5是沿圖1之箭頭A-A及B-B的視圖，圖6-15是沿圖1之箭頭A-A的視圖，且圖16-26是沿圖1之箭頭C-C的視圖。
如圖2中所示，非平面電晶體鰭112可藉由用業內已知的任一種技術蝕刻微電子基板102或藉由在微電子基板102上形成非平面電晶體鰭112而形成。如圖3中所示，一犧牲材料132可沈積在非平面電晶體鰭112上，如圖3中所 示，且一溝槽134可在犧牲材料132中形成以暴露非平面電晶體鰭112的一部分，如圖4中所示。犧牲材料132可以是業內已知的任一種適當的材料，且溝槽134可藉由業內已知的任一種技術來形成，包括但並不限於，微影遮罩及蝕刻。
如圖5中所示，一犧牲閘極136可在溝槽134中形成(參見圖4)。犧牲閘極136可以是任一種適當的材料，諸如多晶矽材料等，且可藉由業內已知的任一種技術沈積在溝槽134中(參見圖4)，包括但並不限於，化學氣相沈積(「CVD」)及物理氣相沈積(「PVD」)。
如圖6中所示，圖5之犧牲材料132可藉由業內已知的任一種技術被移除以暴露犧牲閘極136，諸如選擇性地蝕刻犧牲材料132。如圖7中所示，一共形介電層142可沈積在犧牲閘極136及微電子基板102上。共形介電層142可以是任一種適當的材料，包括但並不限於，氮化矽(Si3N4)及碳化矽(SiC)，且可藉由任一種適當的技術來形成，包括但並不限於，原子層沈積(「ALD」)。
如圖8中所示，圖7之共形介電層142可被蝕刻，諸如藉由利用一適當蝕刻劑的定向蝕刻，以在犧牲閘極136之側壁146上形成一對閘極間隔物144，同時實質上移除與微電子基板102及犧牲閘極136之一頂面148相鄰的共形介電材料層142。據瞭解，在閘極間隔物144形成期間，鰭式間隔物(圖未示)可同時在非平面電晶體鰭112之側壁116及118上形成(參見圖1)。
如圖9中所示，一源極區150a及一汲極區150b可 在閘極間隔物144之任一側上形成。在一實施例中，源極區150a及汲極區150b可在植入N型離子摻雜物的非平面電晶體鰭112中形成。熟於此技者將理解的是，摻雜物植入是在半導性材料中引入雜質以實現改變其傳導率及電子性質之目的的一程序。這一般藉由P型離子(例如，硼)或N型離子(例如，磷)的離子植入來實現，P型離子及N型離子統稱為「摻雜物」。在另一實施例中，部分的非平面電晶體鰭112可藉由業內已知的任一種技術，諸如蝕刻來移除，且源極區150a及汲極區150b可形成以替代移除的部分。在又一實施例中，源極區及汲極區可藉由在鰭112上磊晶成長摻雜的或未摻雜的應變層而形成。在下文中，源極區150a及汲極區將被統稱為「源極/汲極區150」。熟於此技者將理解的是，具有P型源極及汲極的電晶體被稱作「PMOS」或「p通道金屬氧化物半導體」電晶體，且具有N型源極及汲極的電晶體被稱作「NMOS」或「n通道金屬氧化物半導體」電晶體。本說明有關於NMOS電晶體。因此，源極/汲極區150可以是N型。
如圖10中所示，第一介電材料層152可沈積在閘極間隔物144、犧牲閘極頂面148、非平面電晶體鰭112及微電子基板102上。第一介電材料層152可被平面化以暴露犧牲閘極頂面148，如圖11中所示。第一介電材料層152之平面化可藉由業內已知的任一種技術來實現，包括但並不限於化學機械研磨(CMP)。
如圖12中所示，圖11之犧牲閘極136可被移除以 形成一閘極溝槽154。犧牲閘極136可藉由業內已知的任一種技術來移除，諸如選擇性蝕刻。如圖13中所示，閘極介電層124，如同也繪示在圖1中，可被形成為鄰接非平面電晶體鰭112，如先前所討論的。形成閘極介電質124的材料及方法先前已經討論過。
如圖14中所示，一NMOS功函數材料156可共形地沈積在閘極溝槽154內。NMOS功函數材料156可包含包括鋁、鈦及碳的一組成。在一實施例中，按重量計，NMOS功函數材料156可包括約20到40%的鋁，約30到50%的鈦，及約10到30%的碳。在另一實施例中，按重量計，該功函數材料可包括約33%的鋁，約43%的鈦，及約24%的碳。熟於此技者將理解的是，NMOS功函數材料156可藉由一ALD製程共形地沈積以良好地覆蓋非平面電晶體鰭112，且在閘極溝槽154周圍實現一同一的閾值電壓。進一步理解的是，鋁與鈦之比可被調整以調整非平面電晶體100之功函數，而碳可能是ALD製程的一人為因素導入，而非一加入的組分。
如圖15中所示，一閘極填充障蔽158可共形地沈積在NMOS功函數材料156上。閘極填充障蔽158可以是一含鈦材料，包括但並不限於，實質上之純鈦、氮化鈦等。閘極填充障蔽158可藉由任一種已知的技術來形成。在一實施例中，閘極填充障蔽158可以是藉由一化學氣相沈積製程形成的氮化鈦，該化學氣相沈積製程包含在約400℃下利用電漿緻密化來分解四(二甲胺基)鈦(TDMAT)。在又一實施例中，閘極填充障蔽158可以是藉由一原子層沈積製程形成的 氮化鈦，該原子層沈積製程包含在約300℃下的氯化鈦(TiCl)及氨(NH3)脈衝。在又一實施例中，閘極填充障蔽158可以是一雙層的鈦及氮化鈦，其中一鈦層可藉由物理氣相沈積形成，且氮化鈦可如上文所述來形成。閘極障蔽層158可允許在一接著的步驟中使用六氟化鎢來沈積鎢以防止氟腐蝕。在鈦/氮化鈦雙層中使用的鈦層可作用為任何可能擴散通過氮化鈦層的氟的一吸氣劑。
如圖16中所示，一鎢閘極填充材料162可沈積在閘極填充障蔽158上。鎢閘極填充材料162可藉由業內已知的任一種技術形成。在一實施例中，一成核層可被形成，諸如在約300℃下的脈衝二硼烷及六氟化鎢，之後是藉由在約395℃下與氫反應的一六氟化鎢成長的塊體鎢。在一實施例中，鎢閘極填充材料162是一含鎢材料。在另一實施例中，鎢閘極填充材料162是實質上的純鎢。
過量的鎢閘極填充材料162(例如，不在圖16之閘極溝槽154內的鎢閘極填充材料162)可被移除以形成非平面電晶體閘極電極126(還參見圖1)，如圖17中所示。移除過量的鎢閘極填充材料162可藉由業內已知的任一種技術來實現，包括但並不限於，化學機械研磨(CMP)、蝕刻等。
如圖18中所示，非平面電晶體閘極電極126的一部分可被移除以形成一凹口164及一凹入的非平面電晶體閘極166。移除可藉由任一種已知的技術來完成，包括但並不限於，濕式或乾式蝕刻。在一實施例中，凹口的形成可能是由一乾式蝕刻與一濕式蝕刻的組合所導致。例如，鎢 閘極填充材料162可利用一六氟化硫乾式蝕刻而形成凹口，且NMOS功函數材料156可利用後續的一濕式蝕刻而形成凹口。
如圖19中所示，一覆蓋介電材料168可被沈積以填充圖18之凹口164。覆蓋介電材料168可以是任一種適當的材料，包括但並不限於，氮化矽(Si3N4)及碳化矽(SiC)，且可藉由任一種適當的沈積技術形成。覆蓋介電材料168可被平面化以移除過量的覆蓋介電材料168(例如，不在圖16之凹口內的覆蓋介電材料168)以在凹入的非平面電晶體閘極166上及一閘極間隔物144之間形成一覆蓋介電結構170，如圖20中所示。移除過量的覆蓋介電材料168可藉由業內已知的任一種技術來實現，包括但並不限於，化學機械研磨(CMP)、蝕刻等。
如圖21中所示，第二介電材料層172可沈積在第一介電材料層152、閘極間隔物144，及覆蓋介電結構170上。第二介電材料層172可藉由任一種已知的沈積技術，由任一種適當的介電材料形成，包括但並不限於，二氧化矽(SiO2)、氮氧化矽(SiOxNy)，及氮化矽(Si3N4)。如圖22中所示，一蝕刻遮罩174可諸如藉由已知的微影技術在第二介電材料層172上形成具有至少一開口176的圖案。
如圖23中所示，一接觸開口182可藉由蝕穿圖24之蝕刻遮罩開口176而穿過第一介電材料層152及第二介電材料層172被形成，以暴露源極/汲極區150的一部分。圖23之蝕刻遮罩174可在之後被移除，如圖24中所示。在一實施 例中，第一介電材料層152及第二介電材料層172不同於閘極間隔物144及覆蓋介電結構170兩者之介電材料，使得第一介電材料層152及第二介電層172之蝕刻對閘極間隔物144及覆蓋介電結構170可以是選擇性的(即，蝕刻更快)。這在業內被稱作自對準。
如圖25中所示，一導電接觸材料188可沈積在圖23之接觸開口182中。導電接觸材料188可包括但並不限於，多晶矽、鎢、釕、鈀、鉑、鈷、鎳、鉿、鋯、鈦、鉭、鋁、碳化鈦、碳化鋯、碳化鉭、碳化鉿、碳化鋁、其他金屬碳化物、金屬氮化物，及金屬氧化物。應理解的是，在沈積導電接觸材料188之前，各種不同的黏合層、障蔽層、矽化物層，及/或導電層可共形地配置或形成在圖23之接觸開口182中。
如圖26中所示，圖27之過量的導電接觸材料188(例如，不在圖24之接觸開口182內的導電接觸材料188)可被移除以形成一源極/汲極接點190。移除過量的導電接觸材料188可藉由業內已知的任一種技術來實現，包括但並不限於，化學機械研磨(CMP)、蝕刻等。
如上所述，在一實施例中，第一介電材料層152及介電材料層168不同於閘極間隔物144及覆蓋介電結構166兩者之介電材料，使得第一介電材料層152及第二介電層168的蝕刻對閘極間隔物144及覆蓋介電結構166可以是選擇性的(即，蝕刻更快)。因此，凹入的非平面電晶體162在接觸開口182形成期間受到保護。這允許形成一相對較大 尺寸的源極/汲極接點190，這可增加電晶體驅動電流的性能，而源極/汲極接點190與凹入的非平面電晶體閘極162之間不會有短路的風險。
雖然本說明有關於非平面NMOS電晶體，但是應理解的是，包含非平面NMOS電晶體的積體電路也可包括非平面PMOS電晶體。因此，非平面NMOS電晶體的製程可被併入一總體的積體電路製程。
在一實施例中，如圖27中的流程圖之方法200中所示，在形成圖2-13中的結構之後，一PMOS功函數材料，諸如氮化鈦，可沈積在閘極溝槽中，如方塊210中所定義的。如方塊220中所定義的，製造NMOS閘極的區域內的PMOS功函數材料的一部分可被移除，諸如藉由業內已知的抗蝕圖案形成及蝕刻。該方法可接著繼續從圖14開始，諸如使形成圖案的抗蝕劑處於適當的位置，同時沈積NMOS功函數材料。
在一實施例中，如圖28中的流程圖之方法300中所示，在形成圖2-14中的結構之後，製造PMOS閘極的區域內的NMOS功函數材料的一部分可被移除，諸如藉由業內已知的抗蝕圖案形成及蝕刻。如方塊310中所定義的，一PMOS功函數材料，諸如氮化鈦，可沈積在閘極溝槽中，如方塊320中所定義的。該方法可接著繼續從圖15開始。應理解的是，可能不需要單獨形成閘極填充障蔽158，如圖15中所示，因為方塊310中沈積的PMOS功函數也可用作閘極填充障蔽158。
應理解的是，本說明之標的並不一定限於圖1-28中所示之特定應用。熟於此技者將理解的是，該標的可應用於其他微電子裝置製造應用。
已經詳細描述了本發明之實施例，應理解的是，後附申請專利範圍所定義的本發明不欲受上述說明中所提及之特定細節的限制，在不背離其精神或範圍的情況下，許多明顯的變化是可能的。
100‧‧‧非平面電晶體
102‧‧‧微電子基板
112‧‧‧非平面電晶體鰭/鰭
114‧‧‧頂面/非平面電晶體鰭頂面
116‧‧‧側壁/非平面電晶體鰭側壁
118‧‧‧相對的側壁/相對的非平面電晶體鰭側壁/側壁
122‧‧‧非平面電晶體閘極
124‧‧‧閘極介電層/閘極介電質
126‧‧‧閘極電極/非平面電晶體閘極電極

Claims (16)

  1. 一種微電子裝置，其包含有：一基板，其中該基板包含一矽鰭(silicon fin)；在該基板上之一第一介電層，其中該第一介電層包含矽和氧；在該第一介電層上之一第二介電層，其中該第二介電層包含鉿和氧；在該基板上之一對閘極間隔物，其中該等閘極間隔物包含一介電材料；在該第二介電材料之上且在該對閘極間隔物之間的一NMOS金屬閘極電極，其中該NMOS金屬閘極電極包含：接近該對閘極間隔物且在該第二介電層之上的一第一金屬層，其中該第一金屬層包含鋁、鈦和碳；及在該第一金屬層上之一第二金屬層，其中該第二金屬層包含鈦和氮；接近該對閘極間隔物之一者的一源極區，與接近該對閘極間隔物之另一者的一汲極區，其中該源極區和該汲極區包含一n型摻雜物；耦接至該源極區之一第一接點，其中該第一接點包含一鎢材料在一第一障蔽層之上；以及耦接至該汲極區之一第二接點，其中該第二接點包 含一鎢材料在一第二障蔽層之上。
  2. 如請求項1之裝置，其中該NMOS金屬閘極電極係非平面的。
  3. 如請求項1之裝置，其中該NMOS功函數材料包含約20重量百分比至約40重量百分比之間的鋁、約30重量百分比至約50重量百分比之間的鈦、及約10重量百分比至約30重量百分比之間的碳。
  4. 如請求項1之裝置，進一步包括配置成與該NMOS金屬閘極電極相鄰且在該對閘極間隔物之間的一覆蓋介電結構。
  5. 如請求項1之裝置，其中該第二介電層包含一高k介電層。
  6. 如請求項1之裝置，其中該第一金屬層包含一功函數層。
  7. 如請求項1之裝置，其中該第二金屬層包含一障蔽層。
  8. 一種微電子裝置，其包含有：一基板，其中該基板包含一矽鰭；在該基板上之一第一介電層，其中該第一介電層包含矽和氧；在該第一介電層上之一第二介電層，其中該第二介電層包含鉿和氧；在該基板上之一對閘極間隔物，其中該等閘極間隔物包含一介電材料；在該第二介電層之上且在該對閘極間隔物之間的一NMOS金屬閘極電極，其中該NMOS金屬閘極電極包 含：接近該對閘極間隔物且在該第二介電層之上的一第一金屬層，其中該第一金屬層包含鈦和氮；及在該第一金屬層上之一第二金屬層，其中該第二金屬層包含鎢；接近該對閘極間隔物之一者的一源極區，與接近該對閘極間隔物之另一者的一汲極區，其中該源極區和該汲極區包含一n型摻雜物；耦接至該源極區之一第一接點，其中該第一接點包含一鎢材料在一第一障蔽層之上；以及耦接至該汲極區之一第二接點，其中該第二接點包含一鎢材料在一第二障蔽層之上。
  9. 如請求項8之裝置，其中該NMOS金屬閘極電極係非平面的。
  10. 如請求項8之裝置，其中該NMOS功函數材料包含約20重量百分比至約40重量百分比之間的鋁、約30重量百分比至約50重量百分比之間的鈦、及約10重量百分比至約30重量百分比之間的碳。
  11. 如請求項8之裝置，進一步包括配置成與該NMOS金屬閘極電極相鄰且在該對閘極間隔物之間的一覆蓋介電結構。
  12. 如請求項8之裝置，其中該第二介電層包含一高k介電層。
  13. 如請求項8之裝置，其中該第一金屬層包含一障蔽層。
  14. 如請求項8之裝置，其中該第二金屬層包含一填充層。
  15. 一種微電子總成，其包含有：一第一電晶體，其包含有：一基板，其中該基板包含一矽鰭；在該基板上之一第一介電層，其中該第一介電層包含矽和氧；在該第一介電層上之一第二介電層，其中該第二介電層包含鉿和氧；在該基板上之一對閘極間隔物，其中該等閘極間隔物包含一介電材料；在該第二介電材料之上且在該對閘極間隔物之間的一NMOS金屬閘極電極，其中該第一NMOS金屬閘極電極包含：接近該對閘極間隔物且在該第二介電層之上的一功函數層，其中該功函數層包含鋁、鈦和碳；及在該功函數層上之一障蔽層，其中該障蔽層包含鈦和氮；接近該對閘極間隔物之一者的一源極區，與接近該對閘極間隔物之另一者的一汲極區，其中該源極區和該汲極區包含一n型摻雜物；耦接至該源極區之一第一接點，其中該第一接點包含一鎢材料在一第一障蔽層之上；耦接至該汲極區之一第二接點，其中該第二接 點包含一鎢材料在一第二障蔽層之上；以及一第二電晶體，其包含有：一基板，其中該基板包含一矽鰭；在該基板上之一第一介電層，其中該第一介電層包含矽和氧；在該第一介電層上之一第二介電層，其中該第二介電層包含鉿和氧；在該基板上之一對閘極間隔物，其中該等閘極間隔物包含一介電材料；在該第二介電材料之上且在該對閘極間隔物之間的一NMOS金屬閘極電極，其中該NMOS金屬閘極電極包含：在該高k介電材料上之一障蔽層，其中該障蔽層包含鈦和氮；及在該含有鈦的障蔽材料上之一含有鎢的閘極填充材料；接近該對閘極間隔物之一者的一源極區，與接近該對閘極間隔物之另一者的一汲極區，其中該源極區和該汲極區包含一n型摻雜物；耦接至該源極區之一第一接點，其中該第一接點包含一鎢材料在一第一障蔽層之上；以及耦接至該汲極區之一第二接點，其中該第二接點包含一鎢材料在一第二障蔽層之上。
  16. 如請求項15之總成，其中該總成包含一積體電路之一部 分。
TW104131442A 2011-09-30 2012-09-20 用於非平面電晶體之鎢閘極技術（二） TWI585980B (zh)

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