CN103858215B - 非平坦晶体管以及其制造的方法 - Google Patents

非平坦晶体管以及其制造的方法 Download PDF

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CN103858215B
CN103858215B CN201180073727.7A CN201180073727A CN103858215B CN 103858215 B CN103858215 B CN 103858215B CN 201180073727 A CN201180073727 A CN 201180073727A CN 103858215 B CN103858215 B CN 103858215B
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planar transistors
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CN103858215A (zh
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S·M·乔希
M·哈藤多夫
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Intel Corp
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Abstract

本发明涉及在非平坦晶体管内形成源/漏结构，其中从非平坦晶体管除去鳍间隔件，以便从非平坦晶体管鳍形成源/漏结构，或者用合适的材料代替非平坦晶体管鳍，形成源/漏结构。

Description

非平坦晶体管以及其制造的方法
技术领域
本说明书的实施方案通常涉及微电子器件制造领域，并且更具体地涉及非平坦晶体管的制造。
附图简述
在本说明书的结论部分特别指出了本公开内容的主题，并且清楚地要求其权利。参考以下附图，根据以下的说明及所附的权利要求，本公开内容的上述以及其它特征将进一步变得显而易见。应当理解附图仅描绘了根据本公开内容的几个实施方案，因此，不应认为其是对保护范围的限定。通过使用附图，以更多的特征和细节说明本公开内容，这样可以更容易确定本公开内容的优点，其中：
图1是根据本说明书的一个实施方案的非平坦晶体管结构的透视图。
图2根据本说明书的一个实施方案，举例说明了沉积在非平坦晶体管的晶体管栅极和晶体管鳍(fin)上面的介电材料的侧面剖视图。
图3举例说明了在晶体管栅极和晶体管上由介电材料形成晶体管栅极间隔件和晶体管鳍间隔件之后，图2结构的侧面剖视图。
图4根据本说明书的一个实施方案，举例说明了在介电材料上形成帽盖(capping)材料层之后，图2结构的侧面剖视图。
图5根据本说明书的一个实施方案，举例说明了一部分帽盖材料层暴露形成牺牲层之后，图4结构的侧面剖视图。
图6根据本说明书的一个实施方案，举例说明了改变暴露的帽盖材料层之后，图5结构的侧面剖视图。
图7根据本说明书的一个实施方案，举例说明了其中帽盖结构在晶体管栅极上的介电材料上形成的图6结构的侧面剖视图。
图8根据本说明书的一个实施方案，举例说明了在定向蚀刻处理过程中图7结构的侧面剖视图。
图9根据本说明书的一个实施方案，举例说明了在定向蚀刻处理之后图8结构的侧面剖视图，其中在介电体从晶体管鳍除去的时候介电材料留在晶体管栅极上。
图10根据本说明书的一个实施方案，举例说明了用掺杂剂植入图9的鳍，形成源/漏结构。
图11根据本说明书的一个实施方案，举例说明了除去晶体管鳍之后图9结构的侧面剖视图。
图12根据本说明书的一个实施方案，举例说明了如图11所示除去晶体管鳍之后形成的源/漏结构的侧面剖视图。
图13根据本说明书的一个实施方案，举例说明了从晶体管鳍间隔件之间除去晶体管鳍而形成开口之后，图3结构的侧面剖视图。
图14举例说明了用源/漏材料填充晶体管鳍间隔件之间的开口之后，图13结构的侧面剖视图。
图15根据本说明书的一个实施方案，举例说明了用非定向蚀刻除去晶体管鳍间隔件期间图14结构的侧面剖视图。
图16根据本说明书的一个实施方案，举例说明了用非定向蚀刻除去晶体管鳍间隔件之后，图15结构的侧面剖视图。
图17所示为根据本发明的一个实施方案，形成不含间隔件的源/漏结构的方法的流程图。
图18所示为根据本发明的另一个实施方案，形成不含间隔件的源/漏结构的方法的流程图。
具体实施方式
在下面的详细说明中，以举例说明的方式参考了附图，显示了可以实施所要求权利的主题的具体实施方案。这些实施方案足够详细地进行了说明，使本领域技术人员能够实施主题。应当理解，各个实施方案尽管不同，并不一定互相排斥。例如，本说明书所述的具体特征、结构、或特性，涉及一个实施方案，仍可以在其它实施方案内实施，只要不偏离要求保护权利的主题的精神和范围。本说明书内所述的“一个实施方案”或“实施方案”是指针对实施方案说明的具体的特征、结构、或特性被包括在本发明范围的至少一个实施方案中。因此，使用术语“一个实施方案”或“实施方案”不一定必须指相同的实施方案。此外应当理解，每个所公开的实施方案内的单个因素的位置或布置可以修改，而不会偏离要求保护权利的主题的精神和范围。因此，以下的详细说明不应从限定意义上理解，主题的范围仅仅由所附的权利要求所定义，并且应与所附权利要求要求权利的等同物的所有范围一起进行合理解读。在附图中，类似的附图标记贯穿几个视图，表示相同或类似的元件或功能，并且其中描绘的因素不一定互相合乎比例，而是单个的因素可以放大或缩小，以便在本说明书语境中更容易理解所述因素。
在非平坦晶体管如三栅极晶体管和FinFET制造中，非平坦半导体坯体可以用来形成能以极小的栅极长度(如低于约30nm)完全耗竭(depletion)的晶体管。这些半导体坯体通常为鳍状，因此，通常称为晶体管“鳍”。例如在三栅极晶体管中，晶体管鳍具有一个上表面和两个相对的侧壁，其形成在块状半导体基底或绝缘体基底上的硅(silicon-on-insulatorsubstrate)上。栅极介电体可以形成在半导体坯体的表面和侧壁上，栅极电极可以形成在半导体坯体上表面上的栅极介电体上，并且邻近于半导体坯体侧壁上的栅极介电体。这样，由于栅极介电体和栅极电极邻近于半导体坯体的三个表面，所以可以形成三个独立的通道和栅极。由于形成有三个独立的通道，当晶体管打开时半导体坯体可以完全地耗尽。对于finFET晶体管，栅极材料和电极体只接触半导体坯体的侧壁，这样形成两个独立的通道(而不是三栅极晶体管中的三个通道)。
本说明书的实施方案涉及在非平坦晶体管内形成源/漏结构，其中将鳍间隔件从非平坦晶体管除去，以便从非平坦晶体管鳍形成源/漏结构，或者用合适的材料代替非平坦晶体管鳍形成源/漏结构。
图1是非平坦晶体管100的透视图，其显示为三栅极晶体管，由形成在(from on)或者来自基底102的至少一个非平坦晶体管112、和形成在非平坦晶体管鳍112的上面的至少一个非平坦晶体管栅极122构成。在本公开内容的实施方案中，基底102可以是单晶硅基底。基底102还可以是其它类型的基底，如绝缘体上硅(“SOI”)、锗、砷化镓，锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、锑化镓等，其任何均可以与硅组合。
如图1所示，非平坦晶体管鳍112可以有上表面114和一对侧向相对的侧壁，第一侧壁116和相对的第二侧壁118，非平坦晶体管栅极122可以有上表面134和一对侧向相对的侧壁，第一侧壁136和相对的第二侧壁138。如图1进一步所示，晶体管栅极122可以在非平坦晶体管鳍112之上制造：通过在晶体管鳍的上表面114之上或者附近形成栅极介电层124，以及在第一晶体管鳍侧壁116和相对的第二晶体管鳍侧壁118之上或附近形成栅极介电层124。栅极电极126可以形成在栅极介电层124之上或附近。在本公开内容的一个实施方案中，晶体管鳍112可以沿基本上垂直于晶体管栅极122的方向延伸。
栅极介电层124可以由任何众所周知的栅极介电材料形成，包括但不限于二氧化硅(SiO2)、氮氧化硅(SiOxNy)、氮化硅(Si3N4)、和高k介电材料如氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽、和铌酸铅锌。进一步，栅极介电层124可以由众所周知的方法形成，例如通过沉积栅极电极材料，如化学气相沉积(“CVD”)、物理气相沉积(“PVD”)、原子层沉积(“ALD”)，然后用众所周知的光刻方法和蚀刻技术使栅极电极材料形成图样，如本领域技术人员可以理解的。
栅极电极126可以由任何合适的栅极电极材料形成。在本公开内容的一个实施方案中，栅极电极126可以由包括但不限于以下的材料形成：多晶硅、钨、钌、钯、铂、钴、镍、铪、锆、钛、钽、铝、碳化钛、碳化锆、碳化钽、碳化铪、碳化铝、其它的金属碳化物、金属氮化物、和金属氧化物。而且，栅极电极126可以由众所周知的方法形成，例如通过毯状沉积栅极电极材料，然后用众所周知的光刻方法和蚀刻技术使栅极电极材料形成图样，如本领域技术人员可以理解的。
源区和漏区(未显示)可以形成在栅极电极126相对侧上。在一个实施方案中，源区和漏区可以通过掺杂晶体管鳍112形成，如将要讨论的。在另一个实施方案中，可以通过除去部分晶体管鳍112，并用适当的材料替代这些部分形成源和漏结构，从而形成所述源和漏结构，如将讨论的。
图2-13举例说明了沿着箭头A的图1非平坦晶体管栅极122的侧面截面图，以及沿着箭头B的图1非平坦晶体管鳍112的侧面截面图。
如图2中所举例说明的，介电材料层142可以共形沉积在图1的非平坦晶体管100的上方，以覆盖非平坦晶体管栅极122和非平坦晶体管鳍112。如本领域技术人员所知，沉积在涂敷目标所有的暴露表面上时，共形沉积的材料具有基本上相同的厚度。介电材料层142可以由众所周知的任何栅极介电材料形成，其包括但不限于二氧化硅(SiO2)、氮氧化硅(SiOxNy)、氮化硅(Si3N4)和高k的介电材料，可以通过本领域中已知的任何合适技术共形沉积。
可以对图2的介电材料层142进行蚀刻，例如用合适蚀刻剂的定向蚀刻(如箭头150所示)，以及通过任何已知的技术，除去最紧邻非平坦晶体管栅极上表面134的一部分介电材料层142，形成邻近非平坦晶体管栅极侧壁136和138的间隔件144，并同时在非平坦晶体管鳍侧壁116和118上形成间隔件146，同时基本上除去邻近基底102的介电材料层142，如图3所示。如本领域技术人员所知，可以进行定向蚀刻，以沿着特定的轴蚀刻材料。如本领域技术人员进一步所知，间隔件(例如元件144和146)为在微电子器件如晶体管中在导电结构侧壁附近形成的薄的介电材料层，以对那些导电结构进行电气隔离。尽管需要非平坦晶体管栅极间隔件144来限定非平坦晶体管栅极122与随后形成的源和漏结构(下文中总称为“源/漏结构”)分离，但非平坦晶体管鳍间隔件146的形成可能会妨碍所要求的源/漏结构的限定与形成，或者可能会妨碍所要求的将非平坦晶体管鳍112改成源/漏结构，如将要讨论。
图4-9举例说明了用于除去非平坦晶体管鳍间隔件146、而不用除去非平坦晶体管栅极间隔件144的方法的一个实施方案。如图4所示，帽盖材料层152，如化学气相沉积形成的二氧化硅层，可以形成在介电材料层142之上。如图5所示，牺牲层154可以形成在帽盖材料层152之上，并且可以凹进，以暴露帽盖材料层152的一部分158。可以通过任何的蚀刻技术，如干蚀刻，以实现牺牲层154的凹进。如图6所示，帽盖材料层152的暴露部分158可以被改变的是蚀刻特征，如高剂量的离子植入，如箭头162所显示。对于高剂量的离子植入，植入剂量应该足够的高，以使帽盖材料层152的植入部分产生成分变化。可以除去牺牲层154，如通过灰化，随后进行清洁步骤及高温退火(以结合植入的离子)，并且可以除去未改变的帽盖材料152，如通过蚀刻，以形成帽盖结构164，其最接近(proximate)非平坦晶体管栅极122的上部166，后者最接近非平坦晶体管栅极的上表面134，如图7所示。应当理解帽盖结构164可以是任何的合适材料，如光阻材料，如本领域技术人员可以理解的。
如图8所示，定向蚀刻(箭头156所图示说明)可以在介电材料层142上进行，以朝向基底102的方向蚀刻。通过这样的定向蚀刻168，帽盖结构164保护邻近非平坦晶体管栅极122的介电材料层142，而介电材料层142邻近基底102和非平坦晶体管鳍112。这可以导致一部分介电材料层142保留邻近于非平坦晶体管栅极122，而基本上全部的介电材料层142被从非平坦晶体管鳍112去除，如图9所示。一旦所述部分的介电材料层142已从非平坦晶体管鳍112除去，至少一部分非平坦晶体管鳍112可以被植入掺杂剂(箭头172所指示)，以形成源/漏结构174，如图10所示。如本领域技术人员可以理解，掺杂剂的植入是为了改变其导电性和电子学性能的目的，将杂质引入到半导体材料中的方法。其通常通过P型离子(如硼)或N型离子(如磷)的离子植入而实现，其总称为“掺杂剂”。如图10中进一步所示，为了实现非平坦晶体管鳍112的均匀掺杂，掺杂剂可以以某一角度、从非平坦晶体管鳍112的每一侧植入172到晶体管鳍112中。
在另一个实施方案中，非平坦晶体管鳍112(参见图9)可以通过本领域中已知的任何技术除去，如蚀刻，如图11所示。在一个实施方案中，非平坦晶体管鳍112可以用气体如溴化氢、三氟化氮和六氟化硫，通过等离子蚀刻方法除去，或者用溶液如氢氧化铵、氢氧化钾、四甲基氢氧化铵等，通过湿蚀刻除去。
一旦除去了非平坦晶体管鳍112，可以在其位置形成源/漏结构182，如图12所示。可以通过任何已知的制造方法制造源/漏结构182，包括但不限于光刻方法、和蚀刻方法。在一个实施方案中，源/漏结构182可以是外延生长的硅、硅锗、硅/锗/锡、锗、碳化硅等，并且可以包括掺杂剂，如硼或磷(如前面所讨论的)。如本领域技术人员可以理解，用于制造源/漏结构182的材料可以设计成对于其被用于其中的非平坦晶体管100(参见图1)具有基本上最佳的性能。
在又另一个实施方案中，从图3开始，非平坦晶体管鳍112可以通过本领域中已知的任何技术如蚀刻，从非平坦晶体管鳍间隔件146之间除去，形成开口148，如图13所示。一旦非平坦晶体管鳍112已去除(参见图3)，就可以在开口148内(参见图13)布置合适的源/漏材料，以形成源/漏结构184，如图14所示。如图14可看出，源/漏结构184的尺寸基本上受原来的非平坦晶体管鳍112的尺寸限制，对于非平坦晶体管100(参见图1)的性能而言，这可能不是最佳的。
因此，可以在形成源/漏结构之前除去非平坦晶体管鳍间隔件146。如图15所示，可以在非平坦晶体管栅极间隔件144和非平坦晶体管鳍间隔件146上进行非定向蚀刻(箭头192所示)。如本领域技术人员所知，非定向蚀刻可以以基本上相同的速度蚀刻待蚀刻材料的全部暴露表面。由于非定向蚀刻172不但蚀刻非平坦晶体管鳍间隔件146的外表面146a，而且蚀刻其内表面146b(即在开口148内)，所以非平坦晶体管鳍间隔件146被蚀刻掉的速度比非平坦晶体管栅极间隔件144的速度更快，后者只蚀刻其外表面144a。因此，如图16所示，可以除去非平坦晶体管鳍间隔件146(参见图15)，而非平坦晶体管栅极间隔件144可能仅仅变薄，但仍存在。一旦除去了非平坦晶体管鳍间隔件146(参见图15)，如图16所示，就可以形成源/漏结构182，如图12所示及针对其所讨论的。
图17的流程图200举例说明了本说明书形成非平坦晶体管的一个方法的实施方案。如框210所定义，非平坦晶体管鳍可以形成在基底上。非平坦晶体管栅极可以形成在非平坦晶体管鳍的上面，如框220中所定义。介电材料层可以共形沉积在非平坦晶体管栅极和非平坦晶体管鳍的上面，如框230中所定义。如框240中所定义的，邻近非平坦晶体管栅极的一部分介电材料层可以形成为间隔件。邻近非平坦晶体管鳍的一部分介电材料可以在形成非平坦晶体管栅极间隔件的同时除去，如框250中所定义。然后可以形成非平坦源/漏结构，如框260中所定义。
图18的流程图300举例说明了本说明书形成非平坦晶体管的一个方法的实施方案。如框310所定义，非平坦晶体管鳍可以形成在基底上。非平坦晶体管栅极可以形成在非平坦晶体管鳍的上面，如框320中所定义。介电材料层可以共形沉积在非平坦晶体管栅极和非平坦晶体管鳍的上面，如框330中所定义。如框340中所定义，邻近非平坦栅极的一部分介电材料层可以形成为非平坦栅极间隔件，而邻近非平坦晶体管鳍的一部分介电材料层可以同时形成为非平坦鳍间隔件。可以除去非平坦晶体管鳍，如框350中所定义。如框360所示，非平坦晶体管鳍间隔件可以在除去非平坦晶体管鳍之后除去。可以在除去非平坦晶体管鳍间隔件之后形成非平坦源/漏结构，如框370所示。
应当理解，本发明的主题不必限定于图1-18中举例说明的特定应用。所述主题可以应用于其它的微电子器件制造应用，如本领域技术人员可以理解的。进一步，所述主题也可以应用于微电子器件制造以外的任何合适的应用。
虽然以本发明详细实施方案进行了这样的描述，应该理解，所附权利要求所定义的本发明不受上述说明所阐述的具体细节限制，因为其可以有许多显而易见的变化，而不偏离其精神和范围。

Claims (9)

1.一种制造非平坦晶体管的方法，其包括：
在基底上形成非平坦晶体管鳍；
在非平坦晶体管鳍的上面形成非平坦晶体管栅极；
在非平坦晶体管栅极和非平坦晶体管鳍的上面共形沉积介电材料层；以及
由邻近非平坦晶体管栅极侧壁的一部分介电材料层形成非平坦晶体管栅极间隔件，并且除去邻近非平坦晶体管鳍的介电材料层，
其中形成非平坦晶体管栅极间隔件和除去邻近非平坦晶体管鳍的介电材料层是同时进行的，
其中由邻近非平坦晶体管栅极侧壁的一部分介电材料层形成非平坦晶体管栅极间隔件，并且除去邻近非平坦晶体管鳍的介电材料层包括：
在最紧邻非平坦晶体管栅极上部的一部分介电材料层上形成帽盖结构，包括：
在介电材料层的上面形成帽盖材料层；
在帽盖材料层的上面形成牺牲层；
使牺牲层凹进，以暴露一部分帽盖材料层；
改变帽盖材料层暴露部分的蚀刻特征；
除去牺牲层；以及
除去帽盖材料层的未改变部分；以及
定向蚀刻邻近非平坦晶体管鳍的一部分介电材料层。
2.根据权利要求1所述的方法，其中改变帽盖材料层暴露部分的蚀刻特征包括离子掺杂帽盖材料层的暴露部分。
3.根据权利要求2所述的方法，其还包括对帽盖材料层的离子掺杂部分进行退火。
4.根据权利要求1所述的方法，其还包括形成邻近非平坦晶体管栅极的源/漏结构。
5.根据权利要求4所述的方法，其中形成源/漏结构包括用掺杂剂植入一部分非平坦晶体管鳍。
6.根据权利要求5所述的方法，其中用掺杂剂植入一部分非平坦晶体管鳍包括用P型掺杂剂植入所述部分的非平坦晶体管鳍。
7.根据权利要求5所述的方法，其中用掺杂剂植入一部分非平坦晶体管鳍包括用N型掺杂剂植入所述部分的非平坦晶体管鳍。
8.根据权利要求4所述的方法，其中形成源/漏结构包括除去一部分非平坦晶体管鳍，以及用源/漏结构替代它。
9.根据权利要求8所述的方法，其中替代源/漏结构包括外延生长地形成含硅的源/漏结构。
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