CN103633011B - 集成电路结构的形成方法 - Google Patents
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
本发明提供一种集成电路结构的形成方法,该方法包括下列步骤:提供一半导体基底;形成多个图案化元件于半导体基底上,其中图案化元件之间具有沟槽;以第一导电材料填入该沟槽,其中第一导电材料具有第一上表面,其高于图案化元件的上表面;进行第一平坦化以降低第一导电材料的第一上表面,直到露出图案化元件的上表面;沉积第二导电材料,其中第二导电材料具有第二上表面,其高于图案化元件的上表面;以及,进行第二平坦化以降低第二导电材料的第二上表面,直到露出图案化元件的上表面。本发明的方法可明显降低,甚至完全消除碟化效应与空洞。
Description
本申请是申请日为2009年4月17日、申请号为200910133199.4、发明名称为“集成电路结构的形成方法”申请的分案申请。
技术领域
本发明涉及集成电路,且涉及一种集成电路工艺中的填沟(gap-filling)技术,尤其涉及降低填沟工艺的碟化(dishing)效应与空洞(void)。
背景技术
化学机械研磨(CMP;Chemical Mechanical Polishing)为半导体晶片的一种平坦化工艺,特别是用在填沟工艺中。CMP利用物理与化学上的协同作用来研磨晶片。研磨时将晶片放置在研磨垫上,从晶背施加压力,并使晶片与研磨垫作反向旋转,而带有研磨粒子与反应性化学成份的研磨浆在研磨时被配输到研磨垫表面。CMP可以真正达到晶片表面全面性的平坦化。
CMP工艺会有图案化效应的问题。当图案密度不同时会有所谓的“微负载效应(micro-loading effect)”,因而降低图案尺寸的一致性。微负载效应是当同时蚀刻或研磨高密度图案与低密度图案时,由于两个区域的蚀刻/研磨速率不同所造成。因为蚀刻/研磨的反应在不同图案密度的区域变得局部过高或过低,加上大量的蚀刻反应产物无法顺利排出,使得蚀刻速率不一致。当图案的密度差异很大时,会使研磨后的膜厚产生极大的差异。上述的不一致会造成所谓的碟化(dishing)效应,“碟化”指低图案密度的位置,因为其研磨速率大于高图案密度区,因而形成碟状的表面。
图1~图3显示一利用CMP的传统填沟工艺。请参照图1,在半导体基底300上形成多晶硅图案302。多晶硅图案302包括图案密集区与图案疏离区,其中图案密集区比起图案疏离区有更高的图案密度与更小的图案间距。请参照图2,沉积内层介电层304以填入多晶硅图案302之间的沟槽,并使其高度超过多晶硅图案302的上表面。由于多晶硅图案302的表面构型(topography)被部分转移到内层介电层304的上表面,因此内层介电层304的上表面呈现不平坦。此外,特别是在图案密集区可能会出现空洞(void)306,因为该处的沟槽具有相对较高的深宽比(aspect ratio)。
请参照图3,利用CMP工艺去除多余的内层介电层304。该CMP工艺去除位于多晶硅图案302上方的内层介电层304,直到露出多晶硅图案302的上表面。由于图案密集区与图案疏离区的图案密度不同,造成不均匀的CMP。例如,内层介电层304的上表面构型在图案密集区的受到的影响比起图案疏离区较不明显,因此,造成图案疏离区出现碟化效应,因而影响到后续的工艺。另一方面,CMP可能会使空洞306露出,进而在后续工艺中被填入不想要的导电材料,导致集成电路短路或增加阻容延迟(RC delay)。
目前已经有许多方法被提出来以解决或降低微负载效应。例如,在图案疏离区制作闲置图案(dummy pattern)以增加其图案密度。然而,使用闲置图案可能会增加阻容延迟,而且有些区域并不适合形成闲置图案。因此,有需要提出一种新的填沟方法以降低微负载效应。
发明内容
本发明的目的在于提供一种集成电路结构的形成方法,以克服现有技术的缺陷。
本发明提供一种集成电路结构的形成方法,包括下列步骤:提供一半导体基底;形成多个图案化元件于半导体基底上,其中图案化元件之间具有沟槽;以第一导电材料填入该沟槽,其中第一导电材料具有第一上表面,其高于图案化元件的上表面;进行第一平坦化以降低第一导电材料的第一上表面,直到露出图案化元件的上表面;沉积第二导电材料,其中第二导电材料具有第二上表面,其高于图案化元件的上表面;以及,进行第二平坦化以降低第二导电材料的第二上表面,直到露出图案化元件的上表面。
本发明另提供一种集成电路结构的形成方法,包括下列步骤:提供一半导体基底;形成多个栅极条于该半导体基底上,其中栅极条之间具有沟槽,且其中集成电路结构包括一图案密集区与一图案疏离区,栅极条于图案密集区的图案密度大于该图案疏离区;形成一接触蚀刻停止层,其具有第一部分直接位于栅极条上及第二部分位于沟槽中;以第一内层介电层填入沟槽中,其中第一内层介电层具有第一上表面,其高于栅极条的上表面;进行第一化学机械研磨,直到第一内层介电层的第一上表面不高于接触蚀刻停止层的第一部分的上表面;沉积第二内层介电层于第一内层介电层与栅极条上;以及,进行第二化学机械研磨,直到第二内层介电层的第二上表面不高于接触蚀刻停止层的第一部分的上表面。
本发明又提供一种集成电路结构的形成方法,包括下列步骤:提供一半导体基底;形成一介电层于半导体基底上;于介电层中形成多个开口;以第一导电材料填入开口,其中第一导电材料的上表面高于该介电层的上表面;对第一导电材料进行第一化学机械研磨以露出介电层的上表面;形成第二导电材料于第一导电材料与介电层上;以及,对第二导电材料进行第二化学机械研磨以露出介电层的上表面。
实验证实,借由本发明实施例的方法可明显降低,甚至完全消除碟化效应与空洞。
为让本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举出优选实施例,并配合附图,作详细说明如下:
附图说明
图1~图3为一系列剖面图,用以说明公知利用CMP的填沟工艺。
图4~图7B为一系列剖面图,用以说明本发明一优选实施例的中间工艺,其进行一次以上的CMP工艺来降低微负载效应。
图8显示形成金属栅极以取代图7A的多晶硅条。
图9A与图9B显示在金属间介电层中形成接触插塞。
图10~图14显示一镶嵌工艺,其进行一次以上的CMP工艺来形成金属线。
其中,附图标记说明如下:
【公知技术】
300~半导体基底
302~多晶硅图案
304~内层介电层
306~空洞
【实施例】
20~半导体基底
22~栅极条
24~栅介电质
26~接触蚀刻停止层
100~图案密集区
200~图案疏离区
30、40~内层介电层
32~栅极条22的上表面
34~接触蚀刻停止层26的上表面
36~隆起物
38~空洞
H1~内层介电层30多余的高度
H2~内层介电层40多余的高度
50~栅介电质
52~栅极
56~内层介电层
58~接触插塞
60~介电层
61~CMP停止层
62~开口
300~图案密集区
400~图案疏离区
64~导电元件
66~扩散阻障层
68、74~导电材料
70~隆起物
具体实施方式
本发明提供一新颖的填沟工艺,以下将说明本发明一优选实施例的中间工艺,并讨论不同的变化例。在图示与实施例中,类似的元件将以类似的附图标记来标示。
请参照图4,提供一半导体基底20。在优选实施例中,半导体基底20包含硅,但可也可包含其他常见的材料,例如碳、锗、镓等。半导体基底20可以是一单晶或化合物材料;可以是块材(bulk)基底或绝缘层上半导体基底(SOI;semiconductor-on-insulator)。
在半导体基底20上形成栅极条(gate strips)22与栅介电质24。在一实施例中,栅极条22是由掺杂多晶硅所构成,因此也可称为多晶硅条22。在另一实施例中,栅极条22是由其他导电材料所构成,例如金属、金属硅化物、金属氮化物等。栅介电质24的材料可为氧化硅、氮氧化硅、高介电常数材料、或其他适合作为栅介电质的介电材料。上述的集成电路结构可还包括其他元件,例如栅极间隔物、源极/漏极区、硅化物(未显示)、接触蚀刻停止层26等。因此,例如当采用栅极优先(gate-first)工艺的话,栅极条22的顶部可包含金属硅化物。此外,栅极条22可包含或不包含闲置图案。
图4所示的结构包含图案密集区100与图案疏离区200。栅极条22在图案密集区100的图案密度高于图案疏离区200。因此,栅极条22在图案密集区100的平均距离D1小于在图案疏离区200的平均距离D2。
形成内层介电层30以填入栅极条22之间的沟槽。优选可进行一过度填充(overfill),使内层介电层30上表面的低点高于栅极条22的上表面32。如果有形成接触蚀刻停止层26,则使内层介电层30上表面的低点高于接触蚀刻停止层26的上表面34。内层介电层30的材料可为硼磷硅玻璃(BPSG)、硼硅玻璃(BSG)、碳掺杂低介电常数材料、氧化硅等。在一实施例中,可利用化学气相沉积法(CVD;Chemical Vapor Deposition),例如等离子体加强CVD、低压CVD等方式来形成内层介电层30。如此一来,栅极条22的表面构型将有至少一部分被转移到内层介电层30的上表面,因而形成隆起物36。隆起物36在图案密集区100的间距小于在图案疏离区200的间距。由于沟槽具有高深宽比,可能会有空洞38形成。
进行第一CMP工艺以移除多余的内层介电层30,并将其上表面平坦化。在第一实施例中,如图5A所示,CMP停在接触蚀刻停止层26的上表面34,此时接触蚀刻停止层26也作为CMP停止层。如此一来,露出了接触蚀刻停止层26直接位于栅极条22上方的部分。在图案密集区100由于栅极条22的间距相对较小,即使有碟化效应的话也是相对较小,且接触蚀刻停止层26露出的上表面34与栅极条22之间的内层介电层30等高或大致等高。然而,为了露出空洞38,可进行一过度CMP以稍微降低内层介电层30的上表面。在图案疏离区200可能造成显著的碟化效应,其中接触蚀刻停止层26露出的上表面34高于栅极条22之间的内层介电层30。
图5B显示本发明另一实施例,其中第一CMP停在栅极条22的上表面32,该上表面可包括金属硅化物。该实施例可能是因为没有形成接触蚀刻停止层26,或是因为使用了会攻击接触蚀刻停止层26,但不攻击栅极条22的研磨浆所导致。如此一来,露出了栅极条22的上表面32。优选地,经过第一CMP后,露出整个晶片上的栅极条22的上表面32。
图6显示沉积内层介电层40。内层介电层40的材料可与内层介电层30相同或不同。内层介电层40完全填满第一CMP所造成的碟化区域。优选地,当有空洞露出时,内层介电层40也填入空洞38。内层介电层40的上表面优选高于栅极条22的上表面32(以及接触蚀刻停止层26的上表面34,如果存在的话)。内层介电层40多余的高度H2最好低于内层介电层30多余的高度H1(参见图4),使后续进行第二CMP时较不费力,如图7A与图7B所示。
图7A与图7B显示进行第二CMP后的结构。在一实施例中,如图7A所示,第二CMP停在接触蚀刻停止层26的上表面34。在另一实施例中,如图7B所示,在第二CMP后露出栅极条22的上表面32。此实施例可能是没有形成接触蚀刻停止层26,或是接触蚀刻停止层26在第一CMP或第二CMP中被移除。第二CMP的优点在于,内层介电层40的碟化效应明显小于内层介电层30的碟化效应,其部分原因可能是因为内层介电层40没有隆起物,而内层介电层30具有隆起物36(参见图4)。
如果内层介电层30与40的碟化效应仍然显著,可重复进行图6与图7A或图7B的步骤以进一步降低碟化效应。
请参照图8,将多晶硅条22与先前形成的介电质24从内层介电层30/40移除,以形成开口(即相当于图中元件50与52的位置)。之后,毯覆性(blanket)沉积一栅介电层,优选为高介电常数材料,接着以一金属材料将开口填满。进行CMP移除内层介电层30/40上多余的栅介电层与金属材料后,留下开口中的栅介电层与金属材料分别形成MOS元件的栅介电质50与栅极52。在图9A中,形成一额外的内层介电层56,并在内层介电层56中形成接触插塞58。接触插塞58电性连接置至栅极52与源极/漏极区(未显示)。
图9B显示本发明另一实施例。该实施例的初始步骤基本上与图4到图6相同,除了内层介电层40的高度是配合形成接触插塞58的高度所决定。在形成内层介电层40后,进行轻微的CMP使其上表面齐平。然后在内层介电层30/40中形成接触插塞58以连接栅极条22与源极/漏极区(未显示)。
图4至图7B所示的方法可以应用在不同材料的填沟技术。例如,在集成电路的制造过程中,经常使用导电材料填入介电材料中的开口/沟槽。图10至图14显示一利用镶嵌工艺形成内连线结构的实施例。
参照图10,介电层60,也称为金属间介电层(IMD)60,形成在半导体基底20上方。金属间介电层60的上表面可包括或不包括一CMP停止层61。金属间介电层60中形成有开口62。金属间介电层60也包括图案密集区300与图案疏离区400,其中开口62在图案密集区300的宽度D3小于在图案疏离区400的宽度D4。此外,即使开口62在两区300、400的宽度大致相同,图案密集区300与图案疏离区400也可能会因为两区的金属线数量不同而造成。开口62可能露出导电元件64,导电元件64可电性连接至栅极条22(未显示,参照图4)及/或栅极52(未显示,参照图8)。在一实施例中,导电元件64为形成在内层介电层30/40(未显示,参照图7A、图7B)中的接触插塞。在另一实施例中,导电元件64为金属化层中的介层插塞(vias)。
请参照图11,毯覆性形成扩散阻障层66,接着在开口62中填入导电材料68。扩散阻障层66的材料例如是钛、氮化钛、钽、氮化钽等。导电材料68的材料例如是铜或铜合金。导电材料68因为底下结构不平坦而形成隆起物70。
请参照图12,进行第一CMP以移除介电层60上方多余的扩散阻障层66与导电材料68,以露出介电层60。此外,扩散阻障层66也可以在第一CMP中作为CMP停止层而在第一CMP后露出,但其下的介电层60则未露出。应注意的是,第一CMP可能会导致碟化效应,特别是在图案疏离区400。经过第一CMP后,形成了金属线72。
在图13中,形成了导电材料74,其可包括与导电材料68(参见图11)相同或不同的材料。接着,如图14所示,进行一第二CMP以移除多余的导电材料74。第二CMP停在介电层60的上表面。经过第二CMP后的结构,即使有任何碟化效应(及/或空洞),其程度已经明显小于第一CMP后的结构。因此,提供了较平坦的表面以利于后续工艺。应可了解的是,虽然图10至图14显示一单镶嵌工艺,同样的方法也适用于双镶嵌工艺。
实验证实,借由本发明实施例的方法可明显降低,甚至完全消除碟化效应与空洞。
虽然本发明已以数个优选实施例揭示如上,然而其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可作任意的更动与润饰,因此本发明的保护范围当视所附的权利要求所界定的范围为准。
Claims (4)
1.一种集成电路结构的形成方法,包括下列步骤:
提供一半导体基底;
形成多个图案化元件于该半导体基底上,其中所述多个图案化元件之间具有沟槽,且所述多个图案化元件为一金属间介电层,其中该集成电路结构包括一图案密集区与一图案疏离区,所述多个图案化元件于该图案密集区的图案密度大于该图案疏离区;
毯覆性形成一扩散阻障层于该沟槽中;
以第一导电材料填入该沟槽,其中该第一导电材料具有第一上表面,其高于所述多个图案化元件的上表面;
于第一导电材料填入该沟槽后,立即进行第一平坦化以降低该第一导电材料的第一上表面,直到露出所述多个图案化元件的上表面,其中该第一平坦化包括一过度平坦化,以露出形成在第一导电材料中的空洞,其中该扩散阻障层在第一平坦化中作为平坦化停止层;
沉积第二导电材料,填满所述第一平坦化造成的碟化区域以及填满在第一导电材料中的所述空洞,其中所述空洞的深度大于所述碟化区域的深度,其中该第二导电材料具有第二上表面,其高于所述多个图案化元件的上表面,其中该第一导电材料的第一上表面高于该第二导电材料的第二上表面,其中该第二导电材料的一部分覆盖所述金属间介电层的一部分,且该第二导电材料的该部分包括一底表面,该底表面与该金属间介电层的上表面接触;以及
进行第二平坦化以降低该第二导电材料的第二上表面,直到露出所述多个图案化元件的上表面。
2.如权利要求1项所述的方法,其中所述第一与第二导电材料为相同材料。
3.如权利要求1项所述的方法,其中所述第一与第二导电材料包含不同材料。
4.如权利要求1项所述的方法,其中所述第一与第二导电材料包含铜。
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US20090286384A1 (en) | 2009-11-19 |
US8932951B2 (en) | 2015-01-13 |
US20110227189A1 (en) | 2011-09-22 |
US8552522B2 (en) | 2013-10-08 |
CN103633011A (zh) | 2014-03-12 |
US20140030888A1 (en) | 2014-01-30 |
CN101582390B (zh) | 2016-05-04 |
US7955964B2 (en) | 2011-06-07 |
CN101582390A (zh) | 2009-11-18 |
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