CN103579340A - 场效应晶体管的栅电极 - Google Patents

场效应晶体管的栅电极 Download PDF

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CN103579340A
CN103579340A CN201210468202.XA CN201210468202A CN103579340A CN 103579340 A CN103579340 A CN 103579340A CN 201210468202 A CN201210468202 A CN 201210468202A CN 103579340 A CN103579340 A CN 103579340A
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gate electrode
effect transistor
district
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field
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CN103579340B (zh
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陈能国
万幸仁
林奕安
张骏伟
孙诗平
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及一种场效应晶体管的栅电极。场效应晶体管的示例性结构包括衬底；栅电极，位于具有第一顶面和侧壁的衬底的上方；源极/漏极(S/D)区，至少部分设置在栅电极一侧的衬底中；间隔件，位于分布在栅电极和S/D区之间的侧壁上；以及接触蚀刻停止层(CESL)，紧邻间隔件且进一步包括在S/D区上方延伸的部分，其中，该部分的第二顶面与第一顶面基本共面。

Description

场效应晶体管的栅电极
技术领域
本发明涉及集成电路制造，更具体地，涉及一种具有栅电极的场效应晶体管。
背景技术
在一些集成电路(IC)设计中，随着技术节点的缩小，一直期望用金属栅电极代替典型的多晶硅栅电极，以随着减小的特征尺寸来改善器件性能。一种形成金属栅极结构的工艺被称为“后栅极”工艺，其中，“后”制造最终的栅极结构，从而允许减少包括在电极形成之后必须实施的高温处理的后续工艺的数量。此外，随着晶体管尺寸减小，栅极氧化物的厚度也必须减小，以通过减小的栅极长度保证性能。为了降低栅极漏电，还使用高介电常数(高k)栅极介电层，从而允许较大物理厚度而保持与较大的技术节点中所使用具有较低介电常数的较薄栅极氧化物层所提供的相同有效厚度。
然而，在互补金属氧化物半导体(CMOS)制造过程中，存在实现这种部件和工艺的一些挑战。例如，在“后栅极”制造工艺中，很难实现用于场效应晶体管(FET)的较低的栅极阻抗，这是因为在用于高纵横比沟槽的间隙填充的金属层沉积以后，金属栅电极中生成一些空隙，从而增加了器件不稳定和/或器件失效的可能性。由于栅极长度和器件之间的间距减小，加剧了这些问题。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种场效应晶体管，包括：衬底；栅电极，位于所述衬底上方并具有第一顶面和侧壁；源极/漏极(S/D)区，至少部分设置在所述栅电极一侧的所述衬底中；间隔件，位于分布在所述栅电极和所述S/D区之间的所述侧壁上；以及接触蚀刻停止层(CESL)，紧邻所述间隔件且进一步包括在所述S/D区的上方延伸的一部分，其中，所述一部分的第二顶面与所述第一顶面基本共面。
在该场效应晶体管中，所述栅电极的纵横比在大约0.8至大约1.2的范围内。
在该场效应晶体管中，所述S/D区在所述衬底的表面上方延伸并且所述栅电极的第一厚度大于所述CESL的所述一部分的第二厚度。
在该场效应晶体管中，所述第一厚度与所述第二厚度的比率在大约1.1至大约1.5的范围内。
在该场效应晶体管中，所述S/D区完全位于所述衬底的表面下方并且所述栅电极的第一厚度小于所述CESL的所述一部分的第二厚度。
在该场效应晶体管中，所述第一厚度与所述第二厚度的比率在大约0.5到大约0.9的范围内。
在该场效应晶体管中，所述栅电极包括多晶硅、P功函金属或N功函金属。
在该场效应晶体管中，所述栅电极包括P功函金属，所述P功函金属包括TiN、WN、TaN或Ru。
在该场效应晶体管中，所述栅电极包括N功函金属，所述N功函金属包括Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn或Zr。
在该场效应晶体管中，所述CESL包括氮化硅、氮氧化硅、碳化硅或掺碳氮化硅。
在该场效应晶体管中，所述源极/漏极(S/D)区包括应变材料，所述应变材料的晶格常数不同于所述衬底的晶格常数。
在该场效应晶体管中，所述应变材料包括SiGe、SiGeB、SiP或SiC。
在该场效应晶体管中，所述间隔件包括氮化硅、氮氧化硅、碳化硅或掺碳氮化硅。
在该场效应晶体管中，所述场效应晶体管是鳍式场效应晶体管。
根据本发明的另一方面，提供了一种制造场效应晶体管的方法，包括：提供衬底，其中，所述衬底包括具有侧壁的伪栅电极、源极/漏极(S/D)区以及分布在所述伪栅电极和所述S/D区之间的所述侧壁上的间隔件；在所述伪栅电极、所述S/D区和所述间隔件的上方沉积接触蚀刻停止层(CESL)；在所述CESL的上方沉积层间介电(ILD)层；使用第一抛光液实施第一化学机械抛光(CMP)，以暴露所述伪栅电极上方的所述CESL；使用第二抛光液实施第二CMP，以暴露所述伪栅电极；去除所述CESL和所述间隔件的上部；以及使用所述第一抛光液实施第三CMP，以暴露所述S/D区上方的所述CESL。
在该方法中，所述第一抛光液包括CeO2。
在该方法中，所述第二抛光液包括SiO2。
在该方法中，采用湿蚀刻实施去除所述CESL和所述间隔件的上部的步骤。
在该方法中，采用干蚀刻实施去除所述CESL和所述间隔件的上部的步骤。
在该方法中，在大约10mTorr至大约100mTorr之间的压力条件下实施所述干蚀刻。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1示出了根据本发明的各个方面的制造包括栅电极的场效应晶体管的方法的流程图；以及
图2至图12示出了根据本发明的各个方面的处于各个制造阶段的场效应晶体管的栅电极的截面图。
具体实施方式
应该理解，以下本发明提供了用于实现本发明的不同特征的多种不同实施例或实例。以下将描述部件和布置的特定实例用以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括以直接接触的方式形成第一部件和第二部件的实施例，也可以包括其他部件形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。为了简化和清楚，可以按照不同比例任意绘制各种部件。此外，本发明提供了基于“后栅极”金属栅极结构的实例，然而，本领域的技术人员可以认识到其他结构的应用和/或其他材料的使用。
参考图1，其示出了根据本发明的各方面的制造包括栅电极的场效应晶体管的方法100的流程图。方法100从步骤102开始，其中，提供衬底，衬底包括具有侧壁的伪栅电极、源极/漏极(S/D)区和分布在伪栅电极和S/D区之间的侧壁上的间隔件。方法100继续步骤104，其中，在伪栅电极、S/D区和间隔件的上方沉积接触蚀刻停止层(CESL)。方法100继续步骤106，其中，在CESL的上方沉积层间介电层(ILD)层。方法100继续步骤108，其中，实施使用第一抛光液(slurry)的第一化学机械抛光(CMP)，以暴露位于伪栅电极上方的CESL。方法100继续步骤110，其中，实施使用第二抛光液的第二CMP，以暴露伪栅电极。方法100继续步骤112，其中，去除CESL和间隔件的上部。方法100继续步骤114，其中，实施使用第一抛光液的第三CMP，以暴露S/D区上方的CESL。下列论述示出了可以根据图1的方法100制造的场效应晶体管(FET)的实施例。
图2至图12示出了根据本发明的各个方面的处于各个制造阶段的场效应晶体管(FET)200的栅电极224的示意性截面图。在一些实施例中，FET200是平面场效应晶体管。在一些实施例中，FET200是鳍式场效应晶体管。可以在微处理器、存储单元和/或其他集成电路(IC)中包括FET200。在一些实施例中，图1所示的操作的性能无法制造完整的FET200。使用互补金属氧化物半导体(CMOS)技术工艺可以制造完整的FET200。因此，在图1的方法100之前、其中和/或之后可以提供额外的工艺，并且本文仅简单描述了这些其他工艺。另外，为了更好地理解本发明的概念，简化了图2至图12。例如，虽然这些附图示出了FET200，但是IC可以包括具有电阻器、电容器、电感器和熔丝等的大量其他器件。
参考图2和步骤102，提供衬底202。在至少一个实施例中，衬底202包括晶体硅衬底(例如，晶圆)。在一些可选实施例中，衬底202由其他适合的元素半导体(诸如金刚石或锗)、适合的化合物半导体(诸如砷化镓、碳化硅、砷化铟或磷化铟)或适合的合金半导体(碳化硅锗、磷化镓砷或磷化铟镓)制成。此外，衬底202可以包括外延层(epi层)，也可能发生应变以提高性能，和/或可以包括绝缘体上硅(SOI)结构。
衬底202可以进一步包括有源区204(为了简单，仅示出了一个有源区)和隔离区206。根据设计要求，有源区204可以包括各种掺杂结构。在一些实施例中，有源区204掺杂有p型或n型掺杂物。例如，有源区204可以掺杂有p型掺杂物(诸如，硼或BF2、n型掺杂物(诸如磷或砷)和/或它们的组合。有源区204可以用作配置为n型金属氧化物半导体FET(被称为nMOSFET)的区域或可选地用作配置为p型MOSFET(称为pMOSFET)的区域。
隔离区206可以形成在衬底202上，以隔离各种有源区204。隔离区206可以使用诸如局部硅氧化(LOCOS)或浅沟槽隔离(STI)的隔离技术，以限定并电隔离各种有源区204。在所述的实施例中，隔离区206包括STI。隔离区206可以包括氧化硅、氮化硅、氮氧化硅、掺氟硅酸盐玻璃(FSG)、低K介电材料、其他适合的材料和/或它们的组合。通过任何适合的工艺可以形成隔离区206和在所述的实施例中的STI。例如，STI的形成可以包括：通过常规的光刻工艺图案化半导体衬底202，然后在衬底202中蚀刻沟槽(例如，通过采用干蚀刻、湿蚀刻和/或等离子蚀刻工艺)，以及用介电材料填充沟槽内(例如，通过采用化学汽相沉积工艺)。在一些实施例中，被填充的沟槽可能具有多层结构，诸如填充有氮化硅或氧化硅的热氧化衬里层。
然后，在衬底202的上方形成栅极介电层212。在一些实施例中，栅极介电层212可以包括氧化硅、高K介电材料或它们的组合。高k介电材料被定义为具有大于二氧化硅(SiO2)的介电常数的介电材料。高k介电层包括金属氧化物。金属氧化物选自由Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb和Lu的氧化物以及它们的混合物所组成的组。通过热氧化工艺、化学汽相沉积(CVD)工艺和原子层沉积(ALD)工艺可以生长栅极介电层212，并且该栅极介电层212的厚度小于2纳米(nm)。
栅极介电层212可以进一步包括界面层(未示出)，以最小化栅极介电层212和衬底202之间的压力。界面层可以由通过热氧化工艺生长的氧化硅或氮氧化硅形成。例如，可以通过快速热氧化(RTO)法或在含氧的退火工艺中生长界面层。
然后，伪栅电极214可以形成在栅极介电层212的上方。在一些实施例中，伪栅电极214可以包括单层或多层结构。在所述的实施例中，伪栅电极214可以包括多晶硅。此外，伪栅电极214可以是均匀或梯度掺杂的掺杂多晶硅。伪栅电极214的厚度可以是任意适合的厚度。在所述的实施例中，伪栅电极214的厚度在大约30nm至大约60nm的范围内。可以采用低压化学汽相沉积(LPCVD)工艺形成伪栅电极214。
然后，图案化伪栅电极214和栅极介电层212，以制造图2所示的结构。采用诸如旋涂的适合的方法在伪栅电极214的上方形成光刻胶层(未示出)，然后采用合适的光刻图案化法来图案化光刻胶层，以在伪栅电极214的上方形成图案化的光刻胶部件。图案化的光刻胶部件的宽度在大约10nm至45nm的范围内。然后采用干蚀刻工艺，将图案化的光刻胶部件转印至下面的层(即，伪栅电极214和栅极介电层212)，以形成多个伪栅叠层210。伪栅电极214包括顶面214t和侧壁214w。然后，可以去除光刻胶层。
然后在栅叠层210周围沉积共形间隔件材料。在本实施例中，间隔件材料可以包括氮化硅、氮氧化硅、碳化硅或掺碳氮化硅或其他适合的材料。间隔件材料可以包括单层或多层结构。可以通过CVD、ALD、物理汽相沉积法(PVD)或其他适合的技术形成间隔件材料的均匀层(blanket layer)。均匀层的厚度在大约5nm至大约15nm的范围内。然后，对间隔件材料实施各向异性蚀刻，以在伪栅电极214的侧壁214w上形成一对间隔件216。
然后，使用栅叠层210和一对间隔件216作为硬掩模，实施偏置蚀刻工艺，以使未受保护或暴露的衬底202凹进，从而在有源区204(如图3所示)中形成源极/漏极(S/D)腔205。在一个实施例中，可以使用选自NF3、CF4和SF6中的化学物质作为蚀刻气体实施蚀刻工艺。在可选实施例中，采用含NH4OH和H2O2的溶液可以实施蚀刻工艺。
参考图4和图1中的步骤102，在有源区204中形成S/D腔205之后，通过在S/D腔205中外延生长应变材料207以形成S/D区208来生成图4中的结构，其中，应变材料207的晶格常数不同于衬底202的晶格常数。换言之，每个S/D区208至少部分设置在伪栅电极214一侧的衬底202中。在一些实施例中，S/D区208在衬底表面202的上方延伸。在一些实施例中，S/D区208完全位于衬底表面202s的下方(未示出)。
在一些实施例中，应变材料207包括用于nMOSFET的SiC或SiP。采用低压CVD(LPCVD)工艺选择性地生长应变材料207(诸如碳化硅(SiC))，以形成S/D区208。在所述的实施例中，在在大约400℃至800℃之间的温度和在大约1Torr至15Torr之间的压力条件下，使用SiH4、CH4和H2作为反应气体来实施LPCVD工艺。
在一些实施例中，应变材料207包括用于pMOSFET的SiGe或SiGeB。通过LPCVD工艺选择性地生长应变材料207(如硅锗(SiGe))，以形成S/D区208。在一个实施例中，在大约660℃至700℃之间的温度和在大约13Torr至50Torr之间的压力条件下，使用SiH2Cl2、HCl、GeH4、B2H6和H2作为反应气体来实施LPCVD工艺。
在一些实施例中，通过自对准的硅化物(自对准硅化物)工艺可以在S/D区208上任选地形成硅化物区(未示出)。例如，自对准硅化物工艺可以包括1个步骤。首先，在大约500℃到大约900℃之间的温度条件下，可以通过溅射在S/D区208上沉积金属材料，使得下面硅和金属材料发生反应，从而形成硅化物区。然后，可以蚀刻掉未发生反应的金属材料。硅化物区可以包括选自硅化钛、硅化钴、硅化镍、硅化铂、硅化铒和硅化钯的材料。
参考图5和图1中的步骤104，在有源区204中形成S/D区208之后，通过在伪栅电极214、S/D区208和间隔件216的上方沉积接触蚀刻停止层(CESL)218并沿着STI区206延伸来制造图5中的结构。CESL218可以包括但不仅限于：氮化硅、氮氧化硅、碳化硅或掺碳氮化硅。CESL218的厚度在大约15nm至大约20nm的范围内。
在一些实施例中，可以采用CVD、高密度等离子体(HDP)CVD、次大气压CVD(SACVD)、分子层沉积(MLD)、溅射或其他适合的方法来沉积CESL218。例如，在低于10mTorr的压力和在大约350℃至500℃之间的温度范围内的条件下，实施所述的实施例的MLD工艺。在至少一个实施例中，通过硅源化合物和氮源发生反应在栅电极214、S/D区208和间隔件216的上方沉积氮化硅。硅源化合物向沉积的氮化硅提供硅，且可以是硅烷(SiH4)或正硅酸乙酯(TEOS)。氮源向沉积的氮化硅提供氮，且可以是氨(NH3)或氮气(N2)。在其他实施例中，通过碳源化合物、硅源化合物和氮源发生反应，在栅电极214、S/D区208和间隔件216的上方沉积掺碳氮化硅。碳源化合物可以是有机化合物，诸如碳氢化合物(诸如乙烯(C2H6))，并且硅源化合物和氮源可能与氮化硅CESL相同。
参考图6和图1中的步骤106，沉积CESL218之后，通过在CESL218的上方沉积层间介电(ILD)层222来制造图6中的结构。ILD层222可以包括介电材料。介电材料可以包括氧化硅、氮化硅、氮氧化硅、磷硅玻璃(PSG)、掺硼磷硅玻璃(BPSG)、旋涂玻璃(SOG)、掺氟硅玻璃(FSG)、掺碳氧化硅(诸如，SiCOH)、
Figure BDA00002429658800081
(由Santa Clara，California制造的应用材料)、干凝胶、气凝胶、非晶掺氟碳、聚对二甲苯、BCB(苯并环丁烯)、Flare、
Figure BDA00002429658800082
(Dow Chemical，Midland，Michigan)、聚酰亚胺和/或它们的组合。ILD层222可以包括一种或多种介电材料和/或一个或多个介电层。在一些实施例中，通过CVD、高密度等离子体(HDP)CVD、次大气压CVD(SACVD)、旋涂、溅射或其他合适的方法可以在CESL218的上方沉积适当厚度的ILD层222。在所述的实施例中，ILD层222的厚度在大约3000埃
Figure BDA00002429658800083
至大约4500埃
Figure BDA00002429658800084
的范围内。
在后栅极工艺中，可以去除伪栅电极214，使得形成金属栅电极224(如图12所示)以代替伪栅电极214。因此，采用CMP工艺(图1中的步骤108和110)平坦化ILD层222和CESL218，直到暴露或到达伪栅电极层214的顶面214t。
参考图7和图1中的步骤108，在CESL218的上方沉积ILD层222之后，通过使用第一抛光液232实施第一化学机械抛光(CMP)230以暴露伪栅电极214上方的CESL218来生成图7中的结构。在所述的实施例中，在大约50rpm至大约150rpm之间的头部旋转速度和大约50rpm至大约150rpm之间的压盘旋转速度并且在在大约1psi至大约4psi之间的向下压力和在每分钟大约100mL至每分钟大约300mL之间的抛光液流速的条件下，实施第一CMP230。在一些实施例中，第一抛光液232包括CeO2。
参考图8和图1中的步骤110，在进行第一CMP230以暴露CESL218之后，通过使用第二抛光液236实施第二CMP234以暴露伪栅电极214来制造图8中的结构。在所述的实施例中，在大约50rpm至大约150rpm之间的头部旋转速度和在大约50rpm至大约150rpm之间的压盘旋转速度，并且在大约1psi至大约4psi之间的向下压力和在每分钟大约100mL至每分钟大约300mL之间的抛光液流速的条件下，实施第二CMP234。在一些实施例中，第二抛光液236包括二氧化硅(SiO2)。因此，第二CMP234具有高选择性，以提供用于伪栅电极214、间隔件216、CESL218和ILD层222的基本平坦的表面。
在一些实施例中，在CMP工艺之后，实施栅极置换工艺。可以从由介电层围绕的栅叠层210去除伪栅电极214，该介电层包括间隔件216、CESL218和ILD层222，从而通过采用湿蚀刻和/或干蚀刻工艺在介电层中形成高纵横比(例如，大于3)的沟槽。
然后，将金属层填充在高纵横比的沟槽中。金属层可以包括任何适于形成金属栅电极或其部分的金属材料，即，包括势垒层、功函层、衬里层、界面层、晶种层、粘合层、阻挡层等。采用PVD工艺形成金属层。
PVD工艺的副作用是特别容易在高纵横比的沟槽的开口处形成金属突出物(overhang)，从而金属突出物易于堵住高纵横比的沟槽的开口。尽管金属突出物实际上没有夹断(pinch off)和封闭高纵横比的沟槽，但至少能减小了高纵横比的沟槽的开口直径，因此阻止其他金属材料进入高纵横比的沟槽内并且在高纵横比的沟槽中生成空隙，从而增加器件不稳性和/或器件失效的可能性。
因此，下文中关于图9至图12所讨论的工艺可以去除伪栅电极214的至少一部分，以生成低纵横比的沟槽，从而与在高纵横比的沟槽相比更容易在低纵横比的沟槽中进行进一步沉积。这可以减少在低纵横比的沟槽中金属栅电极内的空隙生成而且提高了器件性能。
如图9和图1中的步骤112，为了制造FET200的低纵横比的金属栅电极(诸如，图12所示的金属栅电极224)，通过去除CESL218和间隔件216的上部来制造图9中的结构。使用栅叠层210和ILD层222作为硬掩模，实施湿蚀刻工艺和/或干蚀刻工艺以使未受保护或暴露的CESL218和间隔件216的上部凹进，从而形成低于顶面214t的空腔228。在一些实施例中，用于氮化硅CESL218和氮化硅间隔件216的湿蚀刻工艺包括暴露于含热磷酸(H3PO4)的溶液中。在一些实施例中，在大约10℃至大约70℃之间的温度、在大约300W至大约1000W之间的电源功率、在大约50W至大约300W之间的偏置功率、以及在大约10mTorr至大约100mTorr之间的压力条件下，使用包括CH3F的反应气体实施干蚀刻工艺。
参考图10和图1中的步骤114，在去除CESL218和间隔件216的上部之后，通过使用第一抛光液232实施第三CMP238以暴露S/D区208上方的CESL218来制造图10中的结构，其中，CESL218紧邻间隔件216且进一步包括在S/D区208上方延伸的部分218a，其中，部分218a的第二顶面218t与剩余的伪栅电极215的第一顶面215t基本共面。剩余的伪栅电极215具有低纵横比(在大约0.8至大约1.2之间)。在所述的实施例中，在大约50rpm至大约150rpm之间的头部旋转速度和在大约50rpm至大约150rpm之间的压盘旋转速度并且在大约1psi到大约4psi之间的向下压力和在每分钟大约100mL到每分钟大约300mL之间的抛光液流速的条件下实施第三CMP238。在一些实施例中，第一抛光液232包括CeO2。
图11示出了从伪栅叠层210去除低纵横比的剩余的伪栅电极215以在一对侧壁间隔件216中形成低纵横比的沟槽之后的图10的FET200。采用湿蚀刻和/或干蚀刻工艺可以去除剩余的伪栅电极215。在至少一个实施例中，用于伪多晶硅栅电极215的湿蚀刻工艺包括暴露在含氢氧化铵、稀释的氟化氢、去离子水的氢氧化物溶液中和/或其他适合的蚀刻剂溶液中。在其他实施例中，在大约650W至大约800W之间的源功率、在大约100W至大约120W之间的偏置功率以及在大约60mTorr至大约200mTorr之间的压力的条件下，使用Cl2、HBr和He作为蚀刻气体对剩余的伪栅电极层215实施干蚀刻工艺。
低纵横比的沟槽226使金属材料更容易沉积在低纵横比的沟槽226中。因此，制造FET200的低纵横比金属栅电极224的所述方法(图12所示)减少了在低纵横比的沟槽226中的金属栅电极224内的空隙生成并且提高了器件性能。
参考图12，在低纵横比的沟槽226形成之后，金属层填充在低纵横比的沟槽226中。例如，金属层包括P功函金属或N功函金属。在一些实施例中，P功函金属包括TiN、WN、TaN和Ru。在一些实施例中，N功函金属包括Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn或Zr。对金属层实施另一CMP工艺以形成FET200的金属栅电极224，其中，CESL218紧邻间隔件216并且进一步包括在S/D区208的上方延伸的部分218a，其中，部分218a的第二顶面218t与金属栅电极224的顶面224t基本共面。在一些实施例中，金属栅电极224的纵横比在大约0.8至大约1.2的范围内。在所述的实施例中，金属栅电极224和栅电介层212相结合并且被称为栅叠层220。
如果S/D区208在衬底表面202s的上方延伸，则栅电极224的第一厚度t1大于CESL218在S/D区208上方延伸的部分218a的第二厚度t2。在一些实施例中，第一厚度t1与第二厚度t2的比率在大约1.1至大约1.5的范围内。如果S/D区208位于衬底表面202s的下方(未示出)，则栅电极224的第一厚度t1小于CESL218在S/D区208上方延伸的部分218a的第二厚度t2。在一些实施例中，第一厚度t1与第二厚度t2的比率在大约0.5至大约0.9的范围内。
在实施图1至图12所示的步骤之后，在一些实施例中，实施包括互连工艺的后续工艺，以完成FET200的制造。
根据一个实施例，场效应晶体管包括：衬底；栅电极，位于包括第一顶面和侧壁的衬底的上方；源极/漏极(S/D)区，至少部分设置在栅电极一侧的衬底中；间隔件，位于分布在栅电极和S/D区之间的侧壁上；以及接触蚀刻停止层(CESL)，紧邻间隔件且进一步包括在S/D区上方延伸的一部分，其中，该一部分的第二顶面与第一顶面基本共面。
根据另一个实施例，制造场效应晶体管的方法包括：提供衬底，衬底包括具有侧壁的伪栅电极、源极/漏极(S/D)区和分布在伪栅电极和S/D区之间的侧壁上的间隔件；在伪栅电极、S/D区和间隔件的上方沉积接触蚀刻停止层(CESL)；在CESL的上方沉积层间介电(ILD)层；使用第一抛光液实施第一化学机械抛光(CMP)，以暴露伪栅电极上方的CESL；使用第二抛光液实施第二CMP，以暴露伪栅电极；去除CESL和间隔件的上部；以及使用第一抛光液实施第三CMP，以暴露S/D区上方的CESL。
虽然已经通过实例并且根据各个实施例描述本发明，但是可以理解，本发明不仅限于所公开的实施例。相反地，本发明可以涵盖各种更改和类似布置(对本领域技术人员而言是显而易见的)。因此，所附权利要求的范围应该与最宽泛的解释一致，从而包括所有这些更改和类似布置。

Claims (10)

1.一种场效应晶体管，包括：
衬底；
栅电极，位于所述衬底上方并具有第一顶面和侧壁；
源极/漏极(S/D)区，至少部分设置在所述栅电极一侧的所述衬底中；
间隔件，位于分布在所述栅电极和所述S/D区之间的所述侧壁上；以及
接触蚀刻停止层(CESL)，紧邻所述间隔件且进一步包括在所述S/D区的上方延伸的一部分，其中，所述一部分的第二顶面与所述第一顶面基本共面。
2.根据权利要求1所述的场效应晶体管，其中，所述栅电极的纵横比在大约0.8至大约1.2的范围内。
3.根据权利要求1所述的场效应晶体管，其中，所述S/D区在所述衬底的表面上方延伸并且所述栅电极的第一厚度大于所述CESL的所述一部分的第二厚度。
4.根据权利要求3所述的场效应晶体管，其中，所述第一厚度与所述第二厚度的比率在大约1.1至大约1.5的范围内。
5.根据权利要求1所述的场效应晶体管，其中，所述S/D区完全位于所述衬底的表面下方并且所述栅电极的第一厚度小于所述CESL的所述一部分的第二厚度。
6.根据权利要求5所述的场效应晶体管，其中，所述第一厚度与所述第二厚度的比率在大约0.5到大约0.9的范围内。
7.根据权利要求1所述的场效应晶体管，其中，所述栅电极包括多晶硅、P功函金属或N功函金属。
8.根据权利要求1所述的场效应晶体管，其中，所述栅电极包括P功函金属，所述P功函金属包括TiN、WN、TaN或Ru。
9.根据权利要求1所述的场效应晶体管，其中，所述栅电极包括N功函金属，所述N功函金属包括Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn或Zr。
10.一种制造场效应晶体管的方法，包括：
提供衬底，其中，所述衬底包括具有侧壁的伪栅电极、源极/漏极(S/D)区以及分布在所述伪栅电极和所述S/D区之间的所述侧壁上的间隔件；
在所述伪栅电极、所述S/D区和所述间隔件的上方沉积接触蚀刻停止层(CESL)；
在所述CESL的上方沉积层间介电(ILD)层；
使用第一抛光液实施第一化学机械抛光(CMP)，以暴露所述伪栅电极上方的所述CESL；
使用第二抛光液实施第二CMP，以暴露所述伪栅电极；
去除所述CESL和所述间隔件的上部；以及
使用所述第一抛光液实施第三CMP，以暴露所述S/D区上方的所述CESL。
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US20180069094A1 (en) 2018-03-08
US9812551B2 (en) 2017-11-07
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US10516031B2 (en) 2019-12-24
US10797156B2 (en) 2020-10-06
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US20140042491A1 (en) 2014-02-13
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