CN105789300B - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

Info

Publication number
CN105789300B
CN105789300B CN201410812448.3A CN201410812448A CN105789300B CN 105789300 B CN105789300 B CN 105789300B CN 201410812448 A CN201410812448 A CN 201410812448A CN 105789300 B CN105789300 B CN 105789300B
Authority
CN
China
Prior art keywords
layer
metal
substrate
dielectric layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410812448.3A
Other languages
English (en)
Other versions
CN105789300A (zh
Inventor
张哲诚
程潼文
陈建颖
林木沧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN105789300A publication Critical patent/CN105789300A/zh
Application granted granted Critical
Publication of CN105789300B publication Critical patent/CN105789300B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66515—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned selective metal deposition simultaneously on the gate and on source or drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Inorganic Chemistry (AREA)

Abstract

本发明提供了半导体结构和制造半导体结构的方法。半导体结构包括：衬底；位于衬底上的金属栅极结构；以及接近金属栅极结构的间隔件，间隔件具有延伸至金属栅极结构内并且与衬底接触的边缘部分。金属栅极结构包括高k介电层和位于高k介电层上的金属栅电极。

Description

半导体结构及其制造方法
技术领域
本发明涉及集成电路器件，更具体地，涉及半导体结构及其制造方法。
背景技术
对增大在半导体器件中形成的集成电路的密度的需求已经大大驱动了集成电路(IC)的制造。这通常通过执行更激进的设计规则以允许形成更大密度的IC器件来实现。尽管如此，由于减小的部件尺寸，诸如晶体管的IC器件的增大的密度也已经增加了加工半导体器件的复杂度。
集成电路中的晶体管通常形成为具有硅栅极氧化物和多晶硅栅电极。由于部件尺寸不断减小，期望以高k栅极电介质和金属栅电极替代硅栅极氧化物和多晶硅栅电极以改进器件性能。具有金属栅电极(尤其是与高介电常数(高k)电介质联用)的晶体管可以解决诸如多晶硅损耗和与硅栅极氧化物相关联的栅极泄漏的问题。此外，金属栅极晶体管比掺杂的多晶硅展示出更低的电阻率。在金属栅极晶体管的制造工艺中，不断地需要进一步改进以满足按比例缩小工艺中的性能需求。
发明内容
为了解决现有技术中存在的问题，本发明提供了一种半导体结构，包括：衬底；金属栅极结构，位于所述衬底上；以及间隔件，接近所述金属栅极结构，所述间隔件具有延伸至所述金属栅极结构内并且与所述衬底接触的边缘部分。
在上述半导体结构中，其中，所述半导体结构还包括：外延件，接近所述间隔件。
在上述半导体结构中，其中，所述金属栅极结构包括：高k介电层，位于所述衬底上；金属层，位于所述高k介电层上；以及金属电极，位于所述金属层上。
在上述半导体结构中，其中，所述边缘部分的形状为三角形。
在上述半导体结构中，其中，所述边缘部分的形状为三角形，其中，所述边缘部分的底角介于约1°至约89°的范围内。
根据本发明的另一方面，提供了一种制造半导体结构的方法，包括：在衬底上形成栅极介电层和伪栅极堆叠件；蚀刻所述伪栅极堆叠件以形成伪栅极结构；蚀刻所述栅极介电层以形成位于所述伪栅极结构下方的凹槽；形成围绕所述伪栅极结构并且填充所述凹槽的保护层；形成接近所述保护层的外延件；由所述保护层形成具有边缘部分的两个间隔件；去除位于所述栅极介电层上的所述伪栅极结构；去除所述栅极介电层；以及在所述间隔件之间形成金属栅极结构。
在上述方法中，其中，在所述衬底上形成所述栅极介电层和所述伪栅极堆叠件包括：在衬底上形成栅极介电层；在所述栅极介电层上沉积伪栅极层；在所述伪栅极层上沉积第一硬掩模层；以及在所述第一硬掩模层上沉积第二硬掩模层。
在上述方法中，其中，在所述衬底上形成所述栅极介电层和所述伪栅极堆叠件包括：在衬底上形成栅极介电层；在所述栅极介电层上沉积伪栅极层；在所述伪栅极层上沉积第一硬掩模层；以及在所述第一硬掩模层上沉积第二硬掩模层，其中，在所述衬底上形成所述栅极介电层的方法是热氧化。
在上述方法中，其中，形成接近所述保护层的所述外延件包括：蚀刻接近所述保护层的所述衬底以形成空腔；以及在所述空腔中生长外延件。
在上述方法中，其中，在形成接近所述保护层的所述外延件之后，还包括：在所述衬底上方沉积ILD层。
在上述方法中，其中，去除位于所述栅极介电层上的所述伪栅极结构包括：暴露所述伪栅极层；以及蚀刻掉所述伪栅极层。
在上述方法中，其中，在形成接近所述保护层的所述外延件之后，还包括：在所述衬底上方沉积ILD层，其中，在所述间隔件之间形成所述金属栅极结构包括：在所述衬底上沉积高k介电层；在所述高k介电层上沉积金属层；以及在所述金属层上沉积金属电极。
在上述方法中，其中，在形成接近所述保护层的所述外延件之后，还包括：在所述衬底上方沉积ILD层，其中，在所述间隔件之间形成所述金属栅极结构包括：在所述衬底上沉积高k介电层；在所述高k介电层上沉积金属层；以及在所述金属层上沉积金属电极，其中，在所述金属层上沉积所述金属电极之后，还包括：实施化学机械抛光(CMP)以去除位于所述ILD层上的所述高k介电层、所述金属层和所述金属电极的部分。
在上述方法中，其中，蚀刻所述栅极介电层以形成位于所述伪栅极堆叠件下方的凹槽的方法是干蚀刻。
在上述方法中，其中，蚀刻所述栅极介电层以形成位于所述伪栅极堆叠件下方的凹槽的方法是干蚀刻，其中，所述干蚀刻中的气体选自由HBr、CF4、CHF3、CH4、CH2F2、N2H2、BCl3、Cl2、N2、H2、O2、He、Ar和它们的组合组成的组。
在上述方法中，其中，蚀刻所述栅极介电层以形成位于所述伪栅极结构下方的所述凹槽，凹槽角α介于约10°至约80°的范围内。
根据本发明的又一方面，提供了一种半导体结构，包括：鳍，从衬底延伸；金属栅极结构，位于所述衬底上的所述鳍的部分上方；两个间隔件，邻近所述金属栅极结构，所述间隔件具有延伸至所述金属栅极结构内的边缘部分；以及两个外延件，接近所述间隔件。
在上述半导体结构中，其中，所述金属栅极结构包括：高k介电层，位于所述衬底上；金属层，位于所述高k介电层上；以及金属电极，位于所述金属层上。
在上述半导体结构中，其中，所述边缘部分的形状为三角形，并且所述边缘部分与所述鳍接触。
在上述半导体结构中，其中，所述边缘部分的形状为三角形，并且所述边缘部分与所述鳍接触，其中，所述边缘部分的底角介于约1°至约89°的范围内。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的半导体结构的截面图。
图2A至图2I是根据一些实施例的制造半导体结构的方法的各个截面图。
图3是根据一些实施例的制造半导体结构的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，本文可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且本文使用的空间相对描述符可以同样地作出相应的解释。
在一些实施例中，栅极结构包括位于衬底上方的栅极氧化物层、以及形成在栅极氧化物层上方的栅电极和邻近栅电极的两个间隔件。在金属栅极晶体管制造工艺中，使用“后栅极”或“替代栅极”方法。在这样的工艺中，最初形成伪(例如，牺牲)栅电极，该栅电极可以包括多晶硅，实施与半导体器件相关联的各个工艺，并且随后去除伪栅电极且以金属栅电极代替伪栅电极。当去除伪栅电极时，也去除位于伪栅电极下方的栅极氧化物层，并且以高k介电层代替栅极氧化物层，但是也可以去除位于间隔件下方的栅极氧化物层，并且可以形成位于间隔件下方的隧道。因此，当形成金属栅电极时，形成金属泄漏问题。沉积在间隔件之间的金属泄漏至源极/漏极区，源极/漏极区可以包括穿过间隔件下方的隧道的外延件。并且形成的金属栅电极可以具有位于金属栅电极中的空隙，从而影响晶体管性能。
参照图1，图1是根据一些实施例的半导体结构的截面图。半导体结构100包括衬底110。金属栅极结构120位于衬底110上。间隔件130接近金属栅极结构120，间隔件130具有延伸到金属栅极结构120内的边缘部分(skirting part)132。外延件140接近间隔件130。半导体结构100可以是在集成电路的加工期间制造的中间结构或中间结构的部分，中间结构或其部分可以包括静态随机存取存储器(SRAM)和/或其他逻辑电路、诸如电阻器、电容器和电感器的无源组件、以及诸如P沟道场效应晶体管(PFET)、N沟道FET(NFET)、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管、其他存储单元和它们的组合的有源组件。在一些实施例中，衬底110可以是硅衬底。取决于如本领域已知的设计需求(例如，p型衬底或n型衬底)，衬底110可以包括各种掺杂结构。衬底110可以包括诸如源极/漏极区、n阱、p阱的各种掺杂区，并且可以包括浅沟槽隔离(STI)区。衬底110可以包括诸如碳化硅、砷化镓、砷化铟或磷化铟的化合物半导体。金属栅极结构120包括位于衬底110上的高k介电层122和位于高k介电层122上的金属栅电极124。金属栅电极124可以包括钨(W)、铝(Al)、钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)、钴(Co)、铜(Cu)、镍(Ni)、它们的组合和/或其他合适的材料。高k介电层122可以包括氧化铪(HfO2)。高k电介质的其他实例包括氧化铪硅(HfSiO)、氮氧化铪硅(HfSiON)、氧化铪钽(HMO)、氧化铪钛(HMO)、氧化铪锆(HfZrO)、它们的组合和/或其他合适的材料。在本发明的各个实施例中，金属层126可以形成在高k介电层122和金属栅电极124之间。金属层126可以是适合于形成金属栅极或其部分的任何金属材料，金属栅极或其部分包括功函层、衬垫层、界面层、晶种层、粘合层、阻挡层等。形成在高k介电层上的金属层126可以包括包含Ti、TiN、TaN、Ta、TaC、TaSiN、W、WN、MoN、MoON和其他合适的材料的一个或多个金属层。可以沉积的金属材料的实例包括P型金属材料和N型金属材料。P型金属材料可以包括诸如钌、钯、铂、钴、镍和导电金属氧化物和/或其他合适的材料的组分。N型金属材料可以包括诸如铪、锆、钛、钽、铝、金属碳化物(例如，碳化铪、碳化锆、碳化钛、碳化铝)、铝化合物和/或其他合适的材料的组分。间隔件130接近金属栅极结构120，并且每个间隔件130均具有延伸到金属栅极结构120内的边缘部分132。边缘部分132与衬底110接触。在一些实施例中，边缘部分132的形状是三角形。边缘部分132具有底角θ，其中，底角θ在约1°至约89°的范围内。在一些实施例中，底角θ在约20°至约70°的范围内。例如，底角θ为60°。在一些实施例中，边缘部分132延伸到高k介电层122内。并且边缘部分132与衬底110接触。在一些实施例中，间隔件130可以包括氧化硅、氮化硅、氮氧化硅、碳化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料、它们的组合和/或其他合适的材料。外延件140接近间隔件130。外延件140可以包括硅或硅锗(SiGe)。在一些实施例中，外延件可以掺杂有硼和/或BF2、或者磷和/或砷。具有边缘部分132的间隔件130可以保护金属栅极结构120。间隔件130与衬底110直接接触，这意味着在间隔件130和衬底110之间没有栅极介电层，因此可以防止金属泄漏问题。边缘部分132在金属栅极结构120和外延件140之间延长一段距离，这可以防止蚀刻剂蚀刻穿间隔件，使半导体结构具有更好的可靠性。
在一些实施例中，半导体结构可以是鳍式场效应晶体管(FinFET)的部分。FinFET具有从衬底延伸的薄鳍。在该垂直鳍中形成FinFET的沟道。并且栅极形成在(例如，包裹)鳍上方。在一些实施例中，图1是沿着FinFET的鳍截取的截面图。衬底110可以是鳍，并且金属栅极结构120形成在鳍的部分上方。两个间隔件130邻近金属栅极结构120并且具有延伸到金属栅极结构120内的边缘部分132。并且形成在鳍110中的两个外延件140接近间隔件130。金属栅极结构120可以包括高k介电层122和金属电极124。在一些实施例中，金属层形成在高k介电层122和金属电极124之间。边缘部分132与衬底110接触。在一些实施例中，边缘部分132的形状是三角形。边缘部分132具有底角θ，其中，底角θ在约10°至约80°的范围内。例如，底角θ为60°。在一些实施例中，边缘部分132延伸到高k介电层122内。间隔件130的边缘部分132可以减少金属泄漏问题，金属泄漏问题是金属栅极结构120中的金属泄漏穿过间隔件130或泄漏至间隔件130下方并到达外延件140。
参照图2A至图2I，图2A至图2I是根据一些实施例的制造半导体结构的方法的各个截面图。参照图2A，在衬底200上形成栅极介电层210，并且在栅极介电层210上形成伪栅极堆叠件220。取决于如本领域已知的设计需求(例如，p型衬底或n型衬底)，衬底200可以包括各种掺杂结构。衬底200可以包括诸如源极/漏极区、n阱、p阱的各种掺杂区，并且可以包括浅沟槽隔离(STI)区。衬底200可以包括诸如碳化硅、砷化镓、砷化铟或磷化铟的化合物半导体。栅极介电层210可以是氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、氧化铪(HfO)、氮化钛(TiN)或它们的组合。可以通过诸如化学汽相沉积(CVD)、原子层沉积(ALD)和/或其他合适的工艺的热氧化或沉积来形成栅极介电层210。伪栅极堆叠件220可以包括位于栅极介电层210上的伪栅极层230、位于伪栅极层230上的第一硬掩模层240以及位于第一硬掩模层240上的第二硬掩模层250。伪栅极层230可以包括多晶硅、硅、氮化硅或其他合适的材料。可以通过CVD、PVD或任何合适的方法形成伪栅极层230。第一硬掩模层240可以包括氧化硅、氮化硅、氮氧化硅、碳化硅和/或其他合适的材料。可以使用诸如CVD、PVD或ALD的方法形成第一硬掩模层240。第二硬掩模层250可以包括氧化硅、氮化硅、氮氧化硅、碳化硅和其他合适的材料。可以使用诸如化学汽相沉积(CVD)、PVD或ALD的方法形成第二硬掩模层250。
参照图2B，形成伪栅极结构320。蚀刻图2A中的伪栅极堆叠件220以形成伪栅极结构320。蚀刻工艺可以包括光刻和显影工艺。蚀刻方法可以是干蚀刻或湿蚀刻。在一些实施例中，蚀刻方法是干蚀刻，并且干蚀刻中的气体选自由HBr、CF4、CHF3、CH4、CH2F2、N2H2、BCl3、SF6、Cl2、N2、H2、O2、He、Ar和它们的组合组成的组。可以在从约1毫托至约80毫托的压力范围内、在从约100W至约1000W的功率范围内和在从约10℃至约65℃的温度范围内的条件下操作干蚀刻。
参照图2C，蚀刻栅极介电层210，并且形成凹槽420。蚀刻栅极介电层210的部分以形成栅极介电层410和位于伪栅极结构320下方的凹槽420。在一些实施例中，凹槽420可以具有凹槽角α。凹槽角α在约1°至约89°的范围内。在一些实施例中，凹槽角α在约20°至约70°的范围内。例如，凹槽角α为60°。可以通过干蚀刻形成凹槽420。在一些实施例中，干蚀刻中的气体选自由HBr、CF4、CHF3、CH4、CH2F2、N2H2、BCl3、Cl2、N2、H2、O2、He、Ar和它们的组合组成的组。可以在从约1毫托至约80毫托的压力范围内、在从约100W至约1500W的功率范围内和在从约10℃至约65℃的温度范围内的条件下操作干蚀刻。
参照图2D，形成围绕伪栅极结构320的保护层510。并且保护层510填充凹槽420。可以通过沉积形成保护层510。例如，沉积工艺可以是CVD、PVD、ALD或任何合适的方法。在一些实施例中，可以蚀刻位于衬底上的保护层510的部分，仅留下围绕伪栅极结构320的保护层510的部分。保护层510可以包括氧化硅、氮化硅、氮氧化硅、碳化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料、它们的组合或其他合适的材料。并且保护层510的材料不同于栅极介电层的材料。
参照图2E，形成接近保护层510的外延件610。在一些实施例中，可以通过以下步骤形成外延件610：蚀刻接近保护层510的衬底200以形成空腔620，然后在空腔620中生长外延件610。蚀刻工艺可以是干蚀刻、湿蚀刻或它们的组合，例如，首先进行干蚀刻并且然后实施湿蚀刻可以形成具有金刚石形状的空腔。在形成空腔620之后，实施外延(epi)工艺以在空腔620中形成外延件610。外延工艺可以包括选择性外延生长(SEG)工艺、循环沉积和蚀刻(CDE)工艺、化学汽相沉积(CVD)技术(例如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延(MBE)、其他合适的外延工艺和/或它们的组合。外延工艺可以使用气体前体和/或液体前体，前体可以与衬底200的组分相互作用。外延件610可以包括硅或硅锗(SiGe)。在一些实施例中，外延件可以掺杂有硼和/或BF2、或者磷和/或砷。在一些实施例中，外延件610可以具有金刚石形状或六边形形状。
参照图2F，在衬底200上方沉积层间介电(ILD)层720。并且暴露伪栅极层320，并且形成两个间隔件710。ILD层720可以包括氧化硅、氮氧化硅、可流动氧化物或低k材料。在一些实施例中，通过诸如化学汽相沉积(CVD)、高密度等离子体CVD、旋涂、溅射或其他合适的方法的沉积形成ILD层720。在后栅极工艺中，可以去除伪栅极结构320，从而使得产生的金属栅极结构可以形成为代替伪栅极结构320。因此，如图所示，可以通过化学机械抛光(CMP)工艺平坦化ILD层720，直到达到伪栅极层330的顶部。因此，通过CMP工艺暴露伪栅极层330。在一些实施例中，去除ILD层720的部分、保护层510的部分、第一硬掩模层340和第二硬掩模层350。在一些实施例中，也去除伪栅极层330的部分。并且由保护层510形成两个间隔件710。间隔件710包括边缘部分730。边缘部分730与衬底200接触。在一些实施例中，边缘部分730的形状是三角形。边缘部分730具有底角θ，其中，底角θ在约1°至约89°的范围内。在一些实施例中，底角θ在约20°至约70°的范围内。例如，底角θ为60°。在一些实施例中，边缘部分730延伸到栅极介电层410内。在一些实施例中，间隔件可以包括氧化硅、氮化硅、氮氧化硅、碳化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料、它们的组合或其他合适的材料。
参照图2G，去除伪栅极层330。可以通过干蚀刻或湿蚀刻去除伪栅极层330。蚀刻掉伪栅极层330，并且在间隔件710之间形成沟槽800。在以下操作中，可以在沟槽800内形成金属栅极结构。在一些实施例中，通过湿蚀刻工艺选择性地蚀刻伪栅极层330，该湿蚀刻工艺包括暴露于含氢氧化物的溶液(例如，氢氧化铵)、去离子水和/或其他合适的蚀刻剂溶液。
参照图2H，去除栅极介电层410。可以通过干蚀刻或湿蚀刻去除栅极介电层410。具有边缘部分730的的间隔件710可以防止蚀刻剂蚀刻穿间隔件710。间隔件710与衬底200直接接触，因此在间隔件710下方未保留栅极介电层410，并且在蚀刻操作期间没有隧道可以形成在间隔件下方。因此在以下操作中不会形成金属泄漏问题。
参照图2I，在间隔件710之间形成金属栅极结构900。可以通过诸如CVD、PVD、镀或其他合适的工艺的沉积工艺形成金属栅极结构900。在一些实施例中，金属栅极结构900包括位于衬底200上的高k介电层910、形成在高k介电层910上的金属层920以及位于金属层920上的金属栅电极930。金属栅电极930可以包括钨(W)、铝(Al)、钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)、钴(Co)、铜(Cu)、镍(Ni)、它们的组合和/或其他合适的材料。高k介电层910可以包括氧化铪(HfO2)。高k电介质的其他实例包括氧化铪硅(HfSiO)、氮氧化铪硅(HfSiON)、氧化铪钽(HMO)、氧化铪钛(HMO)、氧化铪锆(HfZrO)、它们的组合和/或其他合适的材料。金属层920可以是适合于形成金属栅极或其部分的任何金属材料，金属栅极或其部分包括功函层、衬垫层、界面层、晶种层、粘合层、阻挡层等。形成在高k介电层上的金属层920可以包括包含Ti、TiN、TaN、Ta、TaC、TaSiN、W、WN、MoN、MoON和其他合适的材料的一个或多个金属层。可以沉积的金属材料的实例包括P型金属材料和N型金属材料。P型金属材料可以包括诸如钌、钯、铂、钴、镍和导电金属氧化物和/或其他合适的材料的组分。N型金属材料可以包括诸如铪、锆、钛、钽、铝、金属碳化物(例如，碳化铪、碳化锆、碳化钛、碳化铝)、铝化合物和/或其他合适的材料的组分。在形成金属栅极结构900之后，实施CMP工艺以去除位于ILD层上的高k介电层、金属层和金属电极的部分。间隔件710具有延伸到金属栅极结构900内的边缘部分730，并且边缘部分730与衬底200接触。边缘部分730可以防止在形成金属栅极结构900的操作期间的金属泄漏。
参照图3，图3是根据一些实施例的制造半导体结构的方法的流程图。方法360开始于框362，其中，在衬底上形成栅极介电层和伪栅极堆叠件。在一些实施例中，衬底可以是硅衬底。在一些实施例中，伪栅极堆叠件包括沉积在栅极介电层上的伪栅极层、沉积在伪栅极层上的第一硬掩模层以及沉积在第一硬掩模层上的第二硬掩模层。并且可以通过热氧化或沉积形成栅极介电层。方法360继续进行框364，其中，蚀刻伪栅极堆叠件以形成伪栅极结构。然后方法360继续进行框366，其中，蚀刻栅极介电层以形成位于伪栅极结构下方的凹槽。在一些实施例中，蚀刻工艺是干蚀刻，并且干蚀刻中的气体选自由HBr、CF4、CHF3、CH4、CH2F2、N2H2、BCl3、Cl2、N2、H2、O2、He、Ar或它们的组合组成的组。在一些实施例中，凹槽具有在约1°至约89°的范围内的凹槽角α。方法360继续进行框368，其中，形成围绕伪栅极结构的保护层。并且保护层填充凹槽。方法360继续进行框370，其中，形成接近保护层的外延件。形成外延件包括蚀刻接近保护层的衬底以形成空腔以及在空腔中生长外延件。在一些实施例中，方法360还包括在衬底上方沉积ILD层。方法360继续进行框372，其中，由保护层形成具有边缘部分的间隔件。并且通过CMP工艺暴露伪栅极层，这意味着去除ILD层的部分、保护层的部分、第一硬掩模层和第二硬掩模层。方法360继续进行框374，其中，去除位于栅极介电层上的伪栅极结构。去除伪栅极结构包括蚀刻掉伪栅极层。方法360继续进行框376，其中，去除栅极介电层。方法360继续进行框378，其中，在间隔件之间形成金属栅极结构。可以通过沉积形成金属栅极结构，形成金属栅极结构可以包括在衬底上沉积高k介电层，在高k介电层上沉积金属层以及在金属层上沉积金属电极。方法360可以防止当形成金属栅极结构时的金属泄漏问题。
总之，可以实施后栅极工艺以形成金属栅极结构。通过蚀刻栅极介电层以形成位于伪栅极结构下方的凹槽，可以减少形成金属栅极结构的问题。因此，接近伪栅极结构形成的间隔件可以具有延伸到伪栅极结构内的边缘部分，并且边缘部分与衬底直接接触。伪栅极结构最终可以由金属栅极结构代替。并且具有边缘部分的间隔件可以有助于减少在代替金属栅极结构期间的金属泄漏问题。边缘部分可以防止蚀刻剂蚀刻穿间隔件，使半导体结构具有更好的可靠性。
根据本发明的其他各个实施例，一种半导体结构包括衬底、位于衬底上的金属栅极结构、以及接近金属栅极结构的间隔件，间隔件具有延伸至金属栅极结构内并且与衬底接触的边缘部分。
根据本发明的其他各个实施例，一种制造半导体结构的方法包括以下操作。在衬底上形成栅极介电层和伪栅极堆叠件。蚀刻伪栅极堆叠件以形成伪栅极结构。蚀刻栅极介电层以形成位于伪栅极结构下方的凹槽。形成围绕伪栅极结构并且填充凹槽的保护层。形成接近保护层的外延件。由保护层形成具有边缘部分的两个间隔件。去除位于栅极介电层上的伪栅极结构。去除栅极介电层。并且在间隔件之间形成金属栅极结构。
根据本发明的其他各个实施例，一种半导体结构包括从衬底延伸的鳍、位于衬底上的鳍的部分上方的金属栅极结构、邻近金属栅极结构的两个间隔件，间隔件具有延伸至金属栅极结构内的边缘部分，以及接近间隔件的两个外延件。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (18)

1.一种半导体结构，包括：
衬底；
金属栅极结构，位于所述衬底上；
间隔件，接近所述金属栅极结构，所述间隔件具有延伸至所述金属栅极结构内并且与所述衬底接触的边缘部分，其中所述边缘部分的形状为三角形，所述间隔件具有向内倾斜的部分；以及
外延件，接触所述向内倾斜的部分。
2.根据权利要求1所述的半导体结构，其中，所述金属栅极结构包括：
高k介电层，位于所述衬底上；
金属层，位于所述高k介电层上；以及
金属电极，位于所述金属层上。
3.根据权利要求1所述的半导体结构，其中，所述边缘部分的底角介于1°至89°的范围内。
4.一种制造半导体结构的方法，包括：
在衬底上形成栅极介电层和伪栅极堆叠件；
蚀刻所述伪栅极堆叠件以形成伪栅极结构；
蚀刻所述栅极介电层以形成位于所述伪栅极结构下方的凹槽；
形成围绕所述伪栅极结构并且填充所述凹槽的保护层；
形成接近所述保护层的外延件；
由所述保护层形成具有边缘部分的两个间隔件，其中所述边缘部分的形状为三角形，所述间隔件具有向内倾斜的部分，所述向内倾斜的部分接触所述外延件；
去除位于所述栅极介电层上的所述伪栅极结构；
去除所述栅极介电层；以及
在所述间隔件之间形成金属栅极结构。
5.根据权利要求4所述的方法，其中，在所述衬底上形成所述栅极介电层和所述伪栅极堆叠件包括：
在衬底上形成栅极介电层；
在所述栅极介电层上沉积伪栅极层；
在所述伪栅极层上沉积第一硬掩模层；以及
在所述第一硬掩模层上沉积第二硬掩模层。
6.根据权利要求5所述的方法，其中，在所述衬底上形成所述栅极介电层的方法是热氧化。
7.根据权利要求4所述的方法，其中，形成接近所述保护层的所述外延件包括：
蚀刻接近所述保护层的所述衬底以形成空腔；以及
在所述空腔中生长外延件。
8.根据权利要求4所述的方法，在形成接近所述保护层的所述外延件之后，还包括：
在所述衬底上方沉积ILD层。
9.根据权利要求5所述的方法，其中，去除位于所述栅极介电层上的所述伪栅极结构包括：
暴露所述伪栅极层；以及
蚀刻掉所述伪栅极层。
10.根据权利要求8所述的方法，其中，在所述间隔件之间形成所述金属栅极结构包括：
在所述衬底上沉积高k介电层；
在所述高k介电层上沉积金属层；以及
在所述金属层上沉积金属电极。
11.根据权利要求10所述的方法，在所述金属层上沉积所述金属电极之后，还包括：
实施化学机械抛光(CMP)以去除位于所述ILD层上的所述高k介电层、所述金属层和所述金属电极的部分。
12.根据权利要求4所述的方法，其中，蚀刻所述栅极介电层以形成位于所述伪栅极堆叠件下方的凹槽的方法是干蚀刻。
13.根据权利要求12所述的方法，其中，所述干蚀刻中的气体选自由HBr、CF4、CHF3、CH4、CH2F2、N2H2、BCl3、Cl2、N2、H2、O2、He、Ar和它们的组合组成的组。
14.根据权利要求4所述的方法，其中，蚀刻所述栅极介电层以形成位于所述伪栅极结构下方的所述凹槽，凹槽角α介于10°至80°的范围内。
15.一种半导体结构，包括：
鳍，从衬底延伸；
金属栅极结构，位于所述衬底上的所述鳍的部分上方；
两个间隔件，邻近所述金属栅极结构，所述间隔件具有延伸至所述金属栅极结构内的边缘部分，其中，所述边缘部分的形状为三角形，所述间隔件具有向内倾斜的部分；以及
两个外延件，接触所述向内倾斜的部分。
16.根据权利要求15所述的半导体结构，其中，所述金属栅极结构包括：
高k介电层，位于所述衬底上；
金属层，位于所述高k介电层上；以及
金属电极，位于所述金属层上。
17.根据权利要求15所述的半导体结构，其中，所述边缘部分与所述鳍接触。
18.根据权利要求17所述的半导体结构，其中，所述边缘部分的底角介于1°至89°的范围内。
CN201410812448.3A 2014-09-05 2014-12-23 半导体结构及其制造方法 Active CN105789300B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/478,915 US9812577B2 (en) 2014-09-05 2014-09-05 Semiconductor structure and fabricating method thereof
US14/478,915 2014-09-05

Publications (2)

Publication Number Publication Date
CN105789300A CN105789300A (zh) 2016-07-20
CN105789300B true CN105789300B (zh) 2020-05-15

Family

ID=55358582

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410812448.3A Active CN105789300B (zh) 2014-09-05 2014-12-23 半导体结构及其制造方法

Country Status (5)

Country Link
US (4) US9812577B2 (zh)
KR (1) KR101699133B1 (zh)
CN (1) CN105789300B (zh)
DE (1) DE102015106574B4 (zh)
TW (1) TWI565074B (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9812577B2 (en) * 2014-09-05 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof
CN104851884A (zh) * 2015-04-14 2015-08-19 上海华力微电子有限公司 用于锗硅填充材料的成形腔
WO2016187022A1 (en) 2015-05-15 2016-11-24 Skyworks Solutions, Inc. Cavity formation in semiconductor devices
CN105633130A (zh) * 2016-03-30 2016-06-01 上海华力微电子有限公司 用于SiGe填充材料的风筝形腔
KR102406668B1 (ko) * 2016-04-26 2022-06-08 삼성전자주식회사 결함 발생 방지를 위한 반도체 소자 제조 방법
TWI619283B (zh) 2016-05-30 2018-03-21 旺宏電子股份有限公司 電阻式記憶體元件及其製作方法與應用
CN106409913B (zh) * 2016-11-15 2019-04-09 中国科学院微电子研究所 具有连续侧墙的半导体设置及其制造方法
JP6919350B2 (ja) * 2017-06-09 2021-08-18 東京エレクトロン株式会社 基板処理方法及び基板処理装置
US20180366579A1 (en) * 2017-06-14 2018-12-20 Globalfoundries Inc. Laterally diffused field effect transistor in soi configuration
US10276690B2 (en) * 2017-07-31 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10749007B2 (en) * 2018-03-14 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure with desired profile for semiconductor devices
US11056392B2 (en) * 2018-03-29 2021-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices having gate stacks with protruding parts and method of forming the same
US20190305105A1 (en) * 2018-04-02 2019-10-03 Globalfoundries Inc. Gate skirt oxidation for improved finfet performance and method for producing the same
US10483368B1 (en) * 2018-05-15 2019-11-19 International Business Machines Corporation Single crystalline extrinsic bases for bipolar junction structures
US11309403B2 (en) 2019-10-31 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method of forming the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724025B1 (en) * 1998-06-30 2004-04-20 Kabushiki Kaisha Toshiba MOSFET having high and low dielectric materials
CN103579340A (zh) * 2012-08-10 2014-02-12 台湾积体电路制造股份有限公司 场效应晶体管的栅电极

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3173760B2 (ja) * 1994-11-11 2001-06-04 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6271094B1 (en) * 2000-02-14 2001-08-07 International Business Machines Corporation Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
KR100372643B1 (ko) * 2000-06-30 2003-02-17 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 제조방법
US6975014B1 (en) * 2001-01-09 2005-12-13 Advanced Micro Devices, Inc. Method for making an ultra thin FDSOI device with improved short-channel performance
KR100398874B1 (ko) * 2001-11-21 2003-09-19 삼성전자주식회사 티자형의 게이트 전극을 갖는 모스 트랜지스터 및 그 제조방법
KR100597460B1 (ko) * 2003-12-31 2006-07-05 동부일렉트로닉스 주식회사 반도체 소자의 트랜지스터 및제조방법
KR100642898B1 (ko) * 2004-07-21 2006-11-03 에스티마이크로일렉트로닉스 엔.브이. 반도체 장치의 트랜지스터 및 그 제조방법
JP4945900B2 (ja) * 2005-01-06 2012-06-06 ソニー株式会社 絶縁ゲート電界効果トランジスタおよびその製造方法
US7192856B2 (en) 2005-01-18 2007-03-20 Intel Corporation Forming dual metal complementary metal oxide semiconductor integrated circuits
US7838372B2 (en) * 2008-05-22 2010-11-23 Infineon Technologies Ag Methods of manufacturing semiconductor devices and structures thereof
US8436404B2 (en) 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
US8368147B2 (en) * 2010-04-16 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained semiconductor device with recessed channel
DE102010029532B4 (de) * 2010-05-31 2012-01-26 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Transistor mit eingebettetem verformungsinduzierenden Material, das in diamantförmigen Aussparungen auf der Grundlage einer Voramorphisierung hergestellt ist
DE102010030768B4 (de) * 2010-06-30 2012-05-31 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Herstellverfahren für ein Halbleiterbauelement als Transistor mit eingebettetem Si/Ge-Material mit geringerem Abstand und besserer Gleichmäßigkeit und Transistor
CN102376769B (zh) * 2010-08-18 2013-06-26 中国科学院微电子研究所 超薄体晶体管及其制作方法
US8617956B2 (en) * 2010-08-19 2013-12-31 International Business Machines Corporation Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device
KR20120019917A (ko) * 2010-08-27 2012-03-07 삼성전자주식회사 반도체 장치의 제조방법
KR20130045716A (ko) 2011-10-26 2013-05-06 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9087917B2 (en) * 2013-09-10 2015-07-21 Texas Instruments Incorporated Inner L-spacer for replacement gate flow
US9812577B2 (en) * 2014-09-05 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724025B1 (en) * 1998-06-30 2004-04-20 Kabushiki Kaisha Toshiba MOSFET having high and low dielectric materials
CN103579340A (zh) * 2012-08-10 2014-02-12 台湾积体电路制造股份有限公司 场效应晶体管的栅电极

Also Published As

Publication number Publication date
US20180040735A1 (en) 2018-02-08
DE102015106574B4 (de) 2021-11-18
KR101699133B1 (ko) 2017-01-23
TW201611285A (zh) 2016-03-16
US20160071980A1 (en) 2016-03-10
US9812577B2 (en) 2017-11-07
US11342458B2 (en) 2022-05-24
US10355135B2 (en) 2019-07-16
DE102015106574A1 (de) 2016-03-10
CN105789300A (zh) 2016-07-20
US20190341493A1 (en) 2019-11-07
TWI565074B (zh) 2017-01-01
KR20160029623A (ko) 2016-03-15
US10818794B2 (en) 2020-10-27
US20210043773A1 (en) 2021-02-11

Similar Documents

Publication Publication Date Title
US11342458B2 (en) Semiconductor structure and fabricating method thereof
US11410993B2 (en) Method of manufacturing semiconductor device
US11264484B2 (en) Structure and formation method of semiconductor device with gate stack
KR101396018B1 (ko) 금속 게이트를 갖는 반도체 집적 회로
US9246002B2 (en) Structure and method for semiconductor device
US10861701B2 (en) Semiconductor device and manufacturing method thereof
TWI604516B (zh) 半導體裝置及其製造方法
US9502527B2 (en) Semiconductor device structure having multi-layered insulating cap layers over metal gate
US9601594B2 (en) Semiconductor device with enhanced strain
US20220359675A1 (en) Source/Drain Via Having Reduced Resistance
US10312092B2 (en) Semiconductor structure and manufacturing method thereof
US20230268406A1 (en) Semiconductor device and manufacturing method thereof
US8093146B2 (en) Method of fabricating gate electrode using a hard mask with spacers
US11757018B2 (en) Formation method of semiconductor device with gate all around structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant