TWI545631B - 場效電晶體及其製造方法 - Google Patents

場效電晶體及其製造方法 Download PDF

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TWI545631B
TWI545631B TW102126417A TW102126417A TWI545631B TW I545631 B TWI545631 B TW I545631B TW 102126417 A TW102126417 A TW 102126417A TW 102126417 A TW102126417 A TW 102126417A TW I545631 B TWI545631 B TW I545631B
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gate electrode
source
field effect
effect transistor
stop layer
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TW102126417A
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TW201407673A (zh
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陳能國
萬幸仁
林奕安
張駿偉
孫詩平
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台灣積體電路製造股份有限公司
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Description

場效電晶體及其製造方法
本發明係有關於一種積體電路的製造，且特別是有關於一種具有閘極電極的場效電晶體。
隨著技術節點的縮減，在一些積體電路(IC)的設計中，欲以金屬閘極電極取代典型的多晶矽閘極電極，以提升尺寸縮減的裝置的效能。「後閘極(gate last)」製程係一種形成金屬閘極結構的製程，其中最終閘極結構在「最後」製造，因而能夠減少後續製程數目(包括高溫處理，其必須於閘極形成後進行)。此外，隨著電晶體尺寸的縮小，閘極氧化物的厚度也必須縮小，以維持縮減的閘極長度的效能。為了降低閘極漏損(leakage)，也使用高介電常數(high-k)閘極介電層，其可容許較大的物理厚度，同時其所提供的有效厚度可與用於較大技術結點中之具有低介電常數之較薄的閘極氧化物相同。
然而，在互補式金氧半(CMOS)的製作中，上述元件及製程面臨挑戰。例如，在「後閘極」的製造製程中難以達到場效電晶體(FET)的低閘極電阻(gate resistance)，其原因在於由金屬層沉積填入具高深寬比的溝槽後所形成的金屬閘極電極會產生空洞(voids)，因此裝置的不穩定性及/或裝置失敗的可能性增加。隨著閘極長度及裝置間的空間縮小，上述問題 也更加嚴重。
本發明一實施例提供一種場效電晶體，包括一基板；一閘極電極，位於該基板上，包括一第一頂表面及一側壁；一源極/汲極(S/D)區，至少部分設置於該基板中該閘極電極的一側；一間隙物，在該側壁上且位於該閘極電極及該源極/汲極區之間；以及一接觸蝕刻停止層(contact etch stop layer；CESL)，鄰接該間隙物，且更包括延伸至該源極/汲極區上的一部分，其中該部分具有一第二頂表面與該第一頂表面大抵共平面。
本發明另一實施例提供一種場效電晶體的製造方法，包括提供一基板，包括具有一側壁的一虛設閘極電極、一源極/汲極區、以及位於該側壁上的一間隙物位於該虛設閘極電極及該源極/汲極區之間；在該虛設閘極電極、該源極/汲極區及該間隙物上沉積一接觸蝕刻停止層(CESL)；在該接觸蝕刻停止層上沉積一層間介電(interlayer dielectric)層；利用一第一研磨漿(slurry)進行一第一化學機械研磨(CMP)以暴露出該虛設閘極電極上的該接觸蝕刻停止層；利用一第二研磨漿進行一第二化學機械研磨以暴露出該虛設閘極電極；移除該間隙物及該接觸蝕刻停止層的一上部分；以及利用該第一研磨漿進行一第三化學機械研磨以暴露出該源極/汲極區上的該接觸蝕刻停止層。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下：
100‧‧‧方法
102、104、106、108、110、112、114‧‧‧步驟
200‧‧‧場效電晶體
224‧‧‧閘極電極
224t‧‧‧頂表面
202‧‧‧基板
204‧‧‧主動區
206‧‧‧隔離區
212‧‧‧閘極介電層
210‧‧‧虛設閘極堆疊
214‧‧‧虛設閘極電極
214t‧‧‧頂表面
214w‧‧‧側壁
216‧‧‧間隙物
205‧‧‧源極/汲極凹孔
207‧‧‧應力材料
208‧‧‧源極/汲極區
202s‧‧‧基板表面
220‧‧‧閘極堆疊
222‧‧‧層間介電層
230‧‧‧第一化學機械研磨
232‧‧‧第一研磨漿
234‧‧‧第二化學機械研磨
236‧‧‧第二研磨漿
228‧‧‧凹孔
238‧‧‧第三化學機械研磨
218‧‧‧接觸蝕刻停止層
218a‧‧‧一部分
218t‧‧‧第二頂表面
226‧‧‧低深寬比溝槽
215‧‧‧剩餘的虛設閘極電極
t1‧‧‧第一厚度
t2‧‧‧第二厚度
第1圖為在本發明一些實施例中製造包括閘極電極的場效電晶體的方法的流程圖。
第2至12圖為在本發明一些實施例中之場效電晶體的閘極電極在不同製造階段的剖面圖。
因本發明之不同特徵而提供數個不同的實施例。本發明中特定的元件及安排係為了簡化，但本發明並不以這些實施例為限。舉例而言，於第二元件上形成第一元件的描述可包括第一元件與第二元件直接接觸的實施例，亦包括具有額外的元件形成在第一元件與第二元件之間、使得第一元件與第二元件並未直接接觸的實施例。此外，為簡明起見，本發明在不同例子中以重複的元件符號及/或字母表示，但不代表所述各實施例及/或結構間具有特定的關係。為了簡化及清楚，各種元件可以不同的尺寸繪製。此外，在本發明各實施例中以”後閘極”金屬閘極結構為例子，然而，本領域技藝人士可知悉其可應用於其他結構及/或利用其他材料。
第1圖顯示在本發明一些實施例中包括閘極電極的場效電晶體的製造方法100的流程圖。在方法100中，由步驟102開始。在步驟102中，提供基板，其中，基板包括具有側壁的虛設閘極電極、源極/汲極(S/D)區以及在側壁上的間隙物位在虛設閘極電極及源極/汲極區之間。方法100繼續進行至步驟 104，在步驟104中，在虛設閘極電極、源極/汲極區及間隙物上沉積接觸蝕刻停止層(contact etch stop layer；CESL)。方法100繼續進行至步驟106，在步驟106中，在接觸蝕刻停止層上沉積層間介電(interlayer dielectric)層。方法100繼續進行至步驟108，在步驟108中，利用第一研磨漿(slurry)進行第一化學機械研磨(CMP)以暴露出虛設閘極電極上的接觸蝕刻停止層。方法100繼續進行至步驟110，在步驟110中，利用第二研磨漿進行第二化學機械研磨以暴露出虛設閘極電極。方法100繼續進行至步驟112，在步驟112中，移除間隙物及接觸蝕刻停止層的上部分。方法100繼續進行至步驟114，在步驟114中，利用第一研磨漿進行第三化學機械研磨以暴露出源極/汲極區上的接觸蝕刻停止層。以下所述實施例中的場效電晶體可依據第1圖的方法100製造。
第2至12圖顯示在本發明一些實施例中的場效電晶體(FET)200的閘極電極224在不同的製造階段的剖面圖。在一些實施例中，場效電晶體200為平面式(planar)場效電晶體。在一些實施例中，場效電晶體200為鰭式場效電晶體。場效電晶體200可包括於微處理器(microprocessor)、記憶體單元(memory cell)、及/或其他積體電路中。在一些實施例中，在第1圖中所述操作步驟並非形成一個完整的場效電晶體200。完整的場效電晶體200可利用互補式金氧半(CMOS)技術製程來製造。因此，在第1圖的方法100之前、之中、及/或之後可進行額外的製程，且一些其他的製程在此僅簡單描述。此外，第2至12圖已經過簡化以便更清楚的了解本發明之概念。例如，雖 然在圖式中顯示場效電晶體200，積體電路可包括一些其他的裝置，包括電阻、電容、電感(inductor)、保險絲(fuse)等。
參照第2圖及步驟102，提供基板202。在至少一實施例中，基板202包括結晶矽(crystalline silicon)基板(例如：晶圓)。在一些其他實施例中，基板202的形成可利用一些其他元素半導體(elemental semiconductor)，如鑽石或鍺；適合的化合物半導體(compound semiconductor)，如砷化鎵(gallium arsenide)、碳化矽(silicon carbide)、砷化銦(indium arsenide)、或磷化銦(indium phosphide)；或者適合的一合金半導體(alloy semiconductor)，如碳矽化鍺(silicon germanium carbide)、磷砷化鎵(gallium arsenic phosphide)、或磷化砷銦(gallium indium phosphide)。此外，基板202可包括磊晶層(epi-layer)，可被應變(strained)以增加效能，及/或可包括絕緣層上矽(silicon-on-insulator；SOI)結構。
基板202可更包括主動區204(為了簡化的緣故，圖中只顯示一個主動區)及隔離區206。主動區204可根據需要設計為包括不同的摻雜特徵。在一些實施例中，主動區204以p型或n型摻質摻雜。例如，主動區204的摻雜可利用：p型摻質，例如硼或氟化硼(BF2)；n型摻質，例如磷或砷；及/或前述之組合。主動區204可作為n型金氧半電晶體(稱為nMOSFET)的區域，或者可作為p型金氧半電晶體(稱為pMOSFET)的區域。
隔離區206可形成於基板202上，以隔離各主動區204。隔離區206可利用隔離技術，如局部矽氧化技術(local oxidation of silicon；LOCOS)或淺溝槽隔離(STI)，以定義並電 性隔離各主動區204。在所述實施例中，隔離區206包括淺溝槽隔離。隔離區206可包括氧化矽、氮化矽、氮氧化矽、氟摻雜矽玻璃(fluoride-doped silicate glass；FSG)、低介電常數材料、其他適當的材料、及/或前述之組合。在此實施例中，隔離區206可利用任何適當的製程形成。例如，淺溝槽隔離的形成可包括利用傳統的光微影製程(photolithography process)圖案化半導體基板202、在基板202中蝕刻溝槽(例如，利用乾蝕刻、濕蝕刻、及/或電漿蝕刻製程)、以及以介電材料填入溝槽(例如，利用化學氣相沉積製程)。在一些實施例中，填入的溝槽可具有多層結構，例如熱氧化襯層(thermal oxide liner layer)填上氮化矽或氧化矽。
而後，在基板202上形成閘極介電層212。在一些實施例中，閘極介電層212可包括氧化矽、高介電常數材料或前述之組合。高介電常數材料的定義為該材料的介電常數大於氧化矽的介電常數。高介電常數層包括金屬氧化物。金屬氧化物係擇自下述金屬的氧化物，如：鋰(Li)、鈹(Be)、鎂(Mg)、鈣(Ca)、鍶(Sr)、鈧(Sc)、釔(Y)、鋯(Zr)、鉿(Hf)、鋁(Al)、鑭(La)、鈰(Ce)、鐠(Pr)、釹(Nd)、釤(Sm)、銪(Eu)、釓(Gd)、鋱(Tb)、鏑(Dy)、鈥(Ho)、鉺(Er)、銩(Tm)、鐿(Yb)、或鎦(Lu)，或前述之混合物。閘極介電層212的形成可利用熱氧化製程、化學氣相沉積製程、原子層沉積(ALD)製程，且其可具有小於2奈米(nm)的厚度。
閘極介電層212可更包括介面層(interfacial layer；圖中未顯示)以最小化閘極介電層212及基板202間的應 力。可藉由熱氧化製程成長氧化矽或氮氧化矽以形成介面層。例如，介面層的形成可利用快速熱氧化製程(Rapid thermal oxidation process；RTO)或包含氧的回火製程。
而後，可在閘極介電層212上形成虛設閘極電極214。在一些實施例中，虛設閘極電極214可包括單一層或多層結構。在此實施例中，虛設閘極電極214可包括多晶矽。此外，虛設閘極電極214可為具有相同或梯度(gradient)摻雜的多晶矽。虛設閘極電極214可具有任何適當的厚度。在此實施例中，虛設閘極電極214的厚度介於約30奈米至約60奈米。可利用低壓化學氣相沉積(LPCVD)製程形成虛設閘極電極214。
之後，圖案化虛設閘極電極214及閘極介電層212以形成第2圖所示結構。利用適當的製程(例如利用旋轉塗佈)在虛設閘極電極214上形成光阻層(圖中未顯示)，並利用適當的微影圖案化方法在虛設閘極電極214上形成圖案化的光阻特徵。圖案化光阻特徵的寬度介於約10奈米至約45奈米。而後，可利用乾蝕刻製程將圖案化光阻特徵轉移到下方的層狀物(亦即，虛設閘極電極214及閘極介電層212)以形成複數個虛設閘極堆疊210。虛設閘極電極214包括頂表面214t及側壁214w。之後可剝除光阻層。
而後，在閘極堆疊210的周圍沉積順應的間隙物材料。在此實施例中，間隙物材料可包括氮化矽(silicon nitride)、氮氧化矽(silicon oxy-nitride)、碳化矽(silicon carbide)、碳摻雜氮化矽(carbon-doped silicon nitride)或其他適當的材料。間隙物材料可包括單一層或多層結構。間隙物材料的毯覆層 (blanket layer)的形成可利用化學氣相沉積(CVD)、原子層沉積(ALD)、物理氣相沉積(PVD)、或其他適當的技術。毯覆層的厚度介於約5奈米至15奈米。而後，在間隙物材料上進行非等相性蝕刻(anisotropic etching)以在虛設閘極電極214的側壁214w上形成一對間隙物216。
而後，利用閘極堆疊210及一對間隙物216作為硬罩幕，進行偏(biased)蝕刻製程以凹陷未受保護或暴露出來的基板202，以在主動區204中形成源極/汲極凹孔(S/D cavities)205(如第3圖所示)。在一實施例中，可利用化學物質如NF3、CF4、或SF6作為蝕刻氣體進行蝕刻製程。在另一實施例中，可利用溶液如NH4OH或H2O2進行蝕刻製程。
參照第4圖及第1圖中的步驟102，在主動區204中形成源極/汲極(S/D)凹孔205之後，在源極/汲極凹孔205中磊晶成長應力材料207以形成第4圖中的源極/汲極區208，其中應力材料207的晶格常數不同於基板202的晶格常數。亦即，各源極/汲極區208至少部分設置於基板202中虛設閘極電極214的一側。在一些實施例中，源極/汲極區208延伸至基板表面202s上。在一些實施例中，源極/汲極區208完全在基板表面202s下(圖中未顯示)。
在一些實施例中，n型金氧半場效電晶體(nMOSFET)的應力材料207包括碳化矽(SiC)或磷化矽(SiP)。可利用低壓化學氣相沉積(LPCVD)製程選擇性的成長應力材料207(如碳化矽)以形成源極/汲極區208。在此實施例中，低壓化學氣相沉積製程係在約在400℃至約800℃下、在約1Torr至約 15Torr下、利用SiH4、CH4、及H2作為反映氣體。
在一些實施例中，p型金氧半場效電晶體(pMOSFET)的應力材料207包括矽鍺(SiGe)或硼化矽鍺(SiGeB)。可利用低壓化學氣相沉積(LPCVD)製程選擇性的成長應力材料207(如矽鍺)以形成源極/汲極區208。在此實施例中，低壓化學氣相沉積製程係在約在660℃至約700℃下、在約13Torr至約50Torr下、利用SiH2Cl2、HCl、GeH4、B2H6及H2作為反應氣體。
在一些實施例中，可利用自效準(self-aligned)矽化(silicide；salicide)製程選擇性的在源極/汲極區208上形成矽化物區(圖中未顯示)。例如，矽化製程可包括二個步驟。首先，在溫度約500℃至約900℃下藉由濺鍍在源極/汲極區208上沉積金屬材料，使金屬材料與其下的矽反映形成矽化物區。而後，蝕刻移除未反應的金屬材料。矽物化區的材料可包括矽化鈦(titanium silicide)、矽化鈷(cobalt silicide)、矽化鎳(nickel silicide)、矽化鉑(platinum silicide)、矽化鉺(erbium silicide)、或矽化鈀(palladium silicide)。
參照第5圖及第1圖的步驟104，在主動區204中形成源極/汲極區208之後，在虛設閘極電極214、源極/汲極區208及間隙物216上沉積第5圖所示接觸蝕刻停止層(CESL)218並沿著淺溝槽隔離區206延伸。接觸蝕刻停止層218可包括氮化矽(silicon nitride)、氮氧化矽(silicon oxy-nitride)、碳化矽(silicon carbide)、或碳摻雜氮化矽(carbon-doped silicon nitride)，但並非以此為限。接觸蝕刻停止層218的厚度可介於約15奈米至約 20奈米。
在一些實施例中，接觸蝕刻停止層218的沉積可利用化學氣相沉積(CVD)、高密度電漿(high density plasma；HDP)化學氣相沉積、次大氣壓化學氣相沉積(sub-atmosphere CVD；SACVD)、分子層沉積(molecular layer deposition；MLD)、濺鍍、或其他適合的方法。例如，在此實施例中的分子層沉積製程可在壓力小於10mTorr、溫度介於約350℃至約500℃下進行。在至少一實施例中，藉由反應一矽源化合物(silicon source compound)及一氮源(nitrogen source)，在閘極電極214、源極/汲極區208及間隙物216上沉積氮化矽。矽源化合物提供沉積氮化矽的矽，且可為矽烷(silane)或四乙氧基矽烷(tetraoxysilane；TEOS)。氮源提供沉積氮化矽的氮，且可為氨(NH3)或氮氣(N2)。在另一實施例中，藉由反應一碳源化合物(carbon source compound)、一矽源化合物及一氮源，在閘極電極214、源極/汲極區208及間隙物216上沉積碳摻雜氮化矽。碳源化合物可為有機化合物，如碳氫化合物，例如乙烯(ethylene；C2H6)，且矽源化合物及氮源可與接觸蝕刻停止層的氮化矽相同。
參照第6圖及第1圖中的步驟106，在沉積接觸蝕刻停止層218之後，在接觸蝕刻停止層218上沉積層間介電層(interlayer dielectric layer；ILD layer)222。層間介電層222可包括介電材料。介電材料可包括氧化矽、氮化矽、氮氧化矽、磷矽玻璃(phosphosilicate glass；PSG)、硼磷矽玻璃(borophosphosilicate glass；BPSG)、旋塗玻璃(SOG)、氟矽玻 璃(FSG)、碳摻雜氧化矽(例如：SiCOH)、Black Diamond®(源自Santa Clara，加州)、Xerogel(乾凝膠)、Aerogel(氣凝膠)、非晶矽氟化碳(amorphous fluorinated carbon)、Parylene(聚對二甲苯)、雙苯並環丁烯(BCB；bis-benzocyclobutene)、Flare、SiLK®(源自Dow Chemical；Midland；Michigan)、聚亞醯氨(polyimide)、及/或前述之組合。層間介電層222可包括一或多種介電材料及/或一或多個介電層。在一些實施例中，可在接觸蝕刻停止層218上沉積適當厚度的層間介電層222，例如利用化學氣相沉積、高密度電漿(high density plasma；HDP)化學氣相沉積、次大氣壓化學氣相沉積(SACVD)、旋塗、濺鍍、或其他適合的方法。在此實施例中，層間介電層222可包括一厚度介於約3000埃至約4500埃。
在一後閘極製程中，可移除虛設閘極電極214，而在虛設閘極電極214的位置形成金屬閘極電極224(如第12圖所示)。利用化學機械研磨製程(第1圖中的步驟108、110)平坦化層間介電層222及接觸蝕刻停止層218直到暴露出或達到虛設閘極電極層214的頂表面214t。
參照第7圖及第1圖中的步驟108，在接觸蝕刻停止層218上形成層間介電層222之後，以第一研磨漿232進行第一化學機械研磨(chemical mechanical polishing)230而暴露出虛設閘極電極214上的接觸蝕刻停止層218，如第7圖所示結構。在此實施例中，第一化學機械研磨230係在下述條件下進行：頭旋轉速度(head rotation speed)為約50rpm至約150rpm，平板旋轉速度(platen rotation speed)為約50rpm至約150rpm，向下 壓力(down force)為約1psi至約4psi，研磨漿流速(slurry flow rate)為每分鐘約100mL至每分鐘約300mL。在一些實施例中，第一研磨漿232包括氧化鈰(CeO2)。
參照第8圖及第1圖中的步驟110，在第一化學機械研磨230暴露出接觸蝕刻停止層218之後，利用第二研磨漿236進行第二化學機械研磨234而暴露出虛設閘極電極214，如第8圖所示結構。在此實施例中，第二化學機械研磨234係在下述條件下進行：頭旋轉速度(head rotation speed)為約50rpm至約150rpm，平板旋轉速度(platen rotation speed)為約50rpm至約150rpm，向下壓力(down force)為約1psi至約4psi，研磨漿流速(slurry flow rate)為每分鐘約100mL至每分鐘約300mL。在一些實施例中，第二化學機械研磨234可具有高度選擇性，以提供虛設閘極電極214、間隙物216、接觸蝕刻停止層218及層間介電層222大抵平坦的表面。
在一些實施例中，在化學機械研磨製程後，進行閘極取代製程。藉由濕蝕刻及/或乾蝕刻製程，可將虛設閘極電極214由被介電質(包括間隙物216、接觸蝕刻停止層218、及層間介電層222)圍繞著的閘極移除，以在介電質中形成高深寬比(例如：大於3)的溝槽。
而後，在高深寬比的溝槽中填入金屬層。金屬層可包括任何適合用以形成金屬閘極電極或其一部分的金屬材料，包括阻障物(barriers)、功函數層(work function layer)、襯層(liner layer)、介面層(interface layer)、種子層(seed layer)、黏著層(adhesion layer)、阻障層(barrier layer)等。金屬層可利 用物理氣相沉積(PVD)製程形成。
然而，物理氣相沉積製程易於在高深寬比溝槽的開口形成金屬突出物(metal overhang)，而金屬突出物容易堵塞高深寬比溝槽的開口。即使金屬突出物並未實際封住高深寬比溝槽，金屬突出物至少會造成高深寬比溝槽之開口直徑的縮減，因而妨礙金屬材料更進一步的進入高深寬比溝槽中，而在高深寬比溝槽中產生空洞(voids)，使得裝置不穩定及/或裝置失效的可能性增加。
因此，在第9至12圖所示製程中，可移除至少一部分的虛設閘極電極214以形成低深寬比的溝槽，使得後續沉積於低深寬比溝槽易於高深寬比溝槽。藉此可降低低深寬比溝槽中之金屬閘極電極中空洞的產生，且可提升裝置效能。
如第9圖及第1圖的步驟112所示，在製造場效電晶體200的低深寬比金屬閘極電極(如第12圖所示的金屬閘極電極224)時，移除接觸蝕刻停止層218及間隙物216的上部分以形成第9圖所示結構。利用閘極堆疊210及層間介電層222作為硬罩幕，進行濕蝕刻及/或乾蝕刻以凹陷未被保護或暴露出的接觸蝕刻停止層218及間隙物216的上部分，以形成低於頂表面214t的凹孔(cavity)228。在一些實施例中，用於氮化矽接觸蝕刻停止層218及氮化矽間隙物216的濕蝕刻製程包括暴露於含有熱磷酸(H3PO4)的溶液。在一些實施例中，乾蝕刻製程的進行可在溫度約10℃至約70℃下，源功率(source power)在約300W至約1000W，偏功率(bias power)在約50W至約300W，壓力在約10mTorr至約100mTorr，利用反應氣體包括CH3F。
參照第10圖及第1圖中的步驟114，在移除接觸蝕刻停止層218及間隙物216的上部分之後，利用第一研磨漿232進行第三化學機械研磨238以暴露出源極/汲極區208上的接觸蝕刻停止層218，如第10圖所示結構，其中接觸蝕刻停止層218鄰接至間隙物216，且更包括延伸至源極/汲極區208上的一部分218a，其中該部分218a具有第二頂表面218t與剩餘的虛設閘極電極215的頂表面215t大抵共平面。剩餘的虛設閘極電極215具有低深寬比(介於約0.8至約1.2)。在此實施例中，第三化學機械研磨238係在下述條件下進行：頭旋轉速度(head rotation speed)為約50rpm至約150rpm，平板旋轉速度(platen rotation speed)為約50rpm至約150rpm，向下壓力(down force)為約1psi至約4psi，研磨漿流速(slurry flow rate)為每分鐘約100mL至每分鐘約300mL。在一些實施例中，第一研磨漿232包括氧化鈰(CeO2)。
第11圖顯示第10圖的場效電晶體200將剩餘的低深寬比虛設閘極電極215自虛設閘極堆疊210移除後，在一對側壁間隙物216中形成低深寬比溝槽226。可利用濕蝕刻及/或乾蝕刻製程移除剩餘的虛設閘極電極215。在至少一實施例中，用於虛設多晶矽閘極電極215的濕蝕刻製程包括暴露於含有氨水(ammonium hydroxide)、稀釋的氫氟酸(HF)、去離子水的氫氧化物溶液、及/或其他適合的蝕刻劑溶液。在其他實施例中，用於剩餘的虛設閘極電極層215的乾蝕刻製程的進行可在源功率(source power)在約650W至約800W，偏功率(bias power)在約100W至約120W，壓力在約60mTorr至約200mTorr，利用氯氣 (Cl2)、溴化氫(HBr)、及氦(He)作為反應氣體。
低深寬比溝槽226可使得金屬材料比較容易填入低深寬比溝槽226中。因此，在上述方法中所形成場效電晶體200的低深寬比金屬閘極224(如第12圖所示)可減少低深寬比溝槽226中的金屬閘極電極224中空洞的產生，並提升裝置效能。
參照第12圖，在形成低深寬比溝槽226之後，將金屬層填入低深寬比溝槽226。例如，金屬層包括P型功函數金屬或N型功函數金屬。在一些實施例中，P型功函數金屬包括氮化鈦(TiN)、氮化鎢(WN)、氮化鉭(TaN)、或釕(Ru)。在一些實施例中，N型功函數金屬包括鈦(Ti)、銀(Ag)、鋁(Al)、鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、碳化鉭(TaC)、氮碳化鉭(TaCN)、氮矽化鉭(TaSiN)、錳(Mn)、或鋯(Zr)。可在金屬層上進行另一化學機械研磨，以形成場效電晶體200的金屬閘極電極，其中接觸蝕刻停止層218鄰接至間隙物216，且更包括延伸至源極/汲極區208上的一部分218a，其中該部分218a具有第二頂表面218t，其與金屬閘極電極224的頂表面224t大抵共平面。在一些實施例中，金屬閘極電極224的深寬比介於約0.8至約1.2。在此實施例中，結合金屬閘極電極224及閘極介電層212並合稱為閘極堆疊220。
若源極/汲極區208延伸至基板表面202s上，則閘極電極224的第一厚度t1大於接觸蝕刻停止層218延伸至源極/汲極區208上的部分218a的第二厚度t2。在一些實施例中，第一厚度t1對第二厚度t2的比率介於約1.1至約1.5。若源極/汲極區208在基板表面202s下(圖中未顯示)，則閘極電極224的第一厚度t1 小於接觸蝕刻停止層218延伸至源極/汲極區208上的部分218a的第二厚度t2。在一些實施例中，第一厚度t1對第二厚度t2的比率介於約0.5至約0.9。
在一些實施例中，在進行第1至12圖所示步驟後，可進行後續製程(包括內連線製程)以完成場效電晶體200的製作。
在一實施例中，場效電晶體包括一基板；一閘極電極，位於該基板上，包括一第一頂表面及一側壁；一源極/汲極(S/D)區，至少部分設置於該基板中該閘極電極的一側；一間隙物，在該側壁上且位於該閘極電極及該源極/汲極區之間；以及一接觸蝕刻停止層(contact etch stop layer；CESL)，鄰接該間隙物，且更包括延伸至該源極/汲極區上的一部分，其中該部分具有一第二頂表面與該第一頂表面大抵共平面。
在另一實施例中，場效電晶體的製造方法，包括提供一基板，包括具有一側壁的一虛設閘極電極、一源極/汲極區、以及位於該側壁上的一間隙物位於該虛設閘極電極及該源極/汲極區之間；在該虛設閘極電極、該源極/汲極區及該間隙物上沉積一接觸蝕刻停止層(CESL)；在該接觸蝕刻停止層上沉積一層間介電(interlayer dielectric)層；利用一第一研磨漿(slurry)進行一第一化學機械研磨(CMP)以暴露出該虛設閘極電極上的該接觸蝕刻停止層；利用一第二研磨漿進行一第二化學機械研磨以暴露出該虛設閘極電極；移除該間隙物及該接觸蝕刻停止層的一上部分；以及利用該第一研磨漿進行一第三化學機械研磨以暴露出該源極/汲極區上的該接觸蝕刻停止層。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200‧‧‧場效電晶體
220‧‧‧閘極堆疊
218‧‧‧接觸蝕刻停止層
206‧‧‧隔離區
208‧‧‧源極/汲極區
224t‧‧‧頂表面
224‧‧‧閘極電極
218a‧‧‧一部分
218t‧‧‧第二頂表面
216‧‧‧間隙物
222‧‧‧層間介電層
202s‧‧‧基板表面
202‧‧‧基板
204‧‧‧主動區
t1‧‧‧第一厚度
t2‧‧‧第二厚度

Claims (10)

  1. 一種場效電晶體，包括：一基板，包括一隔離區；一閘極電極，位於該基板上，包括一第一頂表面及一側壁；一源極/汲極(S/D)區，至少部分設置於該閘極電極與該隔離區之間的該基板中；一間隙物，在該側壁上且位於該閘極電極及該源極/汲極區之間；以及一接觸蝕刻停止層(contact etch stop layer；CESL)，鄰接該間隙物，且延伸至該源極/汲極區及該隔離區上，其中對應於該源極/汲極區及該隔離區上的該接觸蝕刻停止層具有一第二頂表面與該第一頂表面大抵共平面。
  2. 如申請專利範圍第1項所述之場效電晶體，其中該閘極電極的深寬比(aspect ratio)介於約0.8至約1.2。
  3. 如申請專利範圍第1項所述之場效電晶體，其中該源極/汲極區延伸至該基板表面上，且該閘極電極的一第一厚度大於對應於該源極/汲極區的該接觸蝕刻停止層的一第二厚度。
  4. 如申請專利範圍第3項所述之場效電晶體，其中該第一厚度對該第二厚度的比介於約1.1至約1.5。
  5. 如申請專利範圍第1項所述之場效電晶體，其中該源極/汲極區完全位於該基板表面下，且該閘極電極的一第一厚度小於對應於該源極/汲極區的該接觸蝕刻停止層的一第二厚度。
  6. 如申請專利範圍第5項所述之場效電晶體，其中該第一厚度 對該第二厚度的比介於約0.5至約0.9。
  7. 如申請專利範圍第1項所述之場效電晶體，其中該源極/汲極區包括一應力材料(strained material)，其中該應力材料的一晶格常數不同於該基板的一晶格常數。
  8. 一種場效電晶體的製造方法，包括：提供一基板，包括具有一側壁的一虛設閘極電極、一源極/汲極區、以及位於該側壁上的一間隙物位於該虛設閘極電極及該源極/汲極區之間；在該虛設閘極電極、該源極/汲極區及該間隙物上沉積一接觸蝕刻停止層(CESL)；在該接觸蝕刻停止層上沉積一層間介電(interlayer dielectric)層；利用一第一研磨漿(slurry)進行一第一化學機械研磨(CMP)以暴露出該虛設閘極電極上的該接觸蝕刻停止層；利用一第二研磨漿進行一第二化學機械研磨以暴露出該虛設閘極電極；移除該間隙物及該接觸蝕刻停止層的一上部分；以及利用該第一研磨漿進行一第三化學機械研磨以暴露出該源極/汲極區上的該接觸蝕刻停止層。
  9. 如申請專利範圍第8項所述之場效電晶體的製造方法，其中該第一研磨漿包括氧化鈰(CeO2)。
  10. 如申請專利範圍第8項所述之場效電晶體的製造方法，其中該第二研磨漿包括二氧化矽(SiO2)。
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