CN103035526A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN103035526A
CN103035526A CN2012100057119A CN201210005711A CN103035526A CN 103035526 A CN103035526 A CN 103035526A CN 2012100057119 A CN2012100057119 A CN 2012100057119A CN 201210005711 A CN201210005711 A CN 201210005711A CN 103035526 A CN103035526 A CN 103035526A
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substrate
recess cavity
crystal face
epi
protective layer
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CN103035526B (zh
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李彦儒
游明华
李资良
李启弘
蔡邦彦
舒丽丽
林逸宏
郑有宏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/7845—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

公开了一种用于制造半导体器件的方法。在衬底的腔室中且邻近衬底中的隔离结构形成应变材料。应变材料具有位于衬底的表面上方的角部。所公开的方法提供了改进方法，该改进方法用于形成邻近隔离结构并具有位于衬底腔室中的增加部分的应变材料，从而增强载流子迁移率并且提升器件性能。在实施例中，采用蚀刻工艺通过去除至少一部分角部来再分布应变材料使其位于腔室中，从而实现改进的形成方法。本发明提供了半导体器件及其制造方法。

Description

半导体器件及其制造方法
技术领域
本发明涉及集成电路制造，更具体地说，涉及具有应变结构的半导体器件。
背景技术
当诸如金属氧化物半导体场效应晶体管(MOSFET)的半导体器件通过各种技术节点按比例缩小时，将高k栅极介电层和金属栅电极层结合在MOSFET的栅叠层中，从而随部件尺寸的降低而改进器件性能。另外，可以使用应用选择性生长的硅锗(SiGe)的MOSFET的源极和漏极(S/D)凹进腔中的应变结构来提高载流子迁移率。
然而，在互补金属氧化物半导体(CMOS)制造中应用这些部件和工艺存在挑战。当器件之间的栅极长度和间隔减小时，加重了这些问题。例如，因为应变材料不能将给定量的应变传递至半导体器件的沟道区域中，所以很难实现提高半导体器件的载流子迁移率，从而增大了器件不稳定和/或器件故障的可能性。
发明内容
一方面，本发明提供了一种用于制造半导体器件的方法，包括：提供具有表面的衬底；在所述衬底中形成隔离部件；在所述衬底的所述表面上方形成栅叠层；在所述衬底中形成凹进腔，其中，将所述凹进腔水平地设置在所述栅叠层和所述隔离部件之间；在所述凹进腔中形成外延(epi)材料，其中，所述外延材料具有位于所述凹进腔上方的角部；以及实施蚀刻工艺以再分布至少一部分所述角部使其位于所述凹进腔中。
根据本发明所述的方法，进一步包括：在蚀刻步骤之前，在所述外延材料上方形成保护层。其中，所述保护层是通过外延生长工艺形成的Si。并且其中，在形成所述保护层之后，原位实施蚀刻步骤。
根据本发明所述的方法，其中，使用含氯气体和载气实施蚀刻步骤。所述含氯气体是Cl2和/或HCl。所述载气是H2和/或N2。所述含氯气体的流速处于约50sccm至约300sccm的范围内，以及所述载气的流速处于约3slm至约4slm(每分钟标准立升)的范围内。
根据本发明所述的方法，其中，所述外延材料是SiGe。
根据本发明所述的方法，进一步包括：在蚀刻步骤之后，在所述外延材料上方形成接触部件。
根据本发明所述的方法，其中，所述外延材料在蚀刻步骤之前包含(111)晶面而在蚀刻步骤之后包含(311)晶面。
根据本发明所述的方法，其中，所述角部具有尖端高度，所述尖端高度处于约1nm和约10nm之间的范围内。
根据本发明所述的方法，其中，在蚀刻步骤之前，在所述衬底表面的法线和所述外延材料平面的法线之间具有第一角度，而在蚀刻步骤以后，在所述衬底表面的法线和所述外延材料平面的法线之间具有第二角度，其中，所述第二角度小于所述第一角度。
另一方面，本发明提供了一种制造半导体器件的方法，包括：在衬底中形成隔离部件；在所述衬底上方形成栅叠层；在所述衬底中形成源极/漏极(S/D)凹进腔，其中，将所述S/D凹进腔设置在所述栅叠层和所述隔离部件之间；在所述S/D凹进腔中形成外延(epi)材料，其中，所述外延材料具有上表面，所述上表面具有第一晶面；以及使用含氯气体对所述S/D凹进腔中的所述外延材料实施再分布工艺，其中，在再分布之后，将所述第一晶面转变成第二晶面。
根据本发明所述的方法，其中，所述含氯气体是流速处于约50sccm至约300sccm范围内的Cl2和/或HCl。
根据本发明所述的方法，其中，使用所述含氯气体和载气实施所述再分布工艺。
根据本发明所述的方法，其中，所述第一晶面包含(111)晶面以及所述第二晶面包含(311)晶面。
根据本发明所述的方法，其中，使用蚀刻气体而不提供电源或生成等离子体来实施所述再分布工艺。
根据本发明所述的方法，其中，在形成所述外延材料之后，原位实施所述再分布工艺。
又一方面，本发明提供了一种制造半导体器件的方法，包括：提供具有表面的衬底；在所述衬底中形成隔离部件；在所述衬底的所述表面上方形成栅叠层；在所述衬底中形成凹进腔，其中，将所述凹进腔水平地设置在所述栅叠层和所述隔离部件之间；在所述凹进腔中形成具有第一晶面的外延(epi)材料，其中，所述外延材料具有位于所述凹进腔上方的角部；在所述外延(epi)材料上方形成保护层；实施蚀刻工艺，以去除所述保护层并再分布所述外延(epi)材料以去除至少一部分所述角部使其位于所述凹进腔中，其中，所述再分布的外延(epi)材料具有第二晶面，所述第二晶面与所述第一晶面不同；以及在所述再分布的外延(epi)材料上方形成接触部件。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚起见讨论，各种部件的尺寸可以被任意增大或缩小。
图1为示出了根据本发明的各个方面用于制造包括应变结构的半导体器件的方法的流程图；以及
图2至图8示出了根据本发明的各个方面在各个制造阶段的半导体器件的应变结构的示意性横截面图。
具体实施方式
可以理解为了实施本发明的不同部件，以下公开内容提供了许多不同的实施例或实例。在下面描述元件和布置的特定实例以简化本发明。当然这些仅仅是实例并不打算限定。例如，以下描述中第一部件在第二部件上方或者在第二部件上的形成可以包括其中第一部件和第二部件以直接接触形成的实施例，并且也可以包括其中可以在第一部件和第二部件之间形成额外的部件，使得第一部件和第二部件可以不直接接触的实施例。再者，本发明可以在各个实例中重复参照数字和/或字母。这种重复是为了简明和清楚的目的，而且其本身没有规定所讨论的各个实施例和/或结构之间的关系。
图1为示出了根据本发明的各个方面用于制造半导体器件200的方法100的流程图。图2至图8示出了根据图1的方法100的实施例在各个制造阶段的半导体器件200的示意性横截面图。半导体器件200可以包括在微处理器、存储器单元、和/或其他集成电路(IC)中。应该注意，图1的方法没有生产完整的半导体器件200。可以采用互补金属氧化物半导体(CMOS)技术加工来制造完整的半导体器件200。因此，应该理解，可以在图1的方法100之前、之中、以及之后提供其他工艺，以及其他一些工艺在这里仅进行简述。此外，为了更好地理解本发明，简化了图1至图8。例如，尽管附图示出了半导体器件200，但是应该理解，IC可以包括许多其他器件，该其他器件包括电阻器、电容器、电感器、熔丝等。
参考图1和图2，方法100从步骤102开始，在步骤102中，提供了包括表面202s的衬底202。在一个实施例中，衬底202包括晶体硅衬底(例如，晶圆)。在本实施例中，衬底202是指具有由(100)晶面形成的表面202s的(100)衬底。在可选实施例中，衬底202可以包括绝缘体上硅(SOI)结构。
衬底202可以进一步包括有源区204。有源区204可以根据设计要求包括各种掺杂结构。在一些实施例中，有源区204可以用p型掺杂剂或n型掺杂剂掺杂。例如，有源区204可以掺杂有p型掺杂剂，使用诸如硼或BF2的化学品来实施掺杂；n型掺杂剂，使用诸如磷或砷的化学品来实施掺杂；和/或其组合。有源区204可以用作配置用于N型金属氧化物半导体晶体管器件(称作NMOS)的区域和配置用于P型金属氧化物半导体晶体管器件(称作PMOS)的区域。
在一些实施例中，在衬底202中形成隔离结构206a和206b，从而隔离各个有源区204。例如，采用隔离技术如硅的局部氧化(LOCOS)或浅沟槽隔离(STI)来形成隔离结构206a和206b，从而限定并电隔离各个有源区204。在本实施例中，隔离结构206a和206b包括STI。隔离结构206a和206b可以包括：氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料、其他适当材料、和/或其组合。可以通过任何适当工艺形成隔离结构206a和206b，以及在本实施例中形成STI。作为一个实例，STI的形成可以包括：通过光刻工艺图案化半导体衬底202、在衬底202中蚀刻沟槽(例如，通过采用干蚀刻、湿蚀刻、和/或等离子体蚀刻工艺)、以及用介电材料填充沟槽(例如，通过采用化学汽相沉积工艺)。在一些实施例中，经填充的沟槽可以具有多层结构如填充有氮化硅或氧化硅的热氧化物衬层。
还参考图2，在至少一个实施例中，在衬底202的表面202s上方形成栅叠层210a、210b、以及210c。在一些实施例中，通过在衬底202上依次沉积并图案化栅极介电层212、栅电极层214、以及硬掩模层216形成栅叠层210a、210b、以及210c。
在一个实例中，栅极介电层212是薄膜，该薄膜包含氧化硅、氮化硅、氮氧化硅、高k电介质、其他适当介电材料、或者其组合。高k电介质包括金属氧化物。用于高k电介质的金属氧化物的实例包括：Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物，以及其混合物。在本实施例中，栅极介电层212是厚度处于约10埃至约30埃范围内的高k介电层。可以采用适当工艺如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、热氧化、UV-臭氧氧化、或者其组合形成栅极介电层212。栅极介电层212可以进一步包括界面层(未示出)，从而降低栅极介电层212和衬底202之间的损伤。界面层可以包括氧化硅。
然后，在栅极介电层212上形成栅电极层214。在一些实施例中，栅电极层214可以包括单层或多层结构。在本实施例中，栅电极层214可以包含多晶硅。此外，栅电极层214可以为具有相同或不同掺杂种类的掺杂多晶硅。在一个实施例中，栅电极层214具有在约30nm至约60nm范围内的厚度。可以采用工艺如低压化学汽相沉积(LPCVD)、等离子体增强化学汽相沉积(PECVD)、其他适当工艺、或者其组合形成栅电极层214。
接下来，在栅电极层214上方形成硬掩模层216，并且在硬掩模层216上形成经图案化的感光层(未示出)。将感光层的图案转印到硬掩模层216，然后转印到栅电极层214和栅极介电层212，从而在衬底202的表面202s上方形成栅叠层210a、210b、以及210c。在一些实施例中，硬掩模层216包含氧化硅。可选地，硬掩模层216可以包含氮化硅、氮氧化硅、和/或其他适当的介电材料，并且可以采用方法如CVD或PVD形成硬掩模层216。硬掩模层216具有在从约100埃至约800埃范围内的厚度。然后，通过干剥离工艺和/或湿剥离工艺来剥离感光层。
参考图1和图3，方法100继续到步骤104，在步骤104中，在栅叠层210a、210b、以及210c的相对侧壁的上面形成栅极间隔件218。在本实施例中，栅极间隔件218毗邻栅叠层210a、210b、以及210c的侧壁。在一些实施例中，栅极间隔件218可以包括单层或多层结构。在本实施例中，通过沉积工艺包括CVD、PVD、ALD、或者其他适当技术在栅叠层210a、210b、以及210c上方形成均厚间隔件材料层(未示出)。在一些实施例中，间隔件材料包括：氧化硅、氮化硅、氮氧化硅、其他适当材料、或者其组合。在一些实施例中，间隔件材料具有处于约5nm至约15nm范围内的厚度。然后，对间隔件材料实施各向异性蚀刻，以形成栅极间隔件218。
参考图1和图4，方法100继续到步骤106，在步骤106中，使衬底202凹进以在衬底202中形成凹进腔220、230、240、以及250。在一些实施例中，凹进腔220、230、240、以及250为源极和漏极(S/D)凹进腔。在图4的结构中，分别在栅叠层210a/隔离结构206a之间以及在栅叠层210c/隔离结构206b之间形成凹进腔220和250。分别在栅叠层210a/210b之间以及在210b/210c之间形成凹进腔230和240。
在本实施例中，使用各向同性干蚀刻工艺开始用于形成凹进腔220、230、240、以及250的工艺，然后实施各向异性湿蚀刻工艺或各向异性干蚀刻工艺。在一些实施例中，使用栅极间隔件218和隔离结构206a和206b作为硬掩模实施各向同性干蚀刻工艺，从而使未被栅极间隔件218或隔离结构206a和206b保护的衬底202的表面202s凹进，以在衬底202中形成初始凹进腔(未示出)。在实施例中，可以在约1mTorr至约1000mTorr的压力、约50W至约1000W的功率、约20V至约500V的偏压、约40℃至约60℃的温度条件下，使用HBr和/或Cl2作为蚀刻气体来实施各向同性干蚀刻工艺。此外，在所提供的实施例中，可以调谐各向同性干蚀刻工艺中所用的偏压，以允许更好地控制蚀刻方向，从而实现S/D凹进区域的期望轮廓。
在一些实施例中，然后，提供湿蚀刻工艺以扩大初始凹进腔，从而形成凹进腔220、230、240、以及250。在一些实施例中，使用包含水合四甲基铵(TMAH)等的化学品来实施湿蚀刻工艺。作为这种蚀刻工艺的结果，可以在每个凹进腔220、230、240、以及250中形成多个面。应该注意，具有或没有蚀刻停止件的周围环境能够影响所得的S/D凹进腔220、230、240、以及250部件。在湿蚀刻工艺期间，隔离结构206a可以用作蚀刻停止件，其用于限定在栅叠层210a和隔离结构206a之间的凹进腔220。在一些实施例中，栅叠层210a和隔离结构206a之间的凹进腔220具有相应的侧壁表面，该相应的侧壁表面通过底面220c、上侧壁面220a、下侧壁面220b和220d、以及隔离结构206a的侧壁的上部来限定。因此，这样形成的面220a和面220b彼此相交，并且共同限定凹进腔220中的楔形物220w，从而使得楔形凹进腔220在间隔件218右下方区域中朝向沟道区域延伸到衬底202中。在一些实施例中，位于相邻栅叠层210a和210b之间且没有蚀刻停止件的凹进腔230具有相应的侧壁表面，每一个相应的侧壁表面均通过底面230c、上侧壁面230a和230e、以及下侧壁面230b和230d来限定。因此，这样形成的面230d和面230e彼此相交并且共同限定凹进腔230中的楔形物230w，从而使得楔形凹进腔230在间隔件218的右下方区域中朝向沟道区域延伸到衬底202中。
在所示出的实例中，底面220c、230c由与衬底202的表面202s的晶面平行的(100)晶面形成。在所示出的实例中，上侧壁面220a、230a、以及230e和下侧壁面220b、220d、230b、以及230d由(111)晶面形成，并且上侧壁面220a和230a与底面220c和230c形成角θ1。此外，下侧壁面220b和230b与底面220c和230c形成比角θ1更小的角θ2。在图4的结构中，角θ1的取值范围为约90度至约150度，而角θ2的取值范围为约40度至约60度。在本实施例中，在面220a、230a、220b、以及230b由衬底202的(111)晶面形成的情况下，角θ1和角θ2分别取146度和56度的值。然而，应该注意，图4的结构不限于其中面220a、230a、220b、以及230b由(111)晶面形成的情况。
此外，在按照从衬底202的表面202s测量的深度D1处形成底面220c，而向下至深度D2处形成上侧壁面220a。在图4的结构中，深度D1在约20nm至约70nm的范围内，而深度D2在约5nm至约60nm的范围内。通过优化深度D2和在彼此相对的楔形物220w、230w之间的距离，可能有效限制应变材料222(在图5中示出)对沟道区域的单轴压缩应力，从而增强器件性能。
至此，工艺步骤已经提供了具有邻近栅叠层210a、210b、以及210c的凹进腔220、230、240、以及250的衬底202。参考图1和图5，方法100继续到步骤108，在步骤108中，采用工艺包括选择性外延生长(SEG)、交替沉积和蚀刻(CDE)、化学汽相沉积(CVD)技术(例如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延(MBE)、其他适当外延工艺，或者其组合在衬底202的凹进腔220、230、240、以及250中生长应变材料222。在一些实施例中，应变材料222具有与衬底202不同的晶格常数，从而对半导体器件200的沟道区域诱导应变或应力，并因而能够提高器件的载流子迁移率，从而增强器件性能。
在本实施例中，使用包括氢氟酸(HF)或其他适当溶液的化学品实施预清洗工艺，以清洗凹进腔220、230、240、以及250。然后，可以提供气体和/或液体前体以与衬底202的组分相互作用，从而形成应变材料222如硅锗(SiGe)，用于填充凹进腔220、230、240、以及250。在一个实施例中，在约600℃至750℃的温度下、以及在约10Torr至约80Torr的压力下，使用反应气体包括SiH2Cl2、HCl、GeH4、B2H6、H2、或者其组合实施用于形成包括SiGe的应变材料222的工艺。在一些实施例中，SiH2Cl2的质量流率与HCl的质量流率的比率在约0.45至0.55的范围内。在一个实施例中，因此，从衬底202中的凹进腔230的面230a、230b、230c、230d、以及230e向中心生长应变材料222。在另一实施例中，因此，从衬底202中的凹进腔220的面220a、220b、220c、以及220d向中心生长应变材料222。
在一些实施例中，应变材料222在不邻近隔离结构206a的凹进腔230中的生长主要是沿着面230c，并因此具有由(100)晶面形成的上表面222a。在本实施例中，因为由具有非晶结构的电介质形成的隔离结构206a不能提供生长外延材料的成核位置，所以应变材料222在邻近隔离结构206a的凹进腔220中的生长受到隔离结构206a的限制。在一些实施例中，应变材料222在凹进腔220中的生长趋于具有上表面222b，该上表面222b由具有稳定表面能量的(111)晶面形成。凹进腔220中的应变材料222具有在下侧壁面220b上方的形成的下侧壁表面222c，因此，该凹进腔220中的应变材料222由(111)晶面形成。在一些实施例中，下侧壁表面222c与上表面222b平行。在图5中可以看到，邻近隔离结构206a的应变材料222占用凹进腔220的一小部分。
在图5A中，为了更好地理解应变材料222在凹进腔220中的轮廓，放大半导体器件200。在本实施例中，凹进腔220中的应变材料222具有角部222d，该角部222d邻近栅叠层210a的边缘并且具有高于衬底202的表面202s的尖端。角部222d具有从表面202s至角部222d的尖端测量的高度D3。在一些实施例中，高度D3的范围处于约1nm和约10nm之间。如图5A中所示，具有垂直于衬底202的表面202s的法线L1；垂直于凹进腔220中的应变材料222的上表面222b的法线L2；以及法线L1和法线L2之间的角θ3。如上所述，衬底202例如是(100)衬底，该(100)衬底具有由(100)晶面形成的表面202s，以及上表面222b由(111)晶面形成。因此，在本实施例中，度θ3为约54度。
参考图1和图6，方法100继续到步骤110，在步骤110中，在应变材料222上方形成保护层224。保护层224可以用作保护层，从而在后续蚀刻工艺中防止下面的应变材料222被过度蚀刻。在本实施例中，通过外延生长工艺形成保护层224。位于不邻近隔离结构206a的凹进腔230中的应变材料222上方的保护层224具有厚度D4。在一些实施例中，厚度D4的范围在约1nm和约5nm之间。位于邻近隔离结构206a的凹进腔220中的应变材料222上方的保护层224具有接触隔离结构206a的侧壁224c以及厚度D5。在一些实施例中，厚度D4与厚度D5的比率的范围在约1和约3之间。在一些实施例中，位于凹进腔230中的应变材料222上方的保护层224可以沿着上表面222a的晶向生长，并且具有由(100)晶面形成的上表面224a。在一些实施例中，位于凹进腔220中的应变材料222上方的保护层224可以沿着上表面222b的晶向生长，并具有由(111)晶面形成的上表面224b。
在一些实施例中，保护层224包含与应变材料222不同的材料。在一些实施例中，保护层224是含硅层。在本实施例中，保护层224是硅。在一些实施例中，通过工艺包括选择性外延生长(SEG)、交替沉积和蚀刻(CDE)、化学汽相沉积(CVD)技术(例如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延(MBE)、其他适当外延工艺、或者其组合形成保护层224。在本实施例中，通过与形成应变材料222的工艺相同的工艺形成保护层224。在一些实施例中，在形成应变材料222之后，通过改变待实施的工艺条件在约700℃至约800℃的温度下、在约10Torr至约50Torr的压力下，以及使用含硅气体(例如，SiH2Cl2)作为反应气体继续形成保护层224。在可选实施例中，将B2H6和/或H2与含硅气体一起引入用于形成保护层224。
参考图1和图7，方法100继续到步骤112，在步骤112中，对半导体器件200实施蚀刻工艺。在一些实施例中，在用于形成保护层224的装置中(例如，CVD装置)中原位实施蚀刻工艺，由此，在形成保护层224的步骤和实施蚀刻工艺的步骤之间没有破坏真空。在可选实施例中，省略了保护层224并且在用于形成应变材料222的装置中原位实施蚀刻工艺。在本实施例中，通过在保护层224和应变材料222上方引入蚀刻气体而不提供电源或生成等离子体来实施蚀刻工艺。在实施例中，蚀刻气体为含氯气体，如Cl2和/或HCl。在可选实施例中，使用蚀刻气体和载气(例如，H2和/或N2)来实施蚀刻工艺。在本实施例中，蚀刻气体的流速处于约50sccm和约300sccm之间的范围内，以及载气的流速处于约3slm和约4slm(每分钟标准立升)之间的范围内。
在一些实施例中，在蚀刻工艺中去除保护层224，从而暴露下面的应变材料222。接下来，在实施例中，通过再分布应变材料222的至少一部分的角部222d使其位于凹进腔220中，在凹进腔220中形成经处理的应变材料222′。再分布可以增加凹进腔220中的应变材料222的量，因此，制造大容量应变结构，用于增强载流子迁移率并且提升半导体器件200的器件性能。在可选实施例中，再分布位于衬底202的表面202s上方的角部222d，以使其完全位于凹进腔220中，因此，所有的经处理的应变材料222′都在凹进腔220内。同时，对位于凹进腔230、240中的应变材料222不实施再分布工艺。
在一个实施例中，由于降低角部222d中的尖端的高表面能量导致该再分布。在可选实施例中，由于蚀刻工艺中的回流工艺导致该再分布。在蚀刻工艺以后，将凹进腔220中的应变材料222的最初上表面222b转变成经处理的上表面222b′。在一些实施例中，经处理的上表面222b′具有偏离最初的(111)晶面的转变晶面，因此，经处理的应变材料222′的下侧壁表面222c与经处理的上表面222b′不平行。在本实施例中，经处理的上表面222b′具有(311)晶面。在图7A中，为了更好地理解经处理的应变材料222′的轮廓，放大了半导体器件200。如图7A中所示，法线L1与衬底202的表面202s垂直，法线L2′与凹进腔220中的经处理的应变材料222′的经处理的上表面222b′垂直，并且在法线L1和法线L2′之间存在角θ4。在一个实施例中，角θ4小于角θ3。在另一实施例中，角θ4为约25至35度。
参考图1和图8，方法100继续到步骤114，在步骤114中，在凹进腔220、250中的经处理的应变材料222′上方以及凹进腔230、240中的应变材料222上方形成接触部件226。在本实施例中，通过与用于形成应变材料222或保护层224的工艺相同的工艺形成接触部件226。接触部件226可以在保护层224和随后形成的硅化物结构之间提供低接触电阻。在至少一个实施例中，接触部件226具有处于约150埃至约200埃范围内的厚度。在一些实施例中，接触部件226包含与保护层224的材料相同的材料。在可选实施例中，接触部件226包括与应变材料222的材料相同的材料。
应该理解，半导体器件200可以经历其他CMOS工艺来形成各种部件，如接触件/通孔、互连金属层、介电层、钝化层等。在一些实施例中，栅叠层210a、210b、以及210c可以是伪栅叠层。因此，CMOS工艺进一步包括“后栅极”工艺，用金属栅电极替换多晶硅栅电极来改善器件性能。在一个实施例中，金属栅电极可以包括金属，如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi；其他适当的导电材料；或者其组合。已经观察到，改进的应变结构在半导体器件的沟道区中提供给定量的应变，从而增强器件性能。
上面所讨论的本发明的各个实施例提供了优于传统方法的优点，应该理解，没有特定优点是所有实施例所必需的，并且不同实施例可以提供不同优点。这些优点之一是：可以增加邻近隔离结构的S/D凹进腔中的应变材料的下部，从而增强载流子迁移率并且提升器件性能。另一个优点是可以防止由于随后在应变材料的下部上方形成硅化物而导致的器件不稳定和/或器件故障的可能性。
在一个实施例中，用于制造半导体器件的方法包括：提供具有表面的衬底；在衬底中形成隔离部件；在衬底的表面上方形成栅叠层；在衬底中形成凹进腔；在凹进腔中形成外延(epi)材料，其中，外延材料具有位于凹进腔上方的角部；以及实施蚀刻工艺以再分布至少一部分角部使其位于凹进腔中。
在另一个实施例中，用于制造半导体器件的方法包括：在衬底中形成隔离部件；在衬底上方形成栅叠层；在衬底中形成源极/漏极(S/D)凹进腔，其中，将S/D凹进腔设置在栅叠层和隔离部件之间；在S/D凹进腔中形成外延材料，其中，外延材料具有第一晶面的上表面；以及使用含氯气体对S/D凹进腔中的外延材料实施再分布工艺，其中，在再分布之后，将第一晶面转变成第二晶面。
在又一个实施例中，用于制造半导体器件的方法包括：提供具有表面的衬底；在衬底中形成隔离部件；在衬底的表面上方形成栅叠层；在衬底中形成凹进腔，其中，将凹进腔水平地设置在栅叠层和隔离部件之间；在凹进腔中形成具有第一晶面的外延(epi)材料，其中，外延材料具有位于凹进腔上方的角部；在外延(epi)材料上方形成保护层；实施蚀刻工艺，以去除保护层并再分布外延(epi)材料以去除至少一部分角部使其位于凹进腔中，其中，再分布的外延(epi)材料具有第二晶面，该第二晶面与第一晶面不同；以及在再分布的外延(epi)材料上方形成接触部件。
虽然通过实例和根据优选的实施例描述了本发明，但是应理解本发明不限于所公开的实施例。相反地，本发明意图涵盖各种改进和相似的布置(对本领域的技术人员来说是显而易见的)。因此，所附权利要求的范围应与最广泛的解释一致以涵盖所有这些改进和相似的布置。

Claims (10)

1.一种用于制造半导体器件的方法，包括：
提供具有表面的衬底；
在所述衬底中形成隔离部件；
在所述衬底的所述表面上方形成栅叠层；
在所述衬底中形成凹进腔，其中，将所述凹进腔水平地设置在所述栅叠层和所述隔离部件之间；
在所述凹进腔中形成外延(epi)材料，其中，所述外延材料具有位于所述凹进腔上方的角部；以及
实施蚀刻工艺以再分布至少一部分所述角部使其位于所述凹进腔中。
2.根据权利要求1所述的方法，进一步包括：在蚀刻步骤之前，在所述外延材料上方形成保护层，其中，所述保护层是通过外延生长工艺形成的Si。
3.根据权利要求2所述的方法，其中，在形成所述保护层之后，原位实施蚀刻步骤。
4.根据权利要求1所述的方法，其中，使用含氯气体和载气实施蚀刻步骤，所述含氯气体是Cl2和/或HCl，以及所述载气是H2和/或N2。
5.根据权利要求1所述的方法，进一步包括：
在蚀刻步骤之后，在所述外延材料上方形成接触部件。
6.根据权利要求1所述的方法，其中，所述外延材料在蚀刻步骤之前包含(111)晶面而在蚀刻步骤之后包含(311)晶面。
7.根据权利要求1所述的方法，其中，所述角部具有尖端高度，所述尖端高度处于约1nm和约10nm之间的范围内。
8.根据权利要求1所述的方法，其中，在蚀刻步骤之前，在所述衬底表面的法线和所述外延材料平面的法线之间具有第一角度，而在蚀刻步骤以后，在所述衬底表面的法线和所述外延材料平面的法线之间具有第二角度，其中，所述第二角度小于所述第一角度。
9.一种制造半导体器件的方法，包括：
在衬底中形成隔离部件；
在所述衬底上方形成栅叠层；
在所述衬底中形成源极/漏极(S/D)凹进腔，其中，将所述S/D凹进腔设置在所述栅叠层和所述隔离部件之间；
在所述S/D凹进腔中形成外延(epi)材料，其中，所述外延材料具有上表面，所述上表面具有第一晶面；以及
使用含氯气体对所述S/D凹进腔中的所述外延材料实施再分布工艺，其中，在再分布之后，将所述第一晶面转变成第二晶面。
10.一种制造半导体器件的方法，包括：
提供具有表面的衬底；
在所述衬底中形成隔离部件；
在所述衬底的所述表面上方形成栅叠层；
在所述衬底中形成凹进腔，其中，将所述凹进腔水平地设置在所述栅叠层和所述隔离部件之间；
在所述凹进腔中形成具有第一晶面的外延(epi)材料，其中，所述外延材料具有位于所述凹进腔上方的角部；
在所述外延(epi)材料上方形成保护层；
实施蚀刻工艺，以去除所述保护层并再分布所述外延(epi)材料以去除至少一部分所述角部使其位于所述凹进腔中，其中，所述再分布的外延(epi)材料具有第二晶面，所述第二晶面与所述第一晶面不同；以及
在所述再分布的外延(epi)材料上方形成接触部件。
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