CN102593130B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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Abstract
一种半导体器件,具有:基板,包括主表面;栅极叠层,包括侧壁,位于基板上方;隔离件,位于基板上方,邻接栅极叠层的侧壁,其中,隔离件包括底面,底面具有外点,外点与栅极叠层的距离最远;隔离结构,位于基板中,栅极叠层的一侧,隔离结构的外边缘最靠近隔离件;以及应变材料,位于隔离件和隔离结构之间的基板的主表面下方,包括上部和下部,上部和下部通过过渡平面间隔开,过渡平面与基板的主表面之间的夹角为锐角。本发明还涉及一种半导体器件的制造方法。
Description
技术领域
本发明涉及集成电路制造,更具体地来说,涉及带有应变结构的半导体器件。
背景技术
当诸如金属氧化物半导体场效应晶体管(MOSFET)的半导体器件按比例减小到各个技术节点时,高k栅极介电层和金属栅电极层集成到MOSFET的栅极叠层中,从而通过减小器件尺寸来改进器件性能。另外,通过选择性地生长硅锗(SiGe),可以利用MOSFET的源极和漏极(S/D)凹腔中的应变结构来提高载流子迁移率。
然而,在互补金属氧化物半导体(CMOS)制造中,实现上述部件和工艺有一定困难。随着栅极长度和器件之间间隔的减小,上述问题更加严重。例如,因为应变材料无法将给定量的应变传递到半导体器件的沟道区域中,所以难以提高半导体器件的载流子迁移率,从而增加了器件不稳定和/或器件损坏的可能性。
因此,亟需一种在半导体器件中形成应变结构的改进方法。
发明内容
为了解决现有技术中所存在的问题,根据本发明的一个方面,提供了一种半导体器件,包括:基板,包括主表面;栅极叠层,包括侧壁,所述侧壁位于所述基板上方;隔离件,位于所述基板上方,邻接所述栅极叠层的所述侧壁,其中,所述隔离件包括底面,所述底面具有外点,所述外点与所述栅极叠层的距离最远;隔离结构,位于所述基板中,所述栅极叠层的一侧,所述隔离结构的外边缘最靠近所述隔离件;以及应变材料,位于所述隔离件和所述隔离结构之间的所述基板的所述主表面下方,所述应变材料包括上部和下部,所述上部和所述下部通过过渡平面间隔开,所述过渡平面与所述基板的所述主表面之间的夹角为锐角,其中,所述过渡平面与所述外点相交并且向下延伸到所述隔离结构的所述外边缘,其中,所述上部包括第一面,所述第一面邻近所述隔离件,其中,所述第一面与所述基板的所述主表面所夹的锐角小于所述过渡平面与所述基板的所述主表面所夹的锐角。
在该半导体器件中,所述应变材料包含SiGe,并且按照原子百分率,所述SiGe中的Ge浓度处于大约10%到40%的范围内。
在该半导体器件中,所述应变材料的最大厚度处于大约20nm到300nm的范围内;或者所述过渡平面通过所述应变材料的(111)晶面限定;或者所述第一面通过所述应变材料的(311)晶面限定。
在该半导体器件中,所述上部进一步包括:第二面,所述第二面通过所述第一面与所述隔离件间隔开,其中,所述第一面与所述基板的所述主表面所夹的锐角小于所述第二面与所述基板的所述主表面所夹的锐角,其中,所述第一面和所述第二面是平坦表面。
在该半导体器件中,所述下部的横截面积大于所述上部的横截面积;或者所述下部的横截面积小于所述上部的横截面积。
该半导体器件进一步包括:附加应变材料,通过所述栅极叠层与所述应变材料间隔开,其中,所述附加应变材料的横截面积大于所述应变材料的横截面积,其中,所述附加应变材料位于所述基板的所述主表面下方,或者所述附加应变材料的至少一部分位于所述基板的所述主表面上方。
根据本发明的另一方面,提供一种用于制造半导体器件的方法,包括:提供基板,所述基板包括主表面;在所述基板的所述主表面上方形成栅极叠层;使所述基板凹陷,以形成源极和漏极凹腔,所述源极和漏极凹腔邻近所述基板中的所述栅极叠层;以及利用LPCVD工艺在所述基板中的所述源极和漏极凹腔中选择性地生长应变材料,其中,所述LPCVD工艺在以下条件下实施:温度为大约660℃到700℃,压力为大约13Torr到50Torr,使用SiH2Cl2、HCl、GeH4、B2H6、和H2作为反应气体。
在该方法中,所述栅极叠层包括多晶硅栅电极或者金属栅电极中的至少一种;或者在所述应变材料的顶面生长到所述基板的所述主表面上方之前,所述应变材料的生长终止。
在该方法中,所述应变材料的生长继续进行,直到所述应变材料的顶面延伸到在所述源极和漏极凹腔之一中的所述基板的所述主表面上方;或者所述SiH2Cl2的质量流率与所述HCl的质量流率的比率处于大约0.8到1.5的范围内。
在该方法中,所述SiH2Cl2的质量流率与所述GeH4的质量流率的比率处于大约10到50的范围内;或者所述应变材料包含SiGe,按照原子百分率,所述SiGe中的Ge浓度处于大约10%到40%的范围内。
附图说明
根据以下结合附图的详细描述可以最好地理解本发明。需要强调的是,根据工业中的标准实践,各种不同元件没有按比例绘制。实际上,为了使论述清晰,可以任意增加或减小各种元件的尺寸。
图1是示出了根据本发明的各个方面的制造包含有应变结构的半导体器件的方法的流程图;以及
图2-图5B示出了根据本发明的各个方面的各个制造阶段的半导体器件的应变结构的横截面示意图。
具体实施方式
应该理解,以下公开内容提供了许多用于实施所公开的不同特征的不同实施例或实例。以下描述组件和配置的具体实例以简化本发明。当然,这仅仅是实例,并不是用于限制本发明。例如,在以下的本发明中所描述的将一个部件形成在另一部件上方或者之上,可以包括第一部件和第二部件被形成为直接接触的实施例,还可以包括在第一部件和第二部件之间形成有附加部件的实施例,比如,部件不直接接触。另外,本发明的内容可以在不同实例中重复使用参考标号和/或字母。这种重复是为了简化和清晰的目的,其本身并没有表示各个实施例和/或所讨论配置之间的关系。
图1是根据本发明的各个方面的用来制造包含有应变结构220(如图5A和图5B中所示)的半导体器件200的方法的流程图。图2-图5B示出了根据图1的方法100的实施例的各个制造阶段的半导体器件200的应变结构220的横截面示意图。半导体器件200可以包含在微处理器、存储单元、和/或其他集成电路(IC)中。需要注意的是,图1的方法并没有制造出完整的半导体器件200。完整的半导体器件200可以利用互补金属氧化物半导体(CMOS)技术工艺制造。因此,可以理解,可以在图1的方法100之前、之中、和之后提供附加工艺,并且在本文中对这些其他工艺可以只进行简要描述。同样,为了更好地理解本发明的发明构思,对于图1到图5B进行了简化。例如,尽管附图示出了半导体器件200,但是可以理解,IC可以包含多个其他器件,包括电阻器、电容器、电感器、熔丝等等。
参考图1和图2,方法100开始于步骤102,其中,提供基板202,该基板202包括主表面202s。在一个实施例中,基板202包括晶体硅基板(例如,晶圆)。而且,基板202还包括外延层(epi layer)和/或绝缘体上硅(SOI)结构,为了增强性能,可以使该外延层产生应变。
基板202可以进一步包含有源区域204。取决于本领域所公知的设计需求,该有源区域204可以包括各种掺杂配置。在一些实施例中,有源区域204可以掺杂有p型掺杂剂或者n型掺杂剂。例如,有源区域204可以掺杂有诸如硼或者BF2的p型掺杂剂;诸如磷或者砷的n型掺杂剂;和/或上述的组合。有源区域204可以配置为N型金属氧化物半导体晶体管器件(称为NMOS)的区域,还可以配置为P型金属氧化物半导体晶体管器件(称为PMOS)的区域。
隔离结构206a、206b可以形成在基板202上,用来将各个有源区域204隔离。隔离结构206a、206b可以利用隔离技术,比如硅的局部氧化(LOCOS)或者浅沟槽隔离(STI),从而限定并且电绝缘各个有源区域204。在本实施例中,隔离结构206a、206b包括STI。隔离结构206a、206b可以包含氧化硅、氮化硅、氮氧化硅、氟掺杂硅玻璃(FSG)、低K介电材料、其他适当材料、和/或上述的组合。隔离结构206a、206b以及本实施例中的STI都可以通过任意适当工艺形成。例如,STI的形成可以包括:通过传统光刻工艺图案化半导体基板202,在基板202中蚀刻沟槽(例如,通过使用干式蚀刻工艺、湿式蚀刻工艺、和/或等离子蚀刻工艺),以及用介电材料填充沟槽(例如,通过使用化学汽相沉积工艺)。在一些实施例中,所填充的沟槽可以具有多层结构,比如由氮化硅或者氧化硅填充的热氧化物衬层。基板202中的隔离结构206a具有外边缘206e。
再次参考图1和图2,方法100继续到步骤104,其中,通过顺序对基板202上的栅极介电层212和栅电极层214实施沉积和图案化,从而形成栅极叠层210a。可以使用任意适当工艺,包括本文所描述的工艺,来形成栅极叠层210a。
在一个实例中,在基板202上形成覆盖(blanket)栅极介电层212。在一些实施例中,栅极介电层212可以是包含氧化硅、氮化硅、氮氧化硅、高k电介质、和/或其他适当介电材料的薄膜。高k电介质包括金属氧化物。用作高k电介质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物及上述的混合物。在本实施例中,栅极介电层212是厚度在大约10埃到30埃的范围内的高k介电层。栅极介电层212可以利用适当工艺形成,比如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、热氧化、UV-臭氧氧化、或者上述的组合工艺。栅极介电层212可以进一步包括界面层(未示出),从而减小栅极介电层212和基板202之间的损坏。该界面层可以包含氧化硅。
然后,在覆盖栅极介电层212上形成覆盖栅电极层214。在一些实施例中,栅电极层214可以包括单层结构或者多层结构。在本实施例中,栅电极层214可以包含多晶硅。而且,栅电极层214可以是具有相同掺杂质或者不同掺杂质的掺杂多晶硅。在一个实施例中,栅电极层214的厚度处于大约30nm到大约60nm的范围内。栅电极层214可以利用适当工艺形成,比如低压化学汽相淀积(LPCVD)或者等离子体增强型化学汽相淀积(PECVD)、或者上述的组合工艺。
接下来,在覆盖栅电极层214上方形成硬掩模层216,并且在该硬掩模层216上形成图案化的感光层(未示出)。感光层的图案转印到硬掩模层216,然后转印到栅电极层214和栅极介电层212,从而在基板202的主表面202s上方形成栅极叠层210a、210b、和210c。硬掩模层216包含氧化硅。可选地,硬掩模层216可选地包含氮化硅、氮氧化硅、和/或其他适当介电材料,并且可以利用诸如CVD或者PVD的方法形成该硬掩模层216。硬掩模层216的厚度处于大约到的范围内。在此后的步骤中将感光层去除。
然后,在栅极叠层210a、栅极叠层210b和栅极叠层210c的周围都沉积共型隔离件材料(conformal spacer material)。在本实施例中,该隔离件材料可以包含氧化硅、氮化硅、氮氧化硅、或者其他适当材料。该隔离件材料可以包括单层结构或者多层结构。隔离件材料的覆盖层可以通过CVD、PVD、ALD、或者其他适当技术形成。然后,在隔离件材料上实施各向异性蚀刻,从而形成隔离件阵列218。在本实施例中,隔离件阵列218邻接基板202上方的栅极叠层210a的侧壁210s、210w,该隔离件阵列218可以称作一对隔离件218a、218b。隔离件218a包含底面218s,该底面218s具有外点218p,该外点218p是底面218s上距离栅极叠层210a最远的点。该介电层的厚度在大约5nm到15nm的范围内。而且,栅极叠层210a的一侧上的基板202中的隔离结构206a具有外边缘206e,该外边缘206e最接近隔离件218a。
参考图1和图3,方法100继续到步骤106,其中,基板202凹陷,从而形成源极和漏极(S/D)凹腔220、230、240、和250,该S/D凹腔220、230、240、和250邻近基板202中的栅极叠层210a、210b、和210c。在图3的结构中,S/D凹腔220、230、240、和250可以利用以下步骤形成:先实施偏置干式蚀刻工艺,然后实施无偏置湿式蚀刻工艺或者无偏置干式蚀刻工艺。
在本实施例中,基板202是所谓(001)基板,具有主表面202s。利用隔离件阵列218和隔离结构206a、206b作为硬掩模,实施偏置干式蚀刻工艺,从而在基板202的主表面202s上没有保护或者暴露出的位置上形成凹部,进而形成源极和漏极(S/D)凹腔(未示出),其中,该S/D凹腔区域可以包括底面和侧壁,该底面平行于基板202的主表面202s,该侧壁垂直于基板202的主表面202s。在一个实施例中,可以在以下条件下实施偏置干式蚀刻工艺:压力为大约1mTorr到1000mTorr,功率为大约50W到1000W、偏置电压为大约20V到500V,温度为大约40℃到60℃,使用HBr和/或Cl2作为蚀刻气体。另外,在所提供的实施例中,可以调整在偏置干式蚀刻工艺中所使用的偏置电压,从而能够更好地控制蚀刻方向,进而获得所希望得到的S/D凹腔区域的轮廓。
然后,利用四甲基氢氧化铵(TMAH)在源极和漏极(S/D)凹腔区域实施湿式蚀刻工艺,S/D凹陷区域的垂直侧壁变为由基板202的(111)晶面形成的斜面,从而形成S/D凹腔220、230、240、和250。
上述蚀刻工艺的结果是,可以在每个S/D凹腔220、230、240、和250中都形成多个由(111)晶面形成的面。应该注意,在带有或者不带有蚀刻停止情况下的周边环境可能会影响S/D凹腔220、230、240、和250所具有的特征。在一个实例中,由于隔离结构206a起到了蚀刻停止的作用,因此,栅极叠层210a和隔离结构206a之间的S/D凹腔220的相应侧壁表面由底面220c和面220a、220b、和220d限定。因此,面220a和面220b相交,并且一起限定出S/D凹腔220中的楔形220w,从而使得基板202中的楔形形状的S/D凹腔220朝着沟道区域侵入到隔离件218a的正下方区域中。在另一实例中,在不具有蚀刻停止情况下的相邻栅极叠层210a、210b之间的S/D凹腔230具有由底面230c和面210a、210b、230d、和230e限定的相应侧壁表面。因此,面230d和面230e相交,并且一起在S/D凹腔230中限定出楔形230w,从而使得基板202中的楔形形状的S/D凹腔230朝着沟道区域侵入到隔离件218a的正下方区域中。
在所示实例中,底面220c由基板202的(100)晶面形成,该(100)晶面平行于基板202的主表面202s,面220a与底面220c之间形成角度θ1。而且,面220b与底面220c所形成的角度θ2小于角度θ1。在图3的结构中,角度θ1在90度-150度的范围内,角度θ2在40度-60度的范围内。还是在这种情况下,面220a与基板202的(111)晶面所形成的角和面220b与基板202的(111)晶面所形成的角分别为146度和56度。然而,应该注意,图3的结构并不限于面220a、220b通过(111)晶面而形成的这种情况。
而且,底面220c与基板202的主表面202s的距离为深度D1,面220a与基板202的主表面202s的距离为深度D2。在图3的结构中,深度D1在20nm到70nm的范围内,深度D2在5nm到60nm的范围内。通过优化深度D2和相对的楔形220w、230w之间的距离,可以将应变材料222(如图5A和图5B中所示)的单轴压应力有效地限制到沟道区域,从而增强了器件性能。
工艺步骤进行到这一步已经形成了具有S/D凹腔220、230、240、250的基板202,该S/D凹腔220、230、240、250邻近栅极叠层210a、210b、和210c。参考图1、图4、图5A和图5B,方法100继续到步骤108,其中,利用LPCVD工艺,应变材料222在基板202中的S/D凹腔220、230、240、250中选择性地生长。因为应变材料222的晶格常数与基板202不同,所以半导体器件200的沟道区域发生应变或者受到应力,从而激活器件的载流子迁移率,并且提高器件性能。
在本实施例中,可以利用氢氟酸(HF)或者其他适当溶液实施预清洁工艺,来清洁S/D凹腔220、230、240、250。然后,通过LPCVD工艺选择性地生长诸如硅锗(SiGe)的应变材料222的下部222l,从而部分地填充基板202中的S/D凹腔220、230、240、250。在一个实施例中,在以下条件下实施LPCVD工艺:温度为大约400℃到800℃,压力为大约1Torr到15Torr,使用SiH2Cl2、HCl、GeH4、B2H6、和H2作为反应气体,其中,SiH2Cl2的质量流率与HCl的质量流率的比率处于大约0.45到0.55的范围内。在热力学上,应变材料222的密排(111)晶面的生长率远远大于应变材料222的其他晶面的生长率。在一个实施例中,应变材料222因此从基板202中S/D凹腔230的面230a、230b、230d、和230e生长到基板202中S/D凹腔230的中部。在另一实施例中,应变材料222因此从基板202中S/D凹腔220的面220a、220b、和220b生长到基板202中S/D凹腔220的中部。
基本上,具有非晶结构的介电材料无法提供均相成核区域来生长外延材料。在本实施例中,隔离件218a和隔离结构206a都是介电材料,从而当应变材料222的(111)晶面与隔离件218a的底面218s处的外点218p相交时,S/D凹腔220中的应变材料222的生长会终止,并且向下延伸到隔离结构206a。然而,如果LPCVD工艺继续进行,则会同时发生S/D凹腔230中的应变材料222的进一步生长。
在图4中可以看出,S/D凹腔220中的应变材料222的下部222l占据了S/D凹腔220的较小部分,从而无法将给定量的应变传递到半导体器件200的沟道区域中,从而增加了器件不稳定和/或器件损坏的可能性。根据本发明的各个方面,为了使得S/D凹腔220中的应变材料222进一步生长,将在下文中提出一种克服S/D凹腔220中应变材料222的生长能量势垒的方法。
在本实施例中,LPCVD工艺改变为在以下条件下实施:温度为大约660℃到700℃,压力为大约13Torr到15Torr,使用SiH2Cl2、HCl、GeH4、B2H6、和H2作为反应气体,从而形成了应变材料222的上部222u,其中,SiH2Cl2的质量流率与GeH4的质量流率的比率处于大约10到50的范围内,SiH2Cl2的质量流率与HCl的质量流率的比率处于大约0.8到1.5的范围内。因为在本步骤中HCl质量流率较小,使得在选择性外延工艺期间的蚀刻化学品较少,从而使得应变材料222的上部222u的各向同性生长较为容易,所以很有可能出现除了密排(111)晶面的其他晶面形成上部222u(如图5A中所示)。在另一实施例中,应变材料222的下部222l的生长步骤可以由本生长步骤替换。换言之,应变材料222可以利用一种生长步骤形成。因此,这里所公开的制造半导体器件200的方法可以制造出大体积应变结构,从而提高了载流子迁移率,并且改进了器件性能。
总之,置于隔离件218a和隔离结构206a之间的基板202的主表面202s下方的应变材料222包括上部222u和下部222l,该上部222u和下部222l通过过渡平面222p间隔开,该过渡平面222p与基板202的主表面202s之间的角度为锐角θ3,其中,过渡平面222p与外点218p相交,并且向下延伸到隔离结构206a的外边缘206e,其中,上部222u包括第一面222a,该第一面222a邻近隔离件218a(如图5A中所示)。在一个实施例中,锐角θ3在50度-60度的范围内。在另一实施例中,锐角θ3在53度-59度的范围内。在本实施例中,锐角θ3是56度,过渡平面222p通过应变材料222的(111)晶面限定。
可以看出,第一面222a与基板202的主表面202s所夹的锐角θ4小于过渡平面222p与基板202的主表面202s所夹的锐角θ3。在一个实施例中,第一面222a通过应变材料222的(311)晶面限定。在本实施例中,上部222u进一步包括第二面222b,该第二面222b通过第一面222a与隔离件218a间隔开,其中,第一面与基板202的主表面202s所夹的锐角θ4小于第二面222b与基板202的主表面202s所夹的锐角θ5。在一个实施例中,第二面222b通过应变材料222的(111)晶面限定。而且,第一面222a和第二面222b都是平坦表面。然而,应该注意,图5A的结构并不限于上述情况,还可以由于上部222u的各向同性生长而形成应变材料222的其它面。
而且,下部222l的横截面积大于上部222u的横截面积。在一些实施例中,这样足以将给定量的应变传递到半导体器件200的沟道区域中。因此,所公开的制造半导体器件200的方法所制造出的应变结构的载流子迁移率得到了提高,器件性能也得到了改进。
在一些实施例中,应变材料222的上部222u进一步生长,直到下部222l的横截面积小于上部222u的横截面积(图5B中所示),从而将给定量的应变传递到半导体器件200的沟道区域中。
在一些实施例中,S/D凹腔230中的附加应变材料232通过栅极叠层210a与S/D凹腔220中的应变材料222间隔开,该附加应变材料232的选择性生长不被隔离结构206a限制,从而附加应变材料232的生长率大于S/D凹腔220中应变材料222的生长率。因为材料222、材料232同时生长,所以附加应变材料232的横截面积大于应变材料222的横截面积。
在一个实施例中,当材料232在基板202的主表面202a(未示出)下方距离在大约10nm到100nm的范围内时,附加应变材料232的选择性生长终止。在另一实施例中,附加应变材料232的选择性生长继续进行,直到材料232延伸到基板202的主表面202a上方距离在大约10nm到100nm的范围内。附加应变材料232的进一步生长可能会占据形成在材料232上的低电阻硅化物所需的空间,从而增加了邻近器件之间发生短路的可能性。从而,由于附加应变材料232的生长被限制,因此,图5B所示的结构上的应变材料222被限制在隔离件218a和隔离结构206a之间的基板202的主表面202s下方。
总之,隔离件218a和隔离结构206a之间的基板202的主表面202s下方的应变材料222包括上部222u和下部222l,该上部222u和下部222l通过过渡平面222p间隔开,该过渡平面222p与基板202的主表面202s之间的夹角为锐角θ3,其中,过渡平面222p与外点218p相交,并且向下延伸到隔离结构206a的外边缘206e,其中,上部222u包括第一面222a,该第一面222a邻近隔离件218a(如图5B中所示)。在一个实施例中,锐角θ3在50度-60度的范围内。在另一实施例中,锐角θ3在53度-59度的范围内。在本实施例中,锐角θ3是56度,过渡平面222p通过应变材料222的(111)晶面限定。
第一面222a与基板202的主表面202s所夹的锐角θ4小于过渡平面222p与基板202的主表面202s所夹的锐角θ3。在一个实施例中,第一面通过应变材料222的(311)晶面限定。在本实施例中,上部222u进一步包括第二面222b,该第二面222b通过第一面222a与隔离件218a间隔开,其中,第一面与基板202的主表面202s所夹的锐角θ4小于第二面222b与基板202的主表面202s所夹的锐角θ5。在一个实施例中,第二面222b通过应变材料222的(111)晶面限定。而且,第一面222a和第二面222b都是平坦表面。然而,应该注意,图5B所示的结构并不限于上述情况,还可以由于上部222u的各向同性生长而形成应变材料222的附加面。因此,所公开的制造半导体器件200的方法所制造出的应变结构的载流子迁移率得到了提高,器件性能也得到了改进。
而且,图5A和图5B所示的结构上的应变材料222的最大厚度222t处于大约20nm到300nm的范围内。应变材料222所包含的SiGe中按照原子百分率的Ge浓度处于大约10%到40%的范围内。
可以理解,可以对半导体器件200实施另外的CMOS工艺,从而形成各种元件,比如触点/通孔、互连金属层、介电层、钝化层等等。在一些实施例中,栅极叠层210a、210b、210c可以是伪栅极叠层。这样,CMOS工艺进一步包括“后栅极”工艺,从而用金属栅电极替换多晶硅栅电极,进而改进器件性能。在一个实施例中,金属栅电极所包含的金属可以是,比如,Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi、其他适当导电材料、或者上述的组合。可以看出,经过修改的应变结构将给定量的应变提供到半导体器件的沟道区域中,从而增强了器件性能。
在一个实施例中,一种半导体器件,包括:基板,包括主表面;栅极叠层,包括侧壁,位于基板上方;隔离件,位于基板上方,邻接栅极叠层的侧壁,其中,隔离件包括底面,底面具有外点,外点与栅极叠层的距离最远;隔离结构,位于基板中,栅极叠层的一侧,隔离结构的外边缘最靠近隔离件;以及应变材料,位于隔离件和隔离结构之间的基板的主表面下方,包括上部和下部,上部和下部通过过渡平面间隔开,过渡平面与基板的主表面之间的夹角为锐角,其中,过渡平面与外点相交,并且向下延伸到隔离结构的外边缘,其中,上部包括第一面,第一面邻近隔离件,其中,第一面与基板的主表面所夹的锐角小于过渡平面与基板的主表面所夹的锐角。
在另一实施例中,一种半导体器件,包括:基板,包括主表面;栅极叠层,包括侧壁,位于基板上方;隔离件,位于基板上方,邻接栅极叠层的侧壁,其中,隔离件包括底面,底面具有外点,外点与栅极叠层的距离最远;隔离结构,位于基板中,栅极叠层的一侧,隔离结构的外边缘最靠近隔离件;应变材料,位于隔离件和隔离结构之间的基板的主表面下方,包括上部和下部,上部和下部通过过渡平面间隔开,过渡平面与基板的主表面之间的夹角为锐角,其中,过渡平面与外点相交,并且向下延伸到隔离结构的外边缘,其中,上部包括第一面,第一面邻近隔离件,其中,第一面与基板的主表面所夹的锐角小于过渡平面与基板的主表面所夹的锐角;以及附加应变材料,通过栅极叠层与应变材料间隔开,其中,附加应变材料的横截面积大于应变材料的横截面积。
在又一实施例中,一种用于制造半导体器件的方法,包括:提供基板,基板包括主表面;在基板的主表面上方形成栅极叠层;使基板凹陷,以形成源极和漏极凹腔,源极和漏极凹腔邻近基板中的栅极叠层;以及利用LPCVD工艺在基板中源极和漏极凹腔中选择性地生长应变材料,其中,LPCVD工艺在以下条件下实施:温度为大约660℃到700℃,压力位大约13Torr到50Torr,使用SiH2Cl2、HCl、GeH4、B2H6、和H2作为反应气体。
尽管通过实例,根据优选实施例描述了本发明,但是可以理解,本发明并不限于所公开的实施例。相反,本发明涵盖了各种修改和类似配置(对于本领域技术人员来说是显而易见的)。因此,附加权利要求的范围应该符合最广义的解释,从而包括所有这些修改和类似配置。
Claims (17)
1.一种半导体器件,包括:
基板,包括主表面;
栅极叠层,包括侧壁,所述侧壁位于所述基板上方;
隔离件,位于所述基板上方,邻接所述栅极叠层的所述侧壁,其中,所述隔离件包括底面,所述底面具有外点,所述外点与所述栅极叠层的距离最远;
隔离结构,位于所述基板中,所述栅极叠层的一侧,所述隔离结构的外边缘最靠近所述隔离件;
应变材料,位于所述隔离件和所述隔离结构之间的所述基板的所述主表面下方,所述应变材料包括上部和下部,所述上部和所述下部通过过渡平面间隔开,所述过渡平面与所述基板的所述主表面之间的夹角为锐角,其中,所述过渡平面与所述外点相交并且向下延伸到所述隔离结构的所述外边缘;以及
附加应变材料,通过所述栅极叠层与所述应变材料间隔开,其中,所述附加应变材料的至少一部分位于所述基板的所述主表面的上方,所述附加应变材料的横截面积大于所述应变材料的横截面积,
其中,所述上部包括第一面,所述第一面邻近所述隔离件,其中,所述第一面与所述基板的所述主表面所夹的锐角小于所述过渡平面与所述基板的所述主表面所夹的锐角。
2.根据权利要求1所述的半导体器件,其中,所述应变材料包含SiGe。
3.根据权利要求2所述的半导体器件,其中,按照原子百分率,所述SiGe中的Ge浓度处于10%到40%的范围内。
4.根据权利要求1所述的半导体器件,其中,所述应变材料的最大厚度处于20nm到300nm的范围内。
5.根据权利要求1所述的半导体器件,其中,所述过渡平面通过所述应变材料的(111)晶面限定。
6.根据权利要求1所述的半导体器件,其中,所述第一面通过所述应变材料的(311)晶面限定。
7.根据权利要求1所述的半导体器件,其中,所述上部进一步包括:第二面,所述第二面通过所述第一面与所述隔离件间隔开,其中,所述第一面与所述基板的所述主表面所夹的锐角小于所述第二面与所述基板的所述主表面所夹的锐角。
8.根据权利要求7所述的半导体器件,其中,所述第一面和所述第二面是平坦表面。
9.根据权利要求1所述的半导体器件,其中,所述下部的横截面积大于所述上部的横截面积。
10.根据权利要求1所述的半导体器件,其中,所述下部的横截面积小于所述上部的横截面积。
11.一种用于制造根据权利要求1至10中任一项所述的半导体器件的方法,包括:
提供基板,所述基板包括主表面;
在所述基板的所述主表面上方形成栅极叠层;
使所述基板凹陷,以形成源极和漏极凹腔,所述源极和漏极凹腔邻近所述基板中的所述栅极叠层;以及
利用LPCVD工艺在所述基板中的所述源极和漏极凹腔中选择性地生长应变材料,其中,所述LPCVD工艺在以下条件下实施:温度为660℃到700℃,压力为13Torr到50Torr,使用SiH2Cl2、HCl、GeH4、B2H6、和H2作为反应气体。
12.根据权利要求11所述的方法,其中,所述栅极叠层包括多晶硅栅电极或者金属栅电极中的至少一种。
13.根据权利要求11所述的方法,其中,在所述应变材料的顶面生长到所述基板的所述主表面上方之前,所述应变材料的生长终止。
14.根据权利要求11所述的方法,其中,所述应变材料的生长继续进行,直到所述应变材料的顶面延伸到在所述源极和漏极凹腔之一中的所述基板的所述主表面上方。
15.根据权利要求11所述的方法,其中,所述SiH2Cl2的质量流率与所述HCl的质量流率的比率处于0.8到1.5的范围内。
16.根据权利要求11所述的方法,其中,所述SiH2Cl2的质量流率与所述GeH4的质量流率的比率处于10到50的范围内。
17.根据权利要求11所述的方法,其中,所述应变材料包含SiGe,按照原子百分率,所述SiGe中的Ge浓度处于10%到40%的范围内。
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