CN103035574B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103035574B
CN103035574B CN201210160901.8A CN201210160901A CN103035574B CN 103035574 B CN103035574 B CN 103035574B CN 201210160901 A CN201210160901 A CN 201210160901A CN 103035574 B CN103035574 B CN 103035574B
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substrate
crystal face
producing
epitaxial
recess cavity
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CN103035574A (zh
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舒丽丽
蔡邦彦
李资良
李启弘
李彦儒
游明华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

公开了用于制造半导体器件的方法。应变材料形成在衬底的腔中并且与衬底中的隔离结构相邻。应变材料具有位于衬底表面上方的角部。所公开的方法提供了用于利用衬底腔中的增加部分形成与隔离结构相邻的应变材料的改进方法，以增强载流子迁移率并提升器件性能。通过提供处理以重新分布腔中角部的至少一部分来实现改进的形成方法。本发明还提供了半导体器件及其制造方法。

Description

半导体器件及其制造方法
技术领域
本发明涉及集成电路制造，更具体地，涉及具有应变结构的半导体器件。
背景技术
当诸如金属氧化物半导体场效应晶体管(MOSFET)的半导体器件通过各种技术节点尺寸缩小时，高k栅极介电层和金属栅电极层被结合到MOSFET的栅叠层中以利用减小的部件尺寸提高器件性能。此外，利用选择性生长硅锗(SiGe)的MOSFET的源极和漏极(S/D)凹进腔中的应变结构可用于增强载流子迁移率。
然而，在互补金属氧化物半导体(CMOS)制造中存在实施这种部件和工艺的挑战。随着栅极长度和器件之间的间隔的减小，这些问题更加恶化。例如，对于半导体器件来说难以实现增强的载流子迁移率，因为应变材料不能将给定量的应变传送到半导体器件的沟道区域中，从而增加了器件不稳定和/或器件故障的可能性。
发明内容
为了解决现在技术中所存在的缺陷，根据本发明的一方面，提供了一种用于制造半导体器件的方法，包括：在衬底中形成隔离部件；在所述衬底的上方形成栅叠层；在所述衬底中形成凹进腔，其中，所述凹进腔水平地定位在所述栅叠层和所述隔离部件之间；在所述凹进腔中形成外延(epi)材料，其中，所述外延材料具有位于所述凹进腔上方的角部；以及提供处理以重新分布所述凹进腔中的所述角部的至少一部分。
该方法还包括：在处理步骤之前，在所述外延材料的上方形成保护层。
在该方法中，所述保护层是通过外延生长工艺形成的Si。
在该方法中，在低于处理温度的温度下形成所述保护层。
在该方法中，所述保护层具有不大于大约5nm的厚度。
在该方法中，所述外延材料为SiGe。
在该方法中，在低于处理温度的温度下形成所述外延材料。
该方法还包括：在处理之后，在所述外延材料的上方形成接触部件。
在该方法中，在处理之后，所述外延材料具有(311)晶面
在该方法中，所述角部的顶端高度在大约1nm和大约10nm之间的范围内。
根据本发明的另一方面，提供了一种用于制造半导体器件的方法，包括：在衬底中形成隔离部件；在所述衬底的的上方形成栅叠层；在所述衬底中形成源极/漏极(S/D)凹进腔，其中，所述S/D凹进腔定位在所述栅叠层和所述隔离部件之间；在所述S/D凹进腔中形成外延(epi)材料，其中，所述外延材料具有包含晶面的上表面；以及加热所述外延材料以将所述上表面转换为偏离所述晶面。
在该方法中，以范围在大约650℃至大约850℃之间的温度实施加热步骤。
该方法还包括：以范围在大约700℃至大约800℃之间的温度在所述外延材料的上方形成外延Si层。
该方法还包括：在所述外延Si层的上方形成接触部件。
根据本发明的又一方面，提供了一种半导体器件，包括：栅叠层，位于衬底上方；隔离结构，位于所述衬底中；以及应变部件，设置在所述栅叠层和所述隔离结构之间并且设置在所述衬底中，其中，所述应变部件包括：上表面，与具有第一晶面的所述隔离结构相邻；和侧表面，与具有第二晶面的所述栅叠层相邻，其中，所述第一晶面不同于所述第二晶面。
该器件还包括：接触部件，位于所述应变部件上方。
该器件还包括：保护层，位于所述应变部件和所述接触部件之间。
在该器件中，所述第一晶面为(111)。
在该器件中，所述第二晶面为(311)。
该器件还包括：外延Si层，位于所述应变部件上方。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的相对尺寸可以被任意增加或减少。
图1是示出根据本公开各个方面的用于制造包括应变结构的半导体器件的方法的流程图；以及
图2至图8示出了根据本公开各个方面的处于各个制造阶段的半导体器件的应变结构的示意性截面图。
具体实施方式
应该理解，以下发明提供了用于实施本发明不同部件的许多不同的实施例或实例。以下描述部件和布置的具体实例以简化本发明。当然，这些仅是实例，而不用于限制的目的。例如，以下描述中第一部件形成在第二部件上或之上可包括第一部件和第二部件以直接接触形成的实施例，并且也可包括其中额外的部件形成在第一部件和第二部件之间，使得第一部件和第二部件不直接接触的实施例。再者，本发明可以在各个示例中重复参考数字和/或字母。该重复是为了简明和清楚，而且其本身没有规定所述各种实施例和/或结构之间的关系。
图1是示出根据本发明的各个方面用于制造半导体器件200的方法100的流程图。图2至图8示出了根据图1的方法100实施例半导体器件200处于各个制造阶段的示意性截面图。半导体器件200可以包括在微处理器、存储单元和/或其他集成电路(IC)中。应该注意，图1的方法不制造完成的半导体器件200。可以使用互补金属氧化物半导体(CMOS)技术处理来制造完成的半导体器件200。因此，应该理解，可以在图1的方法之前、之间、和之后提供附加工艺，并且一些其他工艺可以仅在本文中进行简要描述。此外，简化了图1至图8以更好地理解本公开。例如，尽管附图示出了半导体器件200，但应该理解，IC可以包括许多其他器件，包括电阻器、电容器、电感器、熔丝等。
参考图1和图2，方法100开始于步骤102，其中，设置包括表面202s的衬底202。在一个实施例中，衬底202包括多晶硅衬底(例如，晶圆)。在本实施例中，衬底202指的是(100)衬底，该(100)衬底具有由(100)晶面形成的表面202s。在可选实施例中，衬底202可包括绝缘体上硅(SOI)结构。
衬底202可以进一步包括有源区域204。有源区域204可以设计要求包括各种掺杂结构。在一些实施例中，有源区域204可以掺杂有p型或n型掺杂物。例如，有源区域204可以掺杂有p型掺杂物，使用诸如硼或BF2的化学物质来实施该掺杂；掺杂有n型掺杂物，使用诸如磷或砷的化学物质来实施该掺杂；和/或其组合。有源区域204可以用作被配置成用于N型金属氧化物半导体晶体管器件(称为NMOS)的区域和被配置成用于P型金属氧化物半导体晶体管器件(称为PMOS)的区域。
在一些实施例中，隔离结构206a和206b形成在衬底202中以隔离各个有源区域204。例如，隔离结构206a和206b使用诸如硅局部氧化(LOCOS)或浅沟槽隔离(STI)的隔离技术来形成，以限定并电隔离各个有源区域204。在本实施例中，隔离结构206a和206b包括STI。隔离结构206a和206b可包括氧化硅、氮化硅、氮氧化硅、掺杂氟化物的硅酸盐玻璃(FSG)、低k介电材料、其他适当材料和/或其组合。可以通过任何适当工艺形成隔离结构206a和206b，在本实施例中，可以通过任何适当工艺形成STI。作为一个实例，STI的形成包括通过光刻工艺图案化半导体衬底202，在衬底202中蚀刻沟槽(例如，通过使用干蚀刻、湿蚀刻和/或等离子体蚀刻工艺)，以及用介电材料填充沟槽(例如，通过使用化学汽相沉积工艺)。在一些实施例中，填充的沟槽可以具有多层结构，诸如用氮化硅或氧化硅填充的热氧化物衬垫层。
仍然参考图2，在至少一个实施例中，栅叠层210a、210b和210c形成在衬底202的表面202s的上方。在一些实施例中，栅叠层210a、210b和210c通过在衬底202上顺序沉积和图案化栅极介电层212、栅电极层214和硬掩模层216来形成。
在一个实例中，栅极介电层212为包括氧化硅、氮化硅、氮氧化硅、高k电介质、其他适当介电材料或其组合的薄膜。高k电介质包括金属氧化物。对于高k电介质使用的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu以及其混合物的氧化物。在本实施例中，栅极介电层212为高k介电层，该高k介电层的厚度在大约10埃至大约30埃的范围内。栅极介电层212可以使用适当的工艺来形成，诸如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、热氧化、UV-臭氧氧化或其组合。栅极介电层212可以进一步包括界面层(未示出)以减小栅极介电层212和衬底202之间的损伤。界面层可以包括氧化硅。
然后，栅电极层214形成在栅极介电层212上方。在一些实施例中，栅电极层214可包括单层或多层结构。在本实施例中，栅电极层214可包括多晶硅。此外，栅电极层214可以为具有相同或不同掺杂物的掺杂多晶硅。在一个实施例中，栅电极层214的厚度在大约30nm至大约60nm之间的范围内。栅电极层214可以使用诸如低压化学汽相沉积(LPCVD)、等离子体增强化学汽相沉积(PECVD)、其他适当工艺或其组合的工艺来形成。
接下来，硬掩模层216形成在栅电极层214的上方，并且图案化光敏层(未示出)形成在硬掩模层216上方。光敏层的图案被转印至硬掩模层216，然后转印至栅电极层214和栅极介电层212以在衬底202的表面202s上方形成栅叠层210a、210b和210c。在一些实施例中，硬掩模层216包括氧化硅。可选地，硬掩模层216可以包括氮化硅、氮氧化硅和/或其他适当介电材料，并且可以使用诸如CVD或PVD的方法来形成。硬掩模层216的厚度在大约100埃至大约800埃之间的范围内。此后，通过干式和/或湿式剥离工艺来剥离光敏层。
参考图1和图3，方法100前进到步骤104，其中，形成栅极隔离件218覆盖栅叠层210a、210b和210c的相对侧壁。在本实施例中，栅极隔离件218与栅叠层210a、210b的侧壁相邻。在一些实施例中，栅极隔离件218可以包括单层或多层结构。在本实施例中，通过包括CVD、PVD、ALD或其他适当技术的沉积工艺在栅叠层210a、210b和210c的上方形成隔离件材料(未示出)的覆盖层。在一些实施例中，隔离件材料包括氧化硅、氮化硅、氮氧化硅、其他适当材料或其组合。在一些实施例中，隔离件材料的厚度范围在大约5nm至大约15nm之间变动。然后，对隔离件材料实施各向异性蚀刻以形成栅极隔离件218。
参考图1和图4，方法100继续到步骤106，其中，使衬底202凹进以在衬底202中形成凹进腔220、230、240和250。在一些实施例中，凹进腔220、230、240和250为源极和漏极(S/D)凹进腔。在图4的结构中，凹进腔220和250分别形成在栅叠层210a/隔离结构206a之间和栅叠层210c/隔离结构206b之间。凹进腔230和240分别形成在栅叠层210a/210b之间和栅叠层210b/210c之间。
在本实施例中，用于形成凹进腔220、230、240和250的工艺使用各向同性干蚀刻工艺开始，随后使用各向异性湿或干蚀刻工艺。在一些实施例中，使用栅极隔离件218和隔离结构206a和206b作为硬掩模来实施各向异性干蚀刻工艺，以使衬底202不被栅极隔离件218或隔离结构206a和206b保护的表面202s凹进，从而在衬底202中形成初始凹进腔(未示出)。在实施例中，可以使用HBr和/或Cl2作为蚀刻气体，在大约1mTorr至大约1000mTorr的压力、大约50W至大约1000W的功率、大约20V至大约500V的偏压、大约40℃至大约60℃的温度下实施各向同性干蚀刻工艺。此外，在所提供的实施例中，各向同性干蚀刻工艺中使用的偏压可以进行调整来更好地控制蚀刻方向，以实现用于S/D凹进区域的预期轮廓。
在一些实施例中，然后，提供湿蚀刻工艺以扩大初始凹进腔，从而形成凹进腔220、230、240和250。在一些实施例中，使用包括水合四甲基铵(TMAH)等的化学物质来实施湿蚀刻工艺。作为这种蚀刻工艺的结果，可以在凹进腔220、230、240和250的每一个中形成多个刻面。应该注意，具有或不具有蚀刻停止件的外围环境可以影响S/D凹进腔220、230、240和250的最终特征。在湿蚀刻工艺期间，隔离结构206a可以用作蚀刻停止件，该蚀刻停止件用于在栅叠层210a和隔离结构206a之间限定凹进腔220。在一些实施例中，栅叠层210a和隔离结构206a之间的凹进腔220具有由底刻面220c、上侧壁刻面220a、下侧壁刻面220b和220d以及隔离结构206a的侧壁上部所限定的对应侧壁表面。从而，由此形成的刻面220a和刻面220b彼此相交并在凹进腔220中一起限定楔形物220w，使得楔形凹进腔220在衬底202中朝向沟道区域延伸到隔离件218正下方的区域中。在一些实施例中，不具有蚀刻停止件的相邻栅叠层210a和210b之间的凹进腔230具有对应的侧壁表面，每一个都由底刻面230c、上侧壁刻面230a、230e以及下侧壁刻面230b和230d来限定。从而，由此形成的刻面230d和刻面230e彼此相交，并在凹进腔230中一起限定楔形物230w，使得楔形凹进腔230在衬底202中朝向沟道区域延伸到隔离件210正下方的区域中。
在所示实例中，底刻面220c、230c由(100)晶面形成，(100)晶面平行于衬底202的表面202s的晶面。在所示实例中，上侧壁刻面220a、230a、230e和下侧壁刻面220b、220d、230b、230d由(111)晶面形成，并且上侧壁刻面220a、230a相对于底刻面220c、230c形成角度θ1。此外，下侧壁刻面220b、230b相对于底刻面220c、230c形成小于角度θ1的角度θ2。在图4的结构中，角度θ1的范围在大约90度至大约150度之间，而角度θ2的范围在大约40度至大约60度之间。在本实施例中，在通过衬底202的(111)晶面形成刻面220a、230a、220b和230b的情况下，角度θ1、θ2分别采用大约146度和大约56度的值。然而，应该注意，图4的结构不限于通过(111)晶面形成刻面220a、230a、220b和230b的情况。
此外，底刻面220c形成在从衬底202的表面202s开始测量的深度D1处，而上刻面220a向下形成深度D2。在图4的结构中，深度D1在大约20nm至大约70nm的范围内，而深度D2在大约5nm至大约60nm的范围内。通过优化深度D2和相对楔形物220w、230w之间的距离，可以有效地限制应变材料222(图5所示)对于沟道区域的单轴压缩应力，从而增强了器件性能。
至此的工艺步骤提供了具有与栅叠层210a、210b和210c相邻的凹进腔220、230、240和250的衬底202。参考图1和图5，方法100继续到步骤108，其中，使用包括选择外延生长(SEG)、循环沉积和蚀刻(CDE)、化学汽相沉积(CVD)技术(例如，汽相外延生长(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延生长(MBE)、其他适当的外延工艺或其组合的工艺，在衬底202的凹进腔220、230、240、250中生长应变材料222。在一些实施例中，应变材料222具有不同于衬底202的晶格常数，以在半导体器件200的沟通区域上引入应变或应力，因此，能够进行器件的载流子迁移以增强器件性能。
在本实施例中，实施预清洗工艺来使用包括氢氟酸(HF)或其他适当溶液的化学制剂清洗凹进腔220、230、240、250。然后，可以提供气态或液态前体来与衬底202的成分相互作用，以形成诸如硅锗(SiGe)的应变材料222来填充凹进腔220、230、240、250。在一个实施例中，使用包括SiH2Cl2、HCl、GeH4、B2H6、H2或其组合的反应气体，以大约600至750℃的温度以及在大约10Torr至大约80Torr的压力下实施形成包括SiGe的应变材料222的工艺。在一些实施例中，SiH2Cl2的质量流率与HCl的质量流率的比率在大约0.45至0.55的范围内。在一个实施例中，应变材料222由此从刻面230a、230b、230c、230d和230e到衬底202中的凹进腔230的中心进行生长。在另一实施例中，应变材料222由此从刻面220a、220b、220c、和220d 230e到衬底202中的凹进腔220的中心进行生长。
在一些实施例中，应变材料222在不与隔离结构206a相邻的凹进腔230中主要沿着刻面230c生长，因此具有由(100)晶面所形成的上表面220a。在本实施例中，应变材料222在与隔离结构206a相邻的凹进腔220中的生长被隔离结构206a所限制，因为由具有非晶结构的电介质形成的隔离结构206a不能提供成核位置来生长外延生长材料。在一些实施例中，应变材料222在凹进腔220中的生长趋向于具有由具有稳定表面能的(111)晶面形成的上表面222b。凹进腔220中的应变材料222具有形成在下侧壁刻面220b上方的下侧壁表面222c，因此由(111)晶面形成。在一些实施例中，下侧壁表面222c与上表面222b平行。从图5可以看出，与隔离结构206a相邻的应变材料222占据凹进腔220的较小部分。
在图5A中，半导体器件200被放大以更好地理解凹进腔220中应变材料222的轮廓。在本实施例中，凹进腔220中的应变材料222具有与栅叠层210a的边缘相邻的角部222d，并具有高于衬底202的表面202s的顶端。角部222c具有从表面202s到角部222d的顶端测量的高度D3。在一些实施例中，高度D3的范围在大约1nm至大约10nm之间。
参考图1和图6，方法100继续到步骤110，其中，在应变材料222的上方形成保护层224。在本实施例中，通过外延生长工艺形成保护层224。在一些实施例中，保护层224用作防止下面的应变材料222在随后处理工艺中波动的保护层。在凹进腔230中的应变材料222上方不与隔离结构206a相邻的保护层224具有厚度D4。在一些实施例中，厚度D4的范围在大约1nm至大约5nm之间。位于凹进腔220中的应变材料222的上方且与隔离结构206a相邻的保护层224具有侧壁224c，该侧壁224c与隔离结构206a接触，其中，与侧壁224c接触的隔离结构206a的位置具有厚度D5。在一些实施例中，厚度D4与厚度D5的比率在大约1nm至大约3nm之间的范围内。在一些实施例中，在凹进腔230中的应变材料222上方的保护层224可以沿着上表面222a的晶体定向生长，并具有由(100)晶面形成的上表面224a。在一些实施例中，在凹进腔220中的应变材料222上方的保护层224可以沿着上表面222b的晶体方向生长，并具有由(111)晶面形成的上表面224b。
在一些实施例中，保护层224包括不同于应变材料222的材料。在一些实施例中，保护层224为含硅层。在本实施例中，覆盖层224为硅。在一些实施例中，保护层224通过包括选择外延生长(SEG)、循环沉积和蚀刻(CDE)、化学汽相沉积(CVD)技术(例如，汽相外延生长(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延生长(MBE)、其他适当的外延工艺或其组合的工艺来形成。在本实施例中，保护层224通过与形成应变材料222的工艺相同的工艺来形成。在一些实施例中，通过改变以大约700℃至大约800℃的温度、在大约10Torr至大约50Torr的压力以及使用含硅的气体(例如，SiH2Cl2)作为反应气体来实施的工艺条件，在形成应变材料222之后继续形成保护层224。在可选实施例中，利用含硅的气体引入B2H6和/或H2用于形成保护层224。
参考图1和图7，方法100继续到步骤112，其中，向半导体器件200提供处理。在一些实施例中，处理为加热工艺。在一些实施例中，以高于用于形成保护层224的温度和/或用于形成应变材料222的温度的温度来实施该处理。在一些实施例中，以范围在大约650℃至大约850℃之间的温度来实施处理。在一些实施例中，在大约10Torr至大约50Torr的压力下实施处理并持续不小于大约30秒的时间周期。在一些实施例中，在处理工艺中引入具有大约35slm至大约40slm(每分钟标准公升)的流速的载气(例如，H2)用于热传导。
在处理工艺之后，在一些实施例中，在凹进腔220中重新分布应变材料222的角部222d的至少一部分，从而增加凹进腔220中应变材料222的量。在一个实施例中，在凹进腔220中完全重新分布衬底202的表面202s上方的角部222d，因此，所有应变材料222都在凹进腔220中。凹进腔220中应变材料222的增加量可以制造大体积应变结构以增强载流子迁移率并提升半导体器件200的器件性能。
在一个实施例中，由于减小角部222d中顶端的高表面能而导致重新分布。在可选实施例中，由于处理中的回流工艺而导致重新分布。凹进腔220中的应变材料222的原始上表面222b在处理之后被转换为经处理的上表面222b’。在一些实施例中，经处理的上表面222b’具有偏离原始(111)晶面的转换晶面，因此，应变材料222的下侧壁表面222c与经处理的上表面222b’不平行。在本实施例中，经处理的上表面222b’具有(311)晶面。因此，覆盖保护层224的上表面224b可以转换为经处理的上表面224b’。在一些实施例中，经处理的上表面224b’从原始(111)晶面转换为偏离(111)晶面。在本实施例中，经处理的上表面224b’具有(311)晶面。在一些实施例中，在处理之后，没有改变凹进腔230中的应变材料222的上表面222a的晶体定向。
参考图1和图8，方法100继续到步骤114，其中，在保护层224的上方形成接触部件226。在本实施例中，通过与用于形成应变材料222或保护层224的工艺相同的工艺来形成接触部件226。接触部件226可以在保护层224和随后形成的硅化物结构之间提供低接触阻抗。在至少一个实施例中，接触部件226具有范围在大约150埃至大约200埃之间的厚度。在一些实施例中，接触部件226包括与保护层224的材料相同的材料。在可选实施例中，接触部件226包括与应变材料222的材料相同的材料。
应该理解，半导体器件200可以经受进一步的CMOS工艺以形成诸如接触/通孔、互连金属层、介电层、钝化层等的各种部件。在一些实施例中，栅叠层210a、210b、21c可以为伪栅叠层。因此，CMOS工艺进一步包括“后栅极”工艺，从而用金属栅电极代替多晶硅栅电极，以提高器件性能。在一个实施例中，金属栅电极可包括诸如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi、其他适当导电材料或其组合的金属。已经意识到，修改的应变结构对半导体器件的沟道区域提供给定量的应变，从而增强器件性能。
上面讨论的本公开的各个实施例提供了相对于先前公知方法的优点，应该理解，不是所有实施例都要求具备特定优点，并且不同的实施例可以提供不同的优点。一个优点为可以增加与隔离结构相邻的S/D凹进腔中应变材料的底部以增强载流子迁移率并提升器件性能。另一优点为可以防止由于在应变材料的底部上方形成随后的硅化物所导致的器件不稳定性和/或器件故障的可能性。
在一个实施例中，用于制造半导体器件的方法包括：在衬底的上方形成栅叠层；在衬底中形成凹进腔，其中，凹进腔水平地定位在栅叠层和隔离部件之间；在凹进腔中形成外延生长(外延)材料，其中，外延材料具有在凹进腔上方的角部；以及提供处理以重新分布凹进腔中的角部的至少一部分。
在另一实施例中，一种用于制造半导体器件的方法包括：在衬底中形成隔离部件；在衬底的的上方形成栅叠层；在衬底中形成源极/漏极(S/D)凹进腔，其中，S/D凹进腔定位在栅叠层和隔离部件之间；在S/D凹进腔中形成外延生长(外延)材料，其中，外延材料具有包含晶面的上表面；以及加热外延材料以将上表面转换为偏离晶面。
在又一实施例中，一种半导体器件包括：栅叠层，位于衬底的上方；隔离结构，位于衬底中；以及应变部件，设置在栅叠层和隔离机构之间并且位于衬底中。应变部件包括：上表面，与具有第一晶面的隔离结构相邻；和侧表面，与具有第二晶面的栅叠层相邻。第一晶面不同于第二晶面。
虽然通过实例并根据优选实施例描述了本公开，但应该理解，本公开不限于所公开的实施例。相反，其可以覆盖各种修改和类似布置(对本领域的技术人员是显而易见的)。因此，所附权利要求的范围应该符合广义解释以包括所有这些修改和类似布置。

Claims (18)

1.一种用于制造半导体器件的方法，包括：
在衬底中形成隔离部件；
在所述衬底的上方形成栅叠层；
在所述衬底中形成凹进腔，其中，所述凹进腔水平地定位在所述栅叠层和所述隔离部件之间；
在所述凹进腔中形成外延(epi)材料，其中，所述外延材料具有位于所述凹进腔上方的角部；
在所述外延材料的上方形成保护层；以及
对所述外延材料和所述保护层提供加热处理以重新分布所述凹进腔中的所述角部和所述保护层的至少一部分。
2.根据权利要求1所述的用于制造半导体器件的方法，其中，所述保护层是通过外延生长工艺形成的Si。
3.根据权利要求1所述的用于制造半导体器件的方法，其中，在低于处理温度的温度下形成所述保护层。
4.根据权利要求1所述的用于制造半导体器件的方法，其中，所述保护层具有不大于5nm的厚度。
5.根据权利要求1所述的用于制造半导体器件的方法，其中，所述外延材料为SiGe。
6.根据权利要求1所述的用于制造半导体器件的方法，其中，在低于处理温度的温度下形成所述外延材料。
7.根据权利要求1所述的用于制造半导体器件的方法，还包括：
在处理之后，在所述外延材料的上方形成接触部件。
8.根据权利要求1所述的用于制造半导体器件的方法，其中，在处理之后，所述外延材料具有(311)晶面。
9.根据权利要求1所述的用于制造半导体器件的方法，其中，所述角部的顶端高度在1nm和10nm之间的范围内。
10.一种用于制造半导体器件的方法，包括：
在衬底中形成隔离部件；
在所述衬底的上方形成栅叠层；
在所述衬底中形成源极/漏极S/D凹进腔，其中，所述源极/漏极S/D凹进腔定位在所述栅叠层和所述隔离部件之间；
在所述源极/漏极S/D凹进腔中形成外延(epi)材料，其中，所述外延材料具有包含(111)晶面的上表面；
在所述外延材料的上方形成外延Si层，其中，所述外延Si层具有包含(111)晶面的上表面；以及
加热所述外延材料和所述外延Si层以将所述外延材料的上表面和所述外延Si层的上表面转换为偏离所述(111)晶面。
11.根据权利要求10所述的用于制造半导体器件的方法，其中，以范围在650℃至850℃之间的温度实施加热步骤。
12.根据权利要求10所述的用于制造半导体器件的方法，还包括：
以范围在700℃至800℃之间的温度在所述外延材料的上方形成外延Si层。
13.根据权利要求12所述的用于制造半导体器件的方法，还包括：
在所述外延Si层的上方形成接触部件。
14.一种半导体器件，包括：
栅叠层，位于衬底上方；
隔离结构，位于所述衬底中；
应变部件，设置在所述栅叠层和所述隔离结构之间并且设置在所述衬底中，其中，所述应变部件包括：
上表面，与具有第一晶面的所述隔离结构相邻；和
侧表面，与具有第二晶面的所述栅叠层相邻，其中，所述第一晶面不同于所述第二晶面；以及
外延Si层，位于所述应变部件上方。
15.根据权利要求14所述的半导体器件，还包括：
接触部件，位于所述应变部件上方。
16.根据权利要求15所述的半导体器件，其中：
所述外延Si层，位于所述应变部件和所述接触部件之间。
17.根据权利要求14所述的半导体器件，其中，所述第一晶面为(111)。
18.根据权利要求14所述的半导体器件，其中，所述第二晶面为(311)。
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