CN103531548B - 具有气隙的半导体封装结构及其形成方法 - Google Patents

具有气隙的半导体封装结构及其形成方法 Download PDF

Info

Publication number
CN103531548B
CN103531548B CN201310264977.XA CN201310264977A CN103531548B CN 103531548 B CN103531548 B CN 103531548B CN 201310264977 A CN201310264977 A CN 201310264977A CN 103531548 B CN103531548 B CN 103531548B
Authority
CN
China
Prior art keywords
package substrate
encapsulating structure
tube core
air gap
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310264977.XA
Other languages
English (en)
Chinese (zh)
Other versions
CN103531548A (zh
Inventor
T·S·尤林
B·J·卡彭特
B·P·维尔克森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of CN103531548A publication Critical patent/CN103531548A/zh
Application granted granted Critical
Publication of CN103531548B publication Critical patent/CN103531548B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07302—Connecting or disconnecting of die-attach connectors using an auxiliary member
    • H10W72/07304—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07502—Connecting or disconnecting of bond wires using an auxiliary member
    • H10W72/07504—Connecting or disconnecting of bond wires using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/127—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed characterised by arrangements for sealing or adhesion
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
CN201310264977.XA 2012-06-29 2013-06-28 具有气隙的半导体封装结构及其形成方法 Active CN103531548B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/537,388 2012-06-29
US13/537,388 US8704370B2 (en) 2012-06-29 2012-06-29 Semiconductor package structure having an air gap and method for forming

Publications (2)

Publication Number Publication Date
CN103531548A CN103531548A (zh) 2014-01-22
CN103531548B true CN103531548B (zh) 2019-03-29

Family

ID=49777257

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310264977.XA Active CN103531548B (zh) 2012-06-29 2013-06-28 具有气隙的半导体封装结构及其形成方法

Country Status (3)

Country Link
US (1) US8704370B2 (https=)
JP (1) JP6214080B2 (https=)
CN (1) CN103531548B (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10068817B2 (en) * 2016-03-18 2018-09-04 Macom Technology Solutions Holdings, Inc. Semiconductor package
US11211305B2 (en) 2016-04-01 2021-12-28 Texas Instruments Incorporated Apparatus and method to support thermal management of semiconductor-based components
US10861796B2 (en) 2016-05-10 2020-12-08 Texas Instruments Incorporated Floating die package
US10179730B2 (en) 2016-12-08 2019-01-15 Texas Instruments Incorporated Electronic sensors with sensor die in package structure cavity
US9761543B1 (en) 2016-12-20 2017-09-12 Texas Instruments Incorporated Integrated circuits with thermal isolation and temperature regulation
US10074639B2 (en) 2016-12-30 2018-09-11 Texas Instruments Incorporated Isolator integrated circuits with package structure cavity and fabrication methods
US10411150B2 (en) 2016-12-30 2019-09-10 Texas Instruments Incorporated Optical isolation systems and circuits and photon detectors with extended lateral P-N junctions
US9865537B1 (en) * 2016-12-30 2018-01-09 Texas Instruments Incorporated Methods and apparatus for integrated circuit failsafe fuse package with arc arrest
US9929110B1 (en) 2016-12-30 2018-03-27 Texas Instruments Incorporated Integrated circuit wave device and method
US10121847B2 (en) 2017-03-17 2018-11-06 Texas Instruments Incorporated Galvanic isolation device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010001711A1 (de) * 2010-02-09 2011-08-11 Robert Bosch GmbH, 70469 Halbleiter-Bauelement und entsprechendes Herstellungsverfahren

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5474958A (en) 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
JP3918303B2 (ja) * 1998-05-29 2007-05-23 ソニー株式会社 半導体パッケージ
JP3654116B2 (ja) * 2000-03-10 2005-06-02 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
TWI256092B (en) * 2004-12-02 2006-06-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
JP4667076B2 (ja) * 2005-03-04 2011-04-06 ソニーケミカル＆インフォメーションデバイス株式会社 機能素子実装モジュールの実装方法
KR100753528B1 (ko) * 2006-01-04 2007-08-30 삼성전자주식회사 웨이퍼 레벨 패키지 및 이의 제조 방법
US7651891B1 (en) 2007-08-09 2010-01-26 National Semiconductor Corporation Integrated circuit package with stress reduction
JP5067107B2 (ja) * 2007-10-12 2012-11-07 富士通株式会社 回路基板および半導体装置
JP2010040890A (ja) * 2008-08-07 2010-02-18 Yokogawa Electric Corp フリップチップｂｇａ基板
JP5590814B2 (ja) * 2009-03-30 2014-09-17 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
JP2010245337A (ja) * 2009-04-07 2010-10-28 Elpida Memory Inc 半導体装置及びその製造方法
JP2011014615A (ja) * 2009-06-30 2011-01-20 Denso Corp センサ装置およびその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010001711A1 (de) * 2010-02-09 2011-08-11 Robert Bosch GmbH, 70469 Halbleiter-Bauelement und entsprechendes Herstellungsverfahren

Also Published As

Publication number Publication date
JP2014011456A (ja) 2014-01-20
JP6214080B2 (ja) 2017-10-18
CN103531548A (zh) 2014-01-22
US8704370B2 (en) 2014-04-22
US20140001632A1 (en) 2014-01-02

Similar Documents

Publication Publication Date Title
CN103531548B (zh) 具有气隙的半导体封装结构及其形成方法
US11895930B2 (en) Current sensor package with continuous insulation
US9252113B2 (en) No-exposed-pad ball grid array (BGA) packaging structures and method for manufacturing the same
CN109494202B (zh) 一种半导体芯片封装方法及封装结构
TW200826270A (en) Semiconductor package and a manufacturing method thereof
CN104659000B (zh) 具有球焊盘的基板、半导体封装体以及制造方法
CN109390239A (zh) 半导体封装件的制造方法
JP4969113B2 (ja) 回路装置の製造方法
CN102891129A (zh) 预塑封引线框架及其封装工艺
JP2013069741A (ja) リードフレーム、半導体装置、リードフレームの製造方法及び半導体装置の製造方法
CN103295979A (zh) 封装结构及其制造方法
KR101085185B1 (ko) 회로 기판 구조, 패키징 구조 및 이들의 제조 방법
CN106601636A (zh) 一种贴装预包封金属导通三维封装结构的工艺方法
TWI506753B (zh) 無芯層封裝結構及其製造方法
CN103579029B (zh) 封装结构及其制造方法
CN211125639U (zh) 电子装置
KR19990068199A (ko) 프레임 형상의 몰드부를 갖는 반도체 장치용 패키지 및 그 제조 방법
JPH11284101A (ja) 半導体装置用パッケ―ジおよびその製造方法
JP4845090B2 (ja) 回路装置の製造方法
CN107768339A (zh) 半导体器件及相应方法
CN102655715A (zh) 柔性印刷电路板及其制造方法
TWI623076B (zh) 導線架製作方法
JP5037071B2 (ja) 樹脂封止型半導体装置の製造方法
JP6219787B2 (ja) 配線基板の製造方法
CN105655315A (zh) 用于无引脚封装结构的引线框架、制作方法及封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: Texas in the United States

Applicant after: NXP America Co Ltd

Address before: Texas in the United States

Applicant before: Fisical Semiconductor Inc.

GR01 Patent grant
GR01 Patent grant