CN103295979A - 封装结构及其制造方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 136
- 230000004888 barrier function Effects 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000000919 ceramic Substances 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 2
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims 2
- 230000008569 process Effects 0.000 description 15
- 238000012545 processing Methods 0.000 description 10
- 238000006073 displacement reaction Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 229910044991 metal oxide Inorganic materials 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000004804 winding Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 230000008439 repair process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- CVOFKRWYWCSDMA-UHFFFAOYSA-N 2-chloro-n-(2,6-diethylphenyl)-n-(methoxymethyl)acetamide;2,6-dinitro-n,n-dipropyl-4-(trifluoromethyl)aniline Chemical compound CCC1=CC=CC(CC)=C1N(COC)C(=O)CCl.CCCN(CCC)C1=C([N+]([O-])=O)C=C(C(F)(F)F)C=C1[N+]([O-])=O CVOFKRWYWCSDMA-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Abstract
本发明公开一种由一元件承载具和一可修改的基板结合组成的封装结构。在一个实施例中,一凹洞形成在该元件承载具上,以及一传导元件配置在该基板上,其中该基板配置在该元件承载具上,以及该传导元件配置在该元件承载具的该凹洞。在该基板内的导电图案电性连接至该元件承载具和该第一传导元件的输入/输出端。本发明也公开一种由一元件承载具和一可修改基板结合组成的封装结构的制造方法。在一个实施例中,可修改在该基板内一部分的该导电图案。
Description
技术领域
本发明是有关一种封装结构,特别指一种由一元件承载具和一可修改的基板结合组成的封装结构。
背景技术
导线架(lead frame)是一种被应用在集成电路(IC)封装的材料,其具有不同的型式,例如四边接脚扁平式封装(QFP)、薄小外型封装(TSOP)、小外型晶体管(SOT)或J型接脚小外型封装(SOJ)。通过组装和互相连接一半导体元件至一导线架来构成封胶(molding)的半导体元件,此结构常常使用塑性材料封胶。一导线架由金属带状物(metal ribbon)构成,且具有一桨状物(paddle)(亦为已知的晶粒桨状物(die paddle),晶粒附加标签(die-attach tab),or岛状物(island)),一半导体元件设置在该桨状物上。前述导线架具有多个导线(lead)不与该桨状物重叠排列。
传统上,集成电路芯片是使用晶粒结合(die bond)的方式设置在导线架上。前述晶粒结合的制造程序包含很多步骤:打线(wire bond)、集成电路芯片封胶、切单后测试等等。通过整合或封装导线架和其他元件,例如电感或电容,可以制造不同的产品。因为制程容易、成熟且信赖性良好,为目前最主要制程之一。然而,这种传统制程有很多的缺点,其包含:a.制程成本高,且须使用模具来完成封胶,因此增加模具开发的成本;b.设计面积只能平面而缺乏设计弹性,产品无法缩小;c.只能封装成单颗元件,并不具模块化的能力;d.散热表现不佳。
因此,本发明提出了一个封装结构及其制程方法来克服上述的缺点。
发明内容
本发明的一目的是提供一个封装结构,包含:一元件承载具,具有在其上的一凹洞;一基板,具有在其内的一导电图案;以及一第一传导元件,具有至少一第一输入/输出端,其中该第一传导元件配置在该基板上,其中该基板配置在该元件承载具上,以及至少一部分的该第一传导元件设置在该元件承载具的该凹洞;以及在该基板内的该导电图案电性连接至该第一元件承载具和该第一传导元件的该至少一第一输入/输出端。
多个传导元件埋藏在此封装结构中以降低封装结构模块尺寸。此封装结构具有最短的导电路径,以降低总线路阻抗以及提高电性效率。
元件承载具可为一印刷电路板(PCB)、一陶瓷基板、一金属基板、一导线架等等。在元件承载具的内部、上方或下方具有用于外部电性连接的导电图案。一第一传导元件被封进元件承载具的凹洞,而非传统上使用塑性材料模封(molding)。在基板的内部、上方或下方也具有用于外部电性连接的导电图案。元件承载具可为一印刷电路板(PCB)、一陶瓷基板等等。
一第二传导元件通过表面粘着技术(SMT)配置于基板上。第一传导元件和第二传导元件可以是主动元件,例如集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)或二极管等等,或是被动元件,例如电阻、电容或电感等等。一绝缘层形成在元件承载具和基板之间。在一个实施例中,绝缘层也填充在元件承载具的凹洞,并将第一导电元件封进内部。
导电图案已在早期的制程图案化于基板上,例如印刷电路板(PCB)制程(印刷电路板(PCB)制程较薄膜制程(film process、黄光制程lithography process)或印刷制程便宜),因此可大大地节省成本。
基板为一可修改或可置换的基板。在一个实施例中,如果基板内的导电图案有故障的状况,可以移动基板且对基板内的一部分导电图案进行修复或修改。在一个实施例中,不用从封装结构移走基板便可对基板内的一部分导电图案进行修复或修改。在一个实施例中,如果基板内的导电图案需要改变或修改,为了达到较佳的封装结构和电性特征,基板可被另一个具有另一个导电图案的基板置换。
本发明的一目的是提供一个封装结构,具有配置在基板内空隙的至少一第三传导元件。第三传导元件可为一电阻。在一个实施例中,元件承载具可配置在基板的上表面和下表面。在一个实施例中,基板可配置在元件承载具的上表面和下表面。
本发明封装结构主要的优点描述如下:
(a)和传统上用于集成电路封装结构的导线架和模封(molding)相比,元件承载具直接电性连接至在基板内的导电图案。因此不需要直接在元件承载具作复杂的图案化制程。
(b)基板为一可修改或可置换的基板(是描述如上)。
(c)利用点胶(dispensing)或涂胶(gluing)取代封胶用以保护第一传导元件。因此,不需要额外的模具开发进而可以节省时间和成本,也较容易设计。
(d)元件承载具由金属制成,因此具有比印刷电路板(PCB)较佳的散热性和导电性。
在参阅图式及接下来的段落所描述的实施方式之后,该技术领域具有通常知识者便可了解本发明的其它目的,以及本发明的技术手段及实施态样。
附图说明
图1A为此封装结构的剖面示意图;
图1B为图1A的结构上具有至少一第二传导元件的一产品结构示意图;
图1C为具有至少一第三传导元件的产品结构示意图;
图1D说明本发明封装结构的一个实施例;
图1E说明本发明封装结构的另一个实施例;
图2为制造图1A或图1B的封装结构的流程剖面示意图。
附图标记说明:10封装结构;11元件承载具;12基板;13导电图案;14绝缘层;15第一传导元件;16第二垫片;17凹洞;18第二传导元件;20,30,40,50产品结构;21第一垫片;22第三传导元件;24空隙;101,102,103,104,105,106步骤。
具体实施方式
本发明的详细说明于随后描述,这里所描述的较佳实施例是作为说明和描述的用途,并非用来限定本发明的范围。
在本发明中,为了使下面的叙述更加清楚,一些易混淆的字在开头定义。元件承载具意指一个在其上可配置至少一个元件的物件。依元件的大小、形状或是配置位置,元件承载可具有任何适合的外观。
本发明公开一种由一元件承载具和一可修改的基板结合组成的封装结构。图1A为此封装结构10的剖面示意图。此结构10包含一元件承载具11、一基板12、一导电图案13、一绝缘层14以及一第一传导元件15。
元件承载具11具有在其内的一导电图案(图未示)和可作为外部电性连接的多个垫片(输入/输出端)(图未示)。在一个实施例中,垫片可配置在封装结构10任何适合的位置。垫片可配置在元件承载具11的下方或是基板12上,用以制成最佳的封装结构。元件承载具11可为一印刷电路板(PCB)、一陶瓷基板、一金属基板、一导线架等等。在一个实施例中,元件承载具11(例如金属基板、导线架)具有至少一空隙(图未示)。空隙可被任何适合的填充层(图未示)填满,例如一绝缘层。元件承载具11和基板12的外观和形状是依垫片的布局(layout)而定,且元件承载具11经由垫片电性连接至印刷电路板(PCB)或另一个传导元件(图未示),例如集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、扼流线圈(choke)或电容等等。在一个实施例中,元件承载具11包含多个次元件承载具,其中该多个次元件承载具一起结合。
元件承载具11具有在其内的至少一凹洞17。凹洞17的形成是通过移除一个或多个部分的元件承载具11。至少一部分的第一传导元件15(例如集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、扼流线圈(choke)或电容)设置在凹洞17。凹洞17是以不同的方式实现,例如,在一个实施例中,凹洞17是形成于元件承载具11内部;在另一个实施例中,凹洞17具有一边和元件承载具11的一边对齐,在更另一个实施例中,凹洞17具有两边和元件承载具11的两边对齐。
在一个实施例中,凹洞17可形成在元件承载具11上,其中元件承载具11包含多个次元件承载具,该多个次元件承载具一起结合。
基板12是设置在元件承载具11之上(例如:向下设置(down set))。基板12包含一导电图案13用以连接元件承载具11和第一传导元件15的至少一输入/输出端。在第一传导元件15和元件承载具11可以直接的电性连接,也可以非直接的电性连接。在一个实施例中(如图1A所示),通过在第一传导元件15和元件承载具11之间填充一绝缘层14使得第一传导元件15电性绝缘于元件承载具11。在一个实施例中,第一传导元件15经由在基板12内部的导电图案13电性连接至元件承载具11。在一个实施例中,至少一导电层(图未示)形成在元件承载具11和基板12之间以达到较佳的电性特征。在一个实施例中,基板12包含多个次基板以达到较佳的电性特征,其中该多个次基板一起结合。
在一个实施例中,基板12包含一金属板,其中该金属板电耦合至封装结构10的多个输入/输出垫片的其中一个,以及和封装结构内的多个导电元件的任何一个绝缘,用以降低来外部电磁波对该多个导电元件造成的干涉。
基板12可为一印刷电路板(PCB)、一陶瓷基板等等。一绝缘层14形成在元件承载具11和基板12之间。绝缘层14也填充在元件承载具11的凹洞17,并将第一导电元件15封进内部。在一个实施例中,绝缘层14和该填充层(用于之前填满元件承载具11的空隙)可由相同的单一层形成。
导电图案13已在早期的预定阶段图案化于基板12上,因此不需要直接在元件承载具11上使用复杂的制程(例如薄膜制程(film process、黄光制程lithography process)或印刷制程)以形成一导电图案13,其中该导电图案13电性连接至第一传导元件15的至少一输入/输出端、第二传导元件18(之后描述)的至少一输入/输出端或元件承载具11。因此可以节省额外的图案化制程成本。基板12为一可修改或可置换的基板。在一个实施例中,如果基板12内的导电图案13有故障的状况,可以移动基板12且对基板12内的一部分导电图案13进行修复或修改。接着,基板12和元件承载具11再结合。在一个实施例中,不用从封装结构移走基板12便可以对基板12内的一部分导电图案13进行修复或修改。在一个实施例中,如果基板12内的导电图案13需要改变或修改,为了达到较佳的封装结构和电性特征,基板12可被另一个具有另一个导电图案的基板(图未示)置换。置换后的基板的导电图案电性连接至元件承载具11和第一传导元件15的至少一输入/输出端。
图1B为图1A的结构10上具有至少一第二传导元件18的一产品结构20示意图。与结构10相比,产品结构20进一步包含在基板12上的至少一第二传导元件18。通过已知技术(例如薄膜制程、印刷制程或其结合),在基板12上形成多个第一垫片21,然后在第一垫片21上放置第二传导元件18(例如:集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、扼流线圈(choke)或电容)。在一个具体实施中,为了得到较佳的电性特征,可在第一垫片21和基板12之间形成至少一导电层(图未示)。元件承载具11下方可配置多个第二垫片16用以外部电性连接。第一垫片21和第二垫片16可由任何导电的材料制成,例如锡、镍/金合金或其类似物等。结构20可设置于印刷电路板(PCB)或电性连接至另一传导元件(图未示)(例如:集成电路芯片(IC chip)、金属氧化层场效晶体管、绝缘栅双极晶体管(IGBT)、二极管、电阻、扼流线圈(choke)或电容),如此该第二传导元件18可经由包含第一垫片21、导电图案13、元件承载具11和该第二垫片16等的传导路径电性连接至印刷电路板(PCB)或另一传导元件(图未示)。值得说明的是,电性连接方式并不仅局限于前述方式,其是根据不同种类的产品和制程而有变化不同的电性连接方式。电性连接方式包含很多方法,但不局限于上面所述,而现有技术者易了解该电性连接方式,在此不进一步描述。
图1C为具有至少一第三传导元件22的产品结构20示意图。与结构10相比,产品结构20进一步包含配置在基板12内空隙24(或凹洞)的至少一第三传导元件22。第三传导元件22可为一电阻。上面所描述的特征可适用于图1C的结构30。
在一个本发明封装结构的实施例中,如图1D所示,元件承载具11可配置在基板12的上表面和下表面。在基板12上表面上的元件承载具11上具有在其上的至少一凹洞17,其中一导电元件15配置在该至少一凹洞17。上面所描述的特征可适用于图1D的结构40。
在一个本发明封装结构50的实施例中,如图1E所示,基板12可配置在元件承载具11的上表面和下表面。
图2为制造图1A的封装结构10或图1B的封装结构20的流程剖面示意图。
在步骤101中,提供一元件承载具11。元件承载具11具有在其内的一导电图案(图未示)和可作为外部电性连接的多个垫片(输入/输出端)(图未示)。导电图案(图未示)也可配置在元件承载具11的上方或下方。
在步骤102中,在该元件承载具11上形成一凹洞17。在步骤103中,提供一基板12,其中该基板12具有在其内的一导电图案13。在步骤104中,在该基板12上配置一第一传导元件15。
在一个实施例中,第一传导元件15和第二传导元件18可配置在基板12的相反面上。
在步骤105中,在该元件承载具11上配置该基板12和该第一传导元件15,其中至少一部分的该第一传导元件15设置在该元件承载具11的该凹洞17;基板12内的导电图案13电性连接至元件承载具11和第一传导元件15的至少一第一输入/输出端。在一个实施例中,在元件承载具11上配置该基板12、第该一传导元件15和该第二传导元件18,其中至少一部分的第一传导元件15设置在元件承载具11的凹洞17;基板12内的导电图案13电性连接至元件承载具11、第一传导元件15的至少一第一输入/输出端和第二传导元件18的至少一第一输入/输出端。元件承载具11和基板12可通过传统的技术结合,例如焊接(soldering)或接头(connector)。一绝缘层形成在元件承载具11和基板12之间。绝缘层14也填充在元件承载具11的凹洞17且将第一导电元件15封进内部。接着,形成多个垫片在元件承载具11下方或是基板12上,以及配置至少一第二导电元件18在基板12上。
在步骤106中,修改在该基板12内的一部分的该导电图案13。基板12为一可修改或可置换的基板。在一个实施例中,如果基板12内的导电图案13有故障的状况,可以移动基板12(通过去焊接(desoldering)或分离(disconnecting))且对基板12内的一部分导电图案13进行修复或修改。接着,基板12和元件承载具11再结合。在一个实施例中,不用从封装结构移走基板12便可对基板12内的一部分导电图案13进行修复或修改。在一个实施例中,如果基板12内的导电图案13需要改变或修改,为了修正错误及提升效能,基板12可被另一个具有另一个导电图案(图未示)的基板(图未示)置换。置换后的基板的导电图案电性连接至元件承载具11和第一传导元件15的至少一输入/输出端。
在一个实施例中,当从封装结构移走基板12时,第一导电元件15和基板12可一起移走。在一个实施例中,仅有基板12从封装结构移走。在一个实施例中,当从封装结构移走基板12时,第二导电元件18和基板12可一起移走。
虽然本发明以前述的较佳实施例公开如上,然其并非用以限定本发明,任何熟习相像技艺者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的专利保护范围须视本说明书所附的申请专利范围所界定者为准。
Claims (20)
1.一种封装结构,其特征在于,包含:
一第一元件承载具,具有在其上的一第一凹洞;
一基板,具有在其内的一导电图案;以及
一第一传导元件,具有至少一第一输入/输出端,其中该第一传导元件配置在该基板上,其中该基板配置在该第一元件承载具上,以及至少一部分的该第一传导元件设置在该第一元件承载具的该第一凹洞;以及在该基板内的该导电图案电性连接至该第一元件承载具和该第一传导元件的该至少一第一输入/输出端。
2.根据权利要求1所述的封装结构,其特征在于,进一步包含配置在该第一元件承载具下方的多个垫片。
3.根据权利要求1所述的封装结构,其特征在于,进一步包含配置在该基板上的多个垫片。
4.根据权利要求1所述的封装结构,其特征在于,该基板为一可置换的基板。
5.根据权利要求1所述的封装结构,其特征在于,该基板为一印刷电路板或一陶瓷基板。
6.根据权利要求1所述的封装结构,其特征在于,该第一元件承载具为一印刷电路板、一金属基板、一陶瓷基板或一导线架。
7.根据权利要求2所述的封装结构,其特征在于,该基板包含一金属板,其中该金属板电耦合至该封装结构的多个输入/输出垫片的其中一个。
8.根据权利要求1所述的封装结构,其特征在于,进一步包含:
一第二导电元件,具有至少一第二输入/输出端,其中该第二传导元件配置在该基板上;其中在该基板内的该导电图案电性连接至该第二导电元件的该至少一第二输入/输出端。
9.根据权利要求1所述的封装结构,其特征在于,进一步包含:
一在该基板内的空隙;以及
一第二导电元件,具有至少一第二输入/输出端,其中该第二传导元件配置在该基板内的该空隙;其中在该基板内的该导电图案电性连接至该第二导电元件的该至少一第二输入/输出端。
10.根据权利要求1所述的封装结构,其特征在于,进一步包含:
一第二元件承载具,是包含在其内的一第二凹洞,其中该第一元件承载具和该第二元件承载具配置在该基板的相反面上;以及
一第二导电元件,具有至少一第二输入/输出端,其中该第二传导元件配置在该第二元件承载具的该第二凹洞,其中在该基板内的该导电图案电性连接至该第二元件承载具和该第二导电元件的该至少一第二输入/输出端。
11.根据权利要求1所述的封装结构,其特征在于,进一步包含一在该第一元件承载具和该基板之间的绝缘层。
12.根据权利要求1所述的封装结构,其特征在于,该第一元件承载具有至少一空隙,其中该至少一空隙被一填充层填满。
13.根据权利要求11所述的封装结构,其特征在于,该第一元件承载具有至少一空隙,其中该至少一空隙被一填充层填满;其中该绝缘层和该填充层是由一相同的单一层形成。
14.根据权利要求1所述的封装结构,其特征在于,该第一元件承载具由多个次第一元件承载具制成。
15.一种封装结构的制造方法,其特征在于,该方法包含了下列步骤:
a.提供一元件承载具;
b.在该元件承载具上形成一凹洞;
c.提供一第一基板,其中该第一基板具有在其内的一第一导电图案;
d.在该第一基板上配置一第一传导元件,其中该第一传导元件具有至少一第一输入/输出端;以及
e.在该元件承载具上配置该第一基板和该第一传导元件,其中至少一部分的该第一传导元件设置在该元件承载具的该凹洞;
其中在该第一基板内的该第一导电图案电性连接至该元件承载具和该第一传导元件的该至少一第一输入/输出端。
16.根据权利要求15所述的方法,其特征在于,进一步包含了下列步骤:
f.修改在该第一基板内的一部分的该第一导电图案。
17.根据权利要求16所述的方法,其特征在于,步骤f包含在修改在该第一基板内的该一部分的该第一导电图案之前,从该封装结构移走该第一基板。
18.根据权利要求17所述的方法,其特征在于,步骤f包含在修改在该第一基板内的该一部分的该第一导电图案之前,从该封装结构移走该第一导电元件。
19.根据权利要求15所述的方法,其特征在于,进一步包含了下列步骤:
f.用一第二基板置换该第一基板,其中该第二基板具有在其内的一第二导电图案,其中该第二导电图案电性连接至该元件承载具和该第一传导元件的该至少一第一输入/输出端。
20.根据权利要求17所述的方法,其特征在于,该封装结构移走该第一基板是由去焊接达成。
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KR102671978B1 (ko) * | 2019-02-11 | 2024-06-05 | 삼성전기주식회사 | 인쇄회로기판 |
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TWI782482B (zh) * | 2021-04-13 | 2022-11-01 | 群光電子股份有限公司 | 電子模組 |
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Also Published As
Publication number | Publication date |
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US20170047273A1 (en) | 2017-02-16 |
US10373894B2 (en) | 2019-08-06 |
CN107104054A (zh) | 2017-08-29 |
US9536798B2 (en) | 2017-01-03 |
US20130213704A1 (en) | 2013-08-22 |
TW201336362A (zh) | 2013-09-01 |
CN103295979B (zh) | 2017-04-12 |
TWI486105B (zh) | 2015-05-21 |
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