TW201336362A - 封裝結構及其製造方法 - Google Patents
封裝結構及其製造方法 Download PDFInfo
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- TW201336362A TW201336362A TW102105942A TW102105942A TW201336362A TW 201336362 A TW201336362 A TW 201336362A TW 102105942 A TW102105942 A TW 102105942A TW 102105942 A TW102105942 A TW 102105942A TW 201336362 A TW201336362 A TW 201336362A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 136
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000011800 void material Substances 0.000 claims description 7
- 239000000919 ceramic Substances 0.000 claims description 6
- 239000000969 carrier Substances 0.000 claims description 5
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims 2
- 239000010410 layer Substances 0.000 description 14
- 239000003990 capacitor Substances 0.000 description 6
- 230000005669 field effect Effects 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 229910044991 metal oxide Inorganic materials 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49534—Multi-layer
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L23/49548—Cross section geometry
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
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- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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Abstract
本發明揭露一種由一元件承載具和一可修改的基板結合組成之封裝結構。在一個實施例中,一凹洞形成在該元件承載具上,以及一傳導元件配置在該基板上,其中該基板配置在該元件承載具上,以及該傳導元件配置在該元件承載具的該凹洞。在該基板內的導電圖案電性連接至該元件承載具和該第一傳導元件的輸入/輸出端。本發明也揭露一種由一元件承載具和一可修改基板結合組成的封裝結構之製造方法。在一個實施例中,可修改在該基板內一部分的該導電圖案。
Description
本發明係有關一種封裝結構,特別指一種由一元件承載具和一可修改的基板結合組成之封裝結構。
導線架(lead frame)是一種被應用在積體電路(IC)封裝的材料,其具有不同的型式,例如四邊接腳扁平式封裝(QFP)、薄小外型封裝(TSOP)、小外型晶體管(SOT)或J型接腳小外型封裝(SOJ)。藉由組裝和互相連結一半導體元件至一導線架來構成封膠(molding)的半導體元件,此結構常常使用塑性材料封膠。一導線架由金屬帶狀物(metal ribbon)構成,且具有一槳狀物(paddle)(亦為已知的晶粒槳狀物(die paddle),晶粒附加標籤(die-attach tab),or島狀物(island)),一半導體元件設置在該槳狀物上。前述導線架具有複數個導線(lead)不與該槳狀物重疊排列。
傳統上,積體電路晶片係使用晶粒結合(die bond)的方式設置在導線架上。前述晶粒結合的製造程序包含很多步驟:打線(wire bond)、積體電路晶片封膠、切單後測試等等。藉由整合或封裝導線架和其他元件,例如電感或電容,可以製造不同的產品。因為製程容易、
成熟且信賴性良好,為目前最主要製程之一。然而,這種傳統製程有很多的缺點,其包含:a.製程成本高,且須使用模具來完成封膠,因此增加模具開發的成本;b.設計面積只能平面而缺乏設計彈性,產品無法縮小;c.只能封裝成單顆元件,並不具模組化的能力;d.散熱表現不佳。
因此,本發明提出了一個封裝結構及其製程方法來克服上述之缺點。
本發明之一目的係提供一個封裝結構,包含:一元件承載具,具有在其上的一凹洞;一基板,具有在其內的一導電圖案;以及一第一傳導元件,具有至少一第一輸入/輸出端,其中該第一傳導元件配置在該基板上,其中該基板配置在該元件承載具上,以及至少一部分的該第一傳導元件設置在該元件承載具的該凹洞;以及在該基板內的該導電圖案電性連接至該第一元件承載具和該第一傳導元件的該至少一第一輸入/輸出端。
複數個傳導元件埋藏在此封裝結構中以降低封裝結構模組尺寸。此封裝結構具有最短的導電路徑,以降低總線路阻抗以及提高電性效率。
元件承載具可為一印刷電路板(PCB)、一陶瓷基板、一金屬基板、一導線架等等。在元件承載具的內部、上方或下方具有用於外部電性連接的導電圖案。一第一傳導元件被封進元件承載具的凹洞,而非傳統上使用塑性材料模封(molding)。在基板的內部、上方
或下方也具有用於外部電性連接的導電圖案。元件承載具可為一印刷電路板(PCB)、一陶瓷基板等等。
一第二傳導元件藉由表面黏著技術(SMT)配置於基板上。第一傳導元件和第二傳導元件可以是主動元件,例如積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)或二極體等等,或是被動元件,例如電阻、電容或電感等等。一絕緣層形成在元件承載具和基板之間。在一個實施例中,絕緣層也填充在元件承載具的凹洞,並將第一導電元件封進內部。
導電圖案已在早期的製程圖案化於基板上,例如印刷電路板(PCB)製程(印刷電路板(PCB)製程較薄膜製程(film process、黃光製程lithography process)或印刷製程便宜),因此可大大地節省成本。
基板為一可修改或可置換的基板。在一個實施例中,如果基板內的導電圖案有故障的狀況,可以移動基板且對基板內的一部分導電圖案進行修復或修改。在一個實施例中,不用從封裝結構移走基板便可對基板內的一部分導電圖案進行修復或修改。在一個實施例中,如果基板內的導電圖案需要改變或修改,為了達到較佳的封裝結構和電性特徵,基板可被另一個具有另一個導電圖案的基板置換。
本發明之一目的係提供一個封裝結構,具有配置在基板內空隙的至少一第三傳導元件。第三傳導元件可為一電阻。在一個實施例中,元件承載具可配置在基板的上表面和下表面。在一個實施例中,基板可配置在元件承載具的上表面和下表面。
本發明封裝結構主要的優點描述如下:
(a)和傳統上用於積體電路封裝結構的導線架和模封(molding)相比,元件承載具直接電性連接至在基板內的導電圖案。因此不需要直接在元件承載具作複雜的圖案化製程。
(b)基板為一可修改或可置換的基板(係描述如上)。
(c)利用點膠(dispensing)或塗膠(gluing)取代封膠用以保護第一傳導元件。因此,不需要額外的模具開發進而可以節省時間和成本,也較容易設計。
(d)元件承載具由金屬製成,因此具有比印刷電路板(PCB)較佳的散熱性和導電性。
在參閱圖式及接下來的段落所描述之實施方式之後,該技術領域具有通常知識者便可瞭解本發明之其它目的,以及本發明之技術手段及實施態樣。
10‧‧‧封裝結構
11‧‧‧元件承載具
12‧‧‧基板
13‧‧‧導電圖案
14‧‧‧絕緣層
15‧‧‧第一傳導元件
16‧‧‧第二墊片
17‧‧‧凹洞
18‧‧‧第二傳導元件
20,30,40,50‧‧‧產品結構
21‧‧‧第一墊片
22‧‧‧第三傳導元件
24‧‧‧空隙
101,102,103,104,105,106‧‧‧步驟
第1A圖為此封裝結構之剖面示意圖;第1B圖為第1A圖之結構上具有至少一第二傳導元件之一產品結構示意圖;第1C圖為具有至少一第三傳導元件之產品結構示意圖;第1D圖說明本發明封裝結構的一個實施例;第1E圖說明本發明封裝結構的另一個實施例;第2圖為製造第1A圖或第1B圖的封裝結構之流程剖面示意圖。
本發明的詳細說明於隨後描述,這裡所描述的較佳實施例是作為說明和描述的用途,並非用來限定本發明之範圍。
在本發明中,為了使下面的敘述更加清楚,一些易混淆的字在開頭定義。元件承載具意指一個在其上可配置至少一個元件的物件。依元件的大小、形狀或是配置位置,元件承載可具有任何適合的外觀。
本發明揭露一種由一元件承載具和一可修改的基板結合組成之封裝結構。第1A圖為此封裝結構10之剖面示意圖。此結構10包含一元件承載具11、一基板12、一導電圖案13、一絕緣層14以及一第一傳導元件15。
元件承載具11具有在其內的一導電圖案(未示之)和可作為外部電性連接的複數個墊片(輸入/輸出端)(未示之)。在一個實施例中,墊片可配置在封裝結構10任何適合的位置。墊片可配置在元件承載具11的下方或是基板12上,用以製成最佳的封裝結構。元件承載具11可為一印刷電路板(PCB)、一陶瓷基板、一金屬基板、一導線架等等。在一個實施例中,元件承載具11(例如金屬基板、導線架)具有至少一空隙(未示之)。空隙可被任何適合的填充層(未示之)填滿,例如一絕緣層。元件承載具11和基板12的外觀和形狀係依墊片的佈局(layout)而定,且元件承載具11經由墊片電性連結至印刷電路板(PCB)或另一個傳導元件(未示之),例如積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、扼流線圈(choke)或電容等等。在一個實施例中,元件承載具
11包含複數個次元件承載具,其中該複數個次元件承載具一起結合。
元件承載具11具有在其內的至少一凹洞17。凹洞17的形成係藉由移除一個或多個部分的元件承載具11。至少一部分的第一傳導元件15(例如積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、扼流線圈(choke)或電容)設置在凹洞17。凹洞17係以不同的方式實現,例如,在一個實施例中,凹洞17係形成於元件承載具11內部;在另一個實施例中,凹洞17具有一邊和元件承載具11的一邊對齊,在更另一個實施例中,凹洞17具有兩邊和元件承載具11的兩邊對齊。在一個實施例中,凹洞17可形成在元件承載具11上,其中元件承載具11包含複數個次元件承載具,該複數個次元件承載具一起結合。
基板12係設置在元件承載具11之上(例如:向下設置(down set))。基板12包含一導電圖案13用以連接元件承載具11和第一傳導元件15的至少一輸入/輸出端。在第一傳導元件15和元件承載具11可以直接的電性連接,也可以非直接的電性連接。在一個實施例中(如第1A圖所示),藉由在第一傳導元件15和元件承載具11之間填充一絕緣層14使得第一傳導元件15電性絕緣於元件承載具11。在一個實施例中,第一傳導元件15經由在基板12內部的導電圖案13電性連接至元件承載具11。在一個實施例中,至少一導電層(未示之)形成在元件承載具11和基板12之間以達到較佳的電性特徵。在一個實施例中,基板12包含複數個次基板以達到較佳的
電性特徵,其中該複數個次基板一起結合。
在一個實施例中,基板12包含一金屬板,其中該金屬板電耦合至封裝結構10的複數個輸入/輸出墊片之其中一個,以及和封裝結構內的複數個導電元件之任何一個絕緣,用以降低來外部電磁波對該複數個導電元件造成之干涉。
基板12可為一印刷電路板(PCB)、一陶瓷基板等等。一絕緣層14形成在元件承載具11和基板12之間。絕緣層14也填充在元件承載具11的凹洞17,並將第一導電元件15封進內部。在一個實施例中,絕緣層14和該填充層(用於之前填滿元件承載具11的空隙)可由相同的單一層形成。
導電圖案13已在早期的預定階段圖案化於基板12上,因此不需要直接在元件承載具11上使用複雜的製程(例如薄膜製程(film process、黃光製程lithography process)或印刷製程)以形成一導電圖案13,其中該導電圖案13電性連接至第一傳導元件15的至少一輸入/輸出端、第二傳導元件18(之後描述)的至少一輸入/輸出端或元件承載具11。因此可以節省額外的圖案化製程成本。基板12為一可修改或可置換的基板。在一個實施例中,如果基板12內的導電圖案13有故障的狀況,可以移動基板12且對基板12內的一部分導電圖案13進行修復或修改。接著,基板12和元件承載具11再結合。在一個實施例中,不用從封裝結構移走基板12便可以對基板12內的一部分導電圖案13進行修復或修改。在一個實施例中,如果基板12內的導電圖案13需要改變或修改,為了達到較佳
的封裝結構和電性特徵,基板12可被另一個具有另一個導電圖案的基板(未示之)置換。置換後之基板的導電圖案電性連接至元件承載具11和第一傳導元件15的至少一輸入/輸出端。
第1B圖為第1A圖之結構10上具有至少一第二傳導元件18之一產品結構20示意圖。與結構10相比,產品結構20進一步包含在基板12上的至少一第二傳導元件18。藉由已知技術(例如薄膜製程、印刷製程或其結合),在基板12上形成複數個第一墊片21,然後在第一墊片21上放置第二傳導元件18(例如:積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、扼流線圈(choke)或電容)。在一個具體實施中,為了得到較佳的電性特徵,可在第一墊片21和基板12之間形成至少一導電層(未示之)。元件承載具11下方可配置複數個第二墊片16用以外部電性連接。第一墊片21和第二墊片16可由任何導電的材料製成,例如錫、鎳/金合金或其類似物等。結構20可設置於印刷電路板(PCB)或電性連接至另一傳導元件(未示之)(例如:積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)、二極體、電阻、扼流線圈(choke)或電容),如此該第二傳導元件18可經由包含第一墊片21、導電圖案13、元件承載具11和該第二墊片16等的傳導路徑電性連接至印刷電路板(PCB)或另一傳導元件(未示之)。值得說明的是,電性連接方式並不僅侷限於前述方式,其係根據不同種類的產品和製程而有變化不同的電性連接方式。電性連接方式包含很多方法,但不侷限於上面所述,而習知技術
者易了解該電性連接方式,在此不進一步描述。
第1C圖為具有至少一第三傳導元件22之產品結構20示意圖。與結構10相比,產品結構20進一步包含配置在基板12內空隙24(或凹洞)的至少一第三傳導元件22。第三傳導元件22可為一電阻。上面所描述的特徵可適用於第1C圖的結構30。
在一個本發明封裝結構的實施例中,如第1D圖所示,元件承載具11可配置在基板12的上表面和下表面。在基板12上表面上的元件承載具11上具有在其上的至少一凹洞17,其中一導電元件15配置在該至少一凹洞17。上面所描述的特徵可適用於第1D圖的結構40。
在一個本發明封裝結構50的實施例中,如第1E圖所示,基板12可配置在元件承載具11的上表面和下表面。
第2圖為製造第1A圖之封裝結構10或第1B圖之封裝結構20的流程剖面示意圖。
在步驟101中,提供一元件承載具11。元件承載具11具有在其內的一導電圖案(未示之)和可作為外部電性連接的複數個墊片(輸入/輸出端)(未示之)。導電圖案(未示之)也可配置在元件承載具11的上方或下方。
在步驟102中,在該元件承載具11上形成一凹洞17。在步驟103中,提供一基板12,其中該基板12具有在其內的一導電圖案13。在步驟104中,在該基板12上配置一第一傳導元件15。在一個實施例中,第一傳導元件15和第二傳導元件18可配置在基板12的
相反面上。
在步驟105中,在該元件承載具11上配置該基板12和該第一傳導元件15,其中至少一部分的該第一傳導元件15設置在該元件承載具11的該凹洞17;基板12內的導電圖案13電性連接至元件承載具11和第一傳導元件15的至少一第一輸入/輸出端。在一個實施例中,在元件承載具11上配置該基板12、第該一傳導元件15和該第二傳導元件18,其中至少一部分的第一傳導元件15設置在元件承載具11的凹洞17;基板12內的導電圖案13電性連接至元件承載具11、第一傳導元件15的至少一第一輸入/輸出端和第二傳導元件18的至少一第一輸入/輸出端。元件承載具11和基板12可藉由傳統的技術結合,例如焊接(soldering)或接頭(connector)。一絕緣層形成在元件承載具11和基板12之間。絕緣層14也填充在元件承載具11的凹洞17且將第一導電元件15封進內部。接著,形成複數個墊片在元件承載具11下方或是基板12上,以及配置至少一第二導電元件18在基板12上。
在步驟106中,修改在該基板12內的一部分之該導電圖案13。基板12為一可修改或可置換的基板。在一個實施例中,如果基板12內的導電圖案13有故障的狀況,可以移動基板12(藉由去焊接(desoldering)或分離(disconnecting))且對基板12內的一部分導電圖案13進行修復或修改。接著,基板12和元件承載具11再結合。在一個實施例中,不用從封裝結構移走基板12便可對基板12內的一部分導電圖案13進行修復或修改。在一個實施例中,如果基板12
內的導電圖案13需要改變或修改,為了修正錯誤及提升效能,基板12可被另一個具有另一個導電圖案(未示之)的基板(未示之)置換。置換後之基板的導電圖案電性連接至元件承載具11和第一傳導元件15的至少一輸入/輸出端。
在一個實施例中,當從封裝結構移走基板12時,第一導電元件15和基板12可一起移走。在一個實施例中,僅有基板12從封裝結構移走。在一個實施例中,當從封裝結構移走基板12時,第二導電元件18和基板12可一起移走。
雖然本發明以前述之較佳實施例揭露如上,然其並非用以限定本發明,任何熟習相像技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。
10‧‧‧封裝結構
11‧‧‧元件承載具
12‧‧‧基板
13‧‧‧導電圖案
14‧‧‧絕緣層
15‧‧‧第一傳導元件
17‧‧‧凹洞
Claims (20)
- 一種封裝結構,包含:一第一元件承載具,具有在其上的一第一凹洞;一基板,具有在其內的一導電圖案;以及一第一傳導元件,具有至少一第一輸入/輸出端,其中該第一傳導元件配置在該基板上,其中該基板配置在該第一元件承載具上,以及至少一部分的該第一傳導元件設置在該第一元件承載具的該第一凹洞;以及在該基板內的該導電圖案電性連接至該第一元件承載具和該第一傳導元件的該至少一第一輸入/輸出端。
- 如申請專利範圍第1項所述之封裝結構,進一步包含配置在該第一元件承載具下方的複數個墊片。
- 如申請專利範圍第1項所述之封裝結構,進一步包含配置在該基板上的複數個墊片。
- 如申請專利範圍第1項所述之封裝結構,其中該基板為一可置換的基板。
- 如申請專利範圍第1項所述之封裝結構,其中該基板為一印刷電路板 (PCB)或一陶瓷基板。
- 如申請專利範圍第1項所述之封裝結構,其中該第一元件承載具為一印刷電路板(PCB)、一金屬基板、一陶瓷基板或一導線架。
- 如申請專利範圍第2項所述之封裝結構,其中該基板包含一金屬板,其中該金屬板電耦合至該封裝結構的複數個輸入/輸出墊片之其中一個。
- 如申請專利範圍第1項所述之封裝結構,進一步包含:一第二導電元件,具有至少一第二輸入/輸出端,其中該第二傳導元件配置在該基板上;其中在該基板內的該導電圖案電性連接至該第二導電元件的該至少一第二輸入/輸出端。
- 如申請專利範圍第1項所述之封裝結構,進一步包含:一在該基板內的空隙;以及一第二導電元件,具有至少一第二輸入/輸出端,其中該第二傳導元件配置在該基板內的該空隙;其中在該基板內的該導電圖案電性連接至該第二導電元件的該至少一第二輸入/輸出端。
- 如申請專利範圍第1項所述之封裝結構,進一步包含:一第二元件承載具,係包含在其內的一第二凹洞,其中該第一元件承載具和該第二元件承載具配置在該基板的相反面上;以及 一第二導電元件,具有至少一第二輸入/輸出端,其中該第二傳導元件配置在該第二元件承載具的該第二凹洞,其中在該基板內的該導電圖案電性連接至該第二元件承載具和該第二導電元件的該至少一第二輸入/輸出端。
- 如申請專利範圍第1項所述之封裝結構,進一步包含一在該第一元件承載具和該基板之間的絕緣層。
- 如申請專利範圍第1項所述之封裝結構,其中該第一元件承載具有至少一空隙,其中該至少一空隙被一填充層填滿。
- 如申請專利範圍第11項所述之封裝結構,其中該第一元件承載具有至少一空隙,其中該至少一空隙被一填充層填滿;其中該絕緣層和該填充層係由一相同的單一層形成。
- 如申請專利範圍第1項所述之封裝結構,其中該第一元件承載具由複數個次第一元件承載具製成。
- 一種封裝結構之製造方法,該方法包含了下列步驟:a.提供一元件承載具;b.在該元件承載具上形成一凹洞;c.提供一第一基板,其中該第一基板具有在其內的一第一導電圖案; d.在該第一基板上配置一第一傳導元件,其中該第一傳導元件具有至少一第一輸入/輸出端;以及e.在該元件承載具上配置該第一基板和該第一傳導元件,其中至少一部分的該第一傳導元件設置在該元件承載具的該凹洞;其中在該第一基板內的該第一導電圖案電性連接至該元件承載具和該第一傳導元件的該至少一第一輸入/輸出端。
- 如申請專利範圍第15項所述之方法,進一步包含了下列步驟:f.修改在該第一基板內的一部分之該第一導電圖案。
- 如申請專利範圍第16項所述之方法,其中步驟f包含在修改在該第一基板內的該一部分之該第一導電圖案之前,從該封裝結構移走該第一基板。
- 如申請專利範圍第17項所述之方法,其中步驟f包含在修改在該第一基板內的該一部分之該第一導電圖案之前,從該封裝結構移走該第一導電元件。
- 如申請專利範圍第15項所述之方法,進一步包含了下列步驟:f.用一第二基板置換該第一基板,其中該第二基板具有在其內的一第二導電圖案,其中該第二導電圖案電性連接至該元件承載具和該第一傳導元件的該至少一第一輸入/輸出端。
- 如申請專利範圍第17項所述之方法,其中該封裝結構移走該第一基板係由去焊接(desoldering)達成。
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