CN103314651A - 用于获得对印刷电路板和ic基板上的铜线键合的钯表面修饰的方法 - Google Patents

用于获得对印刷电路板和ic基板上的铜线键合的钯表面修饰的方法 Download PDF

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Publication number
CN103314651A
CN103314651A CN2011800622767A CN201180062276A CN103314651A CN 103314651 A CN103314651 A CN 103314651A CN 2011800622767 A CN2011800622767 A CN 2011800622767A CN 201180062276 A CN201180062276 A CN 201180062276A CN 103314651 A CN103314651 A CN 103314651A
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palladium
layer
copper
wire bonding
lead
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CN103314651B (zh
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M·厄茨柯克
G·拉莫斯
A·基利安
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Atotech Deutschland GmbH and Co KG
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Atotech Deutschland GmbH and Co KG
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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Abstract

本发明涉及将铜线键合到基板尤其是印刷电路板和IC基板上的方法，所述基板具有包括铜键合部分和钯或钯合金层的层组合件，还涉及具有键合到上述层组合件上的铜线的基板。

Description

用于获得对印刷电路板和IC基板上的铜线键合的钯表面修饰的方法
技术领域
本发明涉及一种将铜线键合到基板，尤其是印刷电路板和IC基板的方法，所述基板具有包含铜键合部分和钯或钯合金层的层组合件以及具有键合到上述层组合件上的铜线的基板。
背景技术
在印刷电路板(PCB)和集成电路(IC)基板制造中，需要将电子元件键合到在基板的一面或双面上生成的铜结构的选定键合区域(焊盘(bond pad)作为键合部分)。这种互连在键合强度方面必须是可靠的，也就是，施加到键合互连的热应力绝不会引起该互连的断裂。
引线键合是IC封装中连接芯片与IC基板的优选工艺之一并且它占据了工业IC制造的超过70％。当前用于IC基板的主要的引线键合工艺是金线键合，其中金线键合到电镀沉积镍和金的层。可选择地，金线键合到镍、钯和金(ENEPIG)的表面上。所有情况下，铜线键合到最终的金层。近年来，铜线键合技术作为金线键合的替代已经引入到IC基板产业。当前铜线键合的标准是使用键合到由沉积在基板的铜线键合部分上的第一电镀镍和第二金层组成的层序列上的铜线键合。
在微电子封装中引线键合的机械可靠性很大程度上取决于键合楔块(bondwedge)和基板(印刷电路板、PCB或者IC基板)上的焊盘之间的界面处的金属间化合物的形成和发展，这对于成功的键合是必需的。
键合金或铜线到铜焊盘表面是困难的，主要是由于铜金属涂敷有很高的氧化趋向。
引线键合部分典型地由铜构成。如果它们保持裸露或者外部暴露于大气以及湿气，由于表面的氧化或腐蚀，铜层的焊接和引线键合性能退化。为了保持焊接或引线键合性能，为此，裸露的或暴露的铜层通常电镀镍或者化学镀镍。镀镍层保护铜相当长的一段时间内免受腐蚀性大气的作用。并且，在焊接组装步骤期间镍层作为扩散阻挡层保护铜层免于被焊料溶解。另外，镀镍层起到了界面膜的作用防止铜层和后面要镀的金层相互扩散。其后，引线键合金以电镀或化学(electroless)镀方式镀敷到约0.5μm的厚度，从而赋予便于引线键合工艺的特性。这类工艺例如描述在US5235139和US6733823中。
US2007/0104929涉及一种电镀印刷电路板的方法，包括步骤：(a)提供具有预定电路图案的印刷电路板，具有用于在其上表面安装半导体的引线键合部分以及连接外部部件与印刷电路板的焊接部分；(b)形成光防焊层到除印刷电路板中的引线键合部分和焊接部分之外的剩余部分；(c)形成化学镀钯或钯合金镀层到引线键合部分和焊接部分上；以及(d)将钯或钯合金镀层用含有水溶性金化合物的置换型浸金镀液浸渍以在钯或钯合金镀层上形成化学镀金或金合金镀层。
US2006/055023涉及包含层合层和氧化保护层的芯片载体。氧化保护层是通过使用简单、快速的膜涂布技术形成在指形焊盘或其它接触的表面上的非电镀金属涂层或者有机氧化保护薄膜。
US5175609涉及用于抗腐蚀和应力的互连多层冶金焊盘的新结构和方法，包括顺序沉积的铬、镍和贵金属或相对贵金属(relatively noble metal)的层作为互连冶金，或者多层冶金焊盘包含顺序沉积的铬、可溶贵金属、镍和贵金属或者相对贵金属的层作为互连冶金。
EP0697805A1涉及一种制造印刷电路板的方法，通过提供具有铜电路图案，铜孔和铜焊区的电路板；用焊接掩膜覆盖电路图案；以及使该板与化学镀钯溶液接触足够的时间以提供足够厚度的最终钯修饰层(finish layer)，从而保护沉积在孔里和焊区上的铜免于形成氧化物并且相对平滑和平整以提供良好的可焊性和良好的引线键合能力。铜电路图案，铜孔和铜焊区通常通过在板上镀铜来提供。然后，钯层可直接提供到铜上或者初始沉积到铜上的化学镀镍层上。
发明内容
因此，本发明的一个目标是提供待沉积到带有由铜构成的引线键合部分的基板上的层，其确保待形成的引线键合的良好可靠性并且不含金层。本文使用的金属层意指形成在引线键合部分上的至少一个由钯或钯合金构成的金属层，其适合作为铜线键合的表面。
本发明的另一个目标是提供一种形成上述层的方法，同时使得能够在这类金属层上形成稳定的引线键合，更具体地形成铜线键合。
本发明的另一个目标是提供一种IC基板，所述IC基板具有铜结构，其中所述铜结构覆盖有所述金属层。
本发明的另一个目标是提供一种印刷电路板，所述印刷电路板具有铜结构，其中所述铜结构覆盖有所述金属层。
为了达到这些目标，本发明提供一种金属层组合件，其包括：
(i)至少一个由铜或铜合金构成的引线键合部分的层；以及沉积于其上的
(ii)为钯或钯合金层的金属层
(iii)键合到所述钯或钯合金层上的铜线。
步骤(ii)中沉积的钯或钯合金层具有0.01-5.0μm的厚度，优选0.05-2.0μm并且更优选0.1-0.5μm。
所述方法的一个优选实施方式中，钯层由纯钯组成。在另一个优选实施方式中所述层组合件在引线键合部分上不含镍或镍合金层而仅含直接镀敷到引线键合部分上的钯或钯合金层。
钯由包含如下的化学(自催化)镀钯浴沉积：
■钯离子源；
■络合剂；
■还原剂。
迄今，通常将镍或镍合金层镀敷到由铜或铜合金构成的引线键合部分的层上。这类镍层通常具有0.5-10.0μm的厚度。
按照本发明的工艺中，不再需要这样做。
发明人已经发现施涂纯钯层到引线键合部分的铜或铜合金上是特别有利的。按照在镀钯或钯层之前没有镍或者镍合金层沉积到由铜或铜合金构成的引线键合部分上的实施方式，纯钯是更加优选的。按照本发明的纯钯层是包含超过99.0wt.％的钯含量的层，优选超过99.5wt.％的钯或者甚至更优选超过99.9wt.％或超过99.99wt.％的钯。
本方法的另一个实施方式中，钯镀层是包含90到99.9wt％的钯和0.1到10.0wt％的磷或硼的合金层。
本发明的优选实施方式中，金属层仅包含为钯层或者钯合金层如钯-磷层的一层，其直接形成在基板的铜或铜合金引线键合部分上。
通常，键合部分的铜或铜合金表面通常通过采用酸清洁器(cleaner)的前处理准备用于镀敷，并随后在微蚀刻浴中减少表面铜氧化物。
为了本发明的目的，在沉积钯或钯合金层之前对铜或铜合金引线键合部分施加额外的活化步骤是有利的。这类活化溶液可包含钯盐，其产生薄的钯层。该层非常薄并且通常不会覆盖整个铜或铜合金引线键合部分。它不视为该层组合件的独立层而视为活化，除钯/钯合金层之外它形成了金属晶种层(seed layer)。通常这类晶种层厚度是几埃。这类晶种层通过浸渍交换工艺镀敷到铜或铜合金层上。
如果钯层的沉积是通过化学(自催化)镀敷方法进行的，则这种活化溶液是特别优选的。
该钯/钯合金层优选镀敷到提供在IC基板或印刷电路板上的铜或铜合金结构上。
IC基板包括载体本体和铜结构，其提供在所述载体本体的一侧或两侧。因此，该金属结构涂覆有钯或钯合金层。其后，铜线键合到钯或钯合金层上。
铜线优选为纯铜线。可选择地，它可以是铜合金线。同样，铜线或铜合金线可以涂覆有金或钯，优选钯。钯涂层例如可以具有5-50nm之间的厚度，优选10-25nm。金涂层可具有相同的厚度范围。
铜结构包括用于电子元件到基板的连接的引线键合部分(也称作焊盘)，用于焊盘之间和金属化的(metalized)孔和焊盘之间的电连接的导线，以及其它导体区域，例如接地区域、屏蔽区域等等。钯或钯合金层优选地仅涂覆到焊接和键合部分，但不在导线和其它导体区域上。
和现有技术形成对比，本发明的层组合件提供了电子元件和基板之间最可靠的键合连接。
本发明的层组合件也不含镀敷到钯或钯合金层上的金层。这不仅导致涉及整体工艺成本的大幅节省。发明人还发现通过省去金层引线键合性能明显增强。
本发明的方法优选包括通过化学(自催化)镀来沉积钯或钯合金层。
化学(自催化)镀包括在化学镀液中所含的还原剂帮助下，通过还原金属来沉积该金属，由此使该还原剂被氧化。由此基板金属将被氧化并且因此溶解。在此情形中，使用的镀液中不含还原剂。
此外，纯钯层优选可通过将基板的至少一个铜线部分接触包含钯离子源和还原剂的溶液来沉积，其不含磷并且导致纯钯层的沉积。
一种沉积纯钯层的合适的化学(自催化)镀浴例如描述于US5882736中。这种镀浴包含钯盐、一种或多种氮化络合剂、以及甲酸或甲酸衍生物，但没有次磷酸盐和/或硼烷胺化合物。溶液的pH值大于4。优选地，伯胺、仲胺或叔胺或者多胺用作氮化络合剂。它们是，例如，乙二胺；1，3-丙二胺；1，2-双(3-氨基丙基氨基)-乙烷；2-乙基氨基乙胺；和二亚乙基三胺。另外，也可使用二亚乙基三胺五乙酸；硝基乙酸；N-(2-羧基乙基)-乙二胺；乙二胺-N，N-二乙酸；2-(二甲基氨基)-乙胺；1，2-二氨基丙胺；1，3-二氨基丙胺；3-(甲基氨基)-丙胺；3-(二甲基氨基)-丙胺；3-(二乙基氨基)-丙胺；双(3-氨基丙基)胺；1，2-双(3-氨基丙基)-烷基胺；二亚乙基三胺；三亚乙基四胺；四亚乙基五胺；五亚乙基六胺，以及这些氮化络合剂的任意所需混合物。然而，含硫化合物不作为稳定剂与该络合剂一起使用。
更优选地，用于以化学镀方式沉积纯钯层的溶液是含水的且包含钯盐，例如氯化钯或硫酸钯，含非次磷酸盐的化合物作为还原剂如甲酸，无机酸，例如硫酸和盐酸，或者无机碱，例如氢氧化钠或氢氧化钾，络合剂，如胺类化合物，例如乙二胺，以及，如果需要，稳定化合物。可选择地，可使用本领域熟知的和美国专利5292361、4424241、4341846、4279951和4255194描述的其它的化学钯沉积溶液和工艺。
在本发明的进一步优选实施方式中，基板的一侧或两侧提供有共形的掩模，所述共形的掩模覆盖所述基板的所述一侧或两侧上的所有区域，除了所述一侧或两侧上的在其中将在所述至少一个铜线部分上涂覆钯或钯合金层的那些区域。该共形的掩模可优选是焊接掩模，如可曝光及可显影的掩模。这类掩模可基于例如环氧树脂并且层合、旋涂、辊涂或以类似方式到电路载体的表面上。此后，它暴露于光化性光并显影以暴露待沉积的层组合件表面上的那些区域。就是这些区域将提供引线键合部分。该共形的掩模可形成为使得基板表面上暴露的区域大于形成在铜结构中的引线键合部分，由此暴露基板的电解质表面区域的部分，或者小于形成在铜结构中的引线键合部分，使得仅暴露形成在铜结构中的引线键合部分。
具体实施方式
按照本发明的工艺，由铜或铜合金构成的暴露的引线键合部分镀有纯钯或钯合金层。
钯合金层优选是具有0.1-10wt％、更优选0.5-7wt％磷含量的钯-磷层。按照本发明的纯钯层是包含钯含量超过99.0wt.％的层，优选超过99.5wt.％的钯或者甚至更优选超过99.9wt.％或超过99.99wt％的钯。优选纯钯层。
在暴露的引线键合部分上镀钯或者钯合金以形成钯或钯合金镀层。
下面，给出了引线键合部分上的化学钯或钯合金镀层形成的更详细的描述。
镀液中使用的还原剂决定了镀敷的是纯钯还是钯合金(钯-磷，钯-硼)。例如，本发明中可用的典型的化学钯镀液包含硫酸钯作为钯源，次磷酸钠或者二甲基胺硼烷，甲醛或甲酸作为还原剂，乳酸作为络合剂，以及琥珀酸作为缓冲剂，但不限于这些。为了获得钯镀层的更致密的结构，化学钯镀液的pH优选落入4.5到5.5的范围内。
该钯或钯合金镀敷工艺在约45到80℃下进行1到60分钟以获得厚度范围从0.05到5.0μm，更优选从0.1到1.0μm以及甚至更优选0.1到0.5μm的钯或钯合金镀层。
浴中络合剂的浓度取决于钯含量。通常，络合剂与钯的摩尔比是5∶1到50∶1，由此浴中络合剂的浓度是每升浴0.05g/升到100g/升。
涂渍溶液的pH值通常大于4。pH值小于4时，溶液变得不稳定并且趋向于自分解而产生氢。pH值稍小于4时，主要是附着差且暗的钯层沉积到金属表面上，当pH值低于约2时钯从溶液中沉淀出来。这种情况下，基板上获得的沉淀物是黑的且缺乏粘附力。
涂渍溶液优选的pH值是5到6。pH值大于7时，碱性浴以胶结(cementative)方式，即以无明亮光泽或粘附到基板的方式在金属表面沉积钯的趋势增加。此外，碱性涂渍溶液会侵蚀有机耐受膜(resistance film)，例如施加到电路板的焊接阻挡掩模。
如果纯钯层直接沉积到引线键合部分的铜或铜合金层上，则铜表面的预处理是可取的。为了这个目的，蚀刻清洗通常在氧化性的酸性溶液中实施，例如硫酸和过氧化氢的溶液。优选地，这之后是在酸性溶液中的另一清洗，例如硫酸溶液。清洗后，表面优选经含钯的溶液活化，例如硫酸钯溶液，其包含额外的酸如硫酸、甲烷磺酸和磷酸。通常，基板在25到30℃浸入活化浴中1到4分钟。
由于以下原因该活化步骤是优选的：随后的沉积步骤，例如在化学(自催化)镀钯浴中，该浴含有被钯金属的存在所催化活化的还原剂。因此，至少一些钯必须通过浸渍工艺沉积到铜表面上，在其中更贵重的金属钯置换较不贵重的铜。如果铜表面直接浸入自催化钯浴中，这种初始的浸渍钯沉积也可以发生，并且一旦沉积了少量的钯，则该过程作为自催化沉积进行下去。已发现过量的铜离子会使自催化钯浴组合物失活。如果初始的浸渍钯沉积在自催化钯浴中实施，则不可避免地产生铜离子的富集。因此，在生产环境中，优选在自催化钯浴之前的额外步骤中应用浸渍钯浴(前述活化溶液)，以延长自催化钯浴的寿命。
之后，在优选的实施方式中，漂洗表面并且随后，在上述活化钯浴中的预处理之后，使用上述化学(自催化)钯浴处理所述表面；另一种情况，可直接使用化学(自催化)钯浴处理表面无需活化钯浴中的预处理。
下面的实施例用于解释本发明的各个方面。
实施例
作为基板使用单面PCB(阵列尺寸61.8×113.8mm)。该阵列由两个单一卡(50×50mm)组成。整个铜厚度是30μm(+/-5μm)。引线键合可实施于所述基板的任何区域。
基础材料是日立MCL-E679FGB-(S)，FR4 18/80，300μm。
实施的镀敷顺序如下表所示：
表1A：在铜引线键合部分上镀纯钯(按照本发明)
Figure BPA0000175206960000071
Figure BPA0000175206960000081
表1B：使用浸渍工艺在铜焊盘上镀钯(对比例)
Figure BPA0000175206960000082
表2：在铜线键合部分上镀镍和纯钯
Figure BPA0000175206960000083
表3：在铜线键合部分上镀镍和钯-磷合金
Figure BPA0000175206960000084
Figure BPA0000175206960000091
表4：在铜线键合部分上镀镍、纯钯和金(对比例)
Figure BPA0000175206960000092
Figure BPA0000175206960000101
按照表1A/B-4使用的组分：
Figure BPA0000175206960000102
Figure BPA0000175206960000111
所实施的测试：
拉力测试
如表1A/B-4中所述沉积金属层之后，将这样镀敷的引线键合部分在165℃下在铜焊盘部分上与Heraeus Maxsoft铜线(直径0.8μm)键合。使用具有Microenvironment Copper Kit的Kulicke and Soffa Max Ultra焊线机实施该铜键合过程。成形期间成形气体(5％/95％H2/N2)保护无空气球(free-air ball)。键合工具是具有1.25密耳的倒圆直径(chamber diameter，CD)和60°内倒角(innerchamfer angle，ICA)的Kulicke and Soffa CuPRAplus毛细管。键合是在超声(US)处理存在下进行的。
键合前使用等离子蚀刻工艺清洁钯表面，其是本领域熟知的。
在Dage4000Tp拉力测试仪上实施拉力测试。
测试结果如表5所示。测试了10个键合样品，且平均值提供于表5中。测试“表号”指示按照上面的表1A/B-4的镀敷顺序。获得的金属层的厚度以μm提供。US处理时间在90到140秒(s)之间变化。相应的拉力强度值以g拉力提供于表5中。
US(超声)处理时间
表5：所得的平均拉力强度值的结果
Figure BPA0000175206960000112
*对比例
从表5的数据明显看出样品号1A的拉力强度值在所有US处理时间下是最高的。拉力强度值越高，基板和铜线之间的键合越好，这是所期望的。低于2.1的键合强度值被认为不足以在基板和铜线之间形成可靠的键合，2.2到3.9的值被认为是可接受的。4.0或更高的值被认为是良好的。当使用浸渍钯镀敷工艺(样品号1B)镀敷钯层时，键合性能相比本发明的化学(自催化)镀敷工艺要差得多。
样品号1的所有值均高于5，也就是非常好。该实施例对应于本发明的特别优选的实施方案，其中钯层是纯钯层并且直接沉积到铜线键合部分上而没有中间的镍或镍合金层。
样品号2和3也是按照本发明的方法获得的并且在基板(更具体的，引线键合部分)和钯层之间包含附加的镍层。获得的平均拉力强度值低于按照优选实施方案的值，但仍是可接受的。
按照相应于对比例的实验，增加金层(样品号4)作为组合件的最终层意外地导致得到差得多的平均拉力强度值。因此，键合性能差。八个值中的三个被认为是“失败的”，八个中的五个被认为是“可接受的”并且没有值被认为是非常好的。
至今，金被认为是对于引线键合而言最合适的层。
因此，借助本发明的方法提供了一种层序列，在所获得的平均拉力强度值方面该层序列提供了非常好的铜线键合结果，其表明铜线与基板的表面修饰(surface finishing)之间的良好键合。
对按照表1A(化学(自催化)镀敷工艺，本发明)和1B(浸渍镀敷工艺，对比例)的镀敷工艺制备的样品实施额外的键合测试，以确定本发明工艺产生优异的键合性能。
对下列四个样品(具有两种不同的钯层厚度)测试了铜线可键合性(bondability)。
表1A：
化学镀钯(自催化)90nm(钯厚度90nm)
化学镀钯(自催化)150nm(钯厚度150nm)
表1B：
浸渍钯100nm，(钯厚度100nm)
浸渍钯150nm，(钯厚度150nm)
测试条件是“原样(as received)”状态(刚刚镀完未进行热处理)和150℃下热处理4小时之后。使用化学(自催化)镀钯的所有样品在两种测试条件下与铜线都是可键合的。使用浸渍镀钯的样品中只有样品“浸渍钯150nm”在“原样”条件下是可键合的。样品“浸渍钯100nm”在两种测试条件下都是不可键合的，样品“浸渍钯150nm”在“4h150℃”热处理之后是不可键合的。引线键合过程期间样品失败。所以没有引线可固定到表面上并且不可能有引线拉力测试。另外使用浸渍镀钯的两个样品在热处理之后都表现出强变色。
键合设备和参数与上面描述的一样，除非另外声明采用下面详细给出的参数设置。使用的铜线：Hereaus Cu Maxsoft，Ф＝20μm，断裂载荷7.3g，温度：200℃
表6：对于引线键合测试使用的参数设置
参数 球形键合 楔形键合
US功率[mAmps] 140 170
US时间[ms] 13 12
键合力[g] 30 35
CV[mils/ms] 0.20 0.40
每个样品实施30次牵拉。拉力测试验收标准(Pulltest Acceptance Criteria)按照DVS2811推荐标准：最小断裂力＞引线B.载荷的50％(＞4.95g)；变异系数CV(标准差(std.dev.)与平均值的比率)＜0.15(＜15％)。键合前，所有样品使用氩等离子预处理10分钟。
表7：表面修饰的拉力强度(g)；老化＝原样
Figure BPA0000175206960000131
表8：表面修饰的拉力强度(g)；老化＝4h150℃
Figure BPA0000175206960000141
从表7和8明显看出，通过化学(自催化)钯沉积获得的钯层上的键合性能高于那些通过浸渍沉积获得的。老化后和100nm厚度的浸渍镀钯层是根本不能键合的，并且因此不适于按照本发明的键合工艺。

Claims (15)

1.在基板上形成铜线的方法，所述基板具有至少一个由铜或铜合金构成的引线键合部分，所述方法包括步骤：
(i)提供基板，其具有至少一个由铜或铜合金构成的引线键合部分；
(ii)在所述至少一个引线键合部分上形成钯或钯合金层，其中由包含如下成分的化学(自催化)镀钯浴沉积所述钯：
-钯离子源；
-络合剂；
-还原剂；以及随后
(iii)将铜线键合到所述钯或钯合金层上。
2.如权利要求1所述的方法，其中按照步骤(ii)的所述钯或钯合金层直接形成到所述铜或铜合金键合部分上。
3.如前述权利要求中任一项所述的方法，其中所述钯或钯合金层具有0.05-5.0μm的厚度。
4.如前述权利要求中任一项所述的方法，其中所述钯或钯合金层具有0.1-0.5μm的厚度。
5.如前述权利要求中任一项所述的方法，其中所述钯层是钯含量超过99.0wt％的纯钯层。
6.如前述权利要求中任一项所述的方法，其中所述钯层是钯含量超过99.9wt％的纯钯层。
7.如前述权利要求中任一项所述的方法，其中所述钯层是包含90.0-99.9wt％的钯和0.1-10.0wt％的磷的钯合金层。
8.如前述权利要求中任一项所述的方法，其中所述还原剂是甲酸或它的盐。
9.如前述权利要求中任一项所述的方法，其中铜线是涂覆有金或钯层的纯铜或铜合金线。
10.如权利要求9所述的方法，其中所述钯或金涂层具有5-50nm的厚度。
11.如前述权利要求中任一项所述的方法，其中在步骤(ii)之前，所述至少一个引线键合部分通过浸入含有钯离子的溶液中活化。
12.一种层组合件，其包括：
(i)至少一个由铜或铜合金构成的引线键合部分层；以及直接沉积在其上的
(ii)厚度0.05-0.5μm的钯或钯合金层；以及
(iii)键合到所述钯或钯合金层上的铜线。
13.可由权利要求1-11中任一项的方法制得的权利要求12所述的层组合件。
14.一种印刷电路板，具有权利要求12和13所述的层组合件，以及另外的用于连接外部部件与所述印刷电路板的焊接部分。
15.一种集成电路，具有权利要求12和13所述的层组合件。
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