CN103247594A - 应力降低装置 - Google Patents

应力降低装置 Download PDF

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CN103247594A
CN103247594A CN2012102096298A CN201210209629A CN103247594A CN 103247594 A CN103247594 A CN 103247594A CN 2012102096298 A CN2012102096298 A CN 2012102096298A CN 201210209629 A CN201210209629 A CN 201210209629A CN 103247594 A CN103247594 A CN 103247594A
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layer
metal
drop low
dielectric layer
metal structure
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吕盈缔
陈文昭
毛明瑞
蔡冠智
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种应力降低装置。该应力降低装置包括：在衬底上方形成的金属结构；在衬底上方形成的金属间介电层，其中，金属结构的下部嵌入金属间介电层；以及在金属结构上方形成的倒杯形应力降低层，其中，金属结构的上部嵌入倒杯形应力降低层。

Description

应力降低装置
技术领域
本发明涉及半导体制造，具体而言，涉及应力降低装置。
背景技术
半导体产业由于各种电子元件(诸如晶体管、二极管、电阻器，电容器等)的集成密度的不断提高而经历了快速增长。在大多数情况下，这种集成密度的提高源于最小部件尺寸的不断减小，从而容许更多的元件集成到给定的面积中。最近随着甚至更小的电子器件的需求在增长，在半导体管芯中集成电感器的需要也在增长。可以在半导体器件衬底的表面上形成在平行于衬底表面的平面中形成的螺旋形状的电感器。
随着半导体技术的发展，嵌入在半导体器件中的电感器可以通过采用超厚金属(UTM)工艺由铜形成。铜电感器已成为进一步降低半导体芯片的功率损耗的有效备选物。在铜电感器中，可以通过采用镶嵌工艺形成电感器的铜结构。在该技术中，图案化绝缘层以形成沟槽。在图案化之后，可以在沟槽上沉积阻挡层。可以在阻挡层上沉积晶种层以提供更好的铜粘着性。此外，通过电化学镀工艺，用金属材料(诸如铜)填充沟槽以形成金属结构，诸如金属线和通孔。
镶嵌工艺可以分成两类，即单镶嵌工艺和双镶嵌工艺。在单镶嵌技术中，金属通孔及其邻近的金属线可以具有不同的工艺步骤。结果，每个步骤都可能需要化学机械平坦化工艺来清洁表面。相反，在双镶嵌技术中，金属通孔及其邻近的金属线可以形成在单个沟槽内。结果，在双镶嵌工艺中需要两个电介质图案化工艺和一个CMP工艺来形成金属通孔及其邻近的金属线。
在铜电感器中，电感器的铜结构可以被介电层封闭。在与铜结构的角部和其邻近的介电层之间的界面邻近的区域中可能存在应力集中。结果，在与铜结构邻近的区域中可能发生电介质碎裂。这种电介质碎裂可能导致不可靠的半导体器件。
发明内容
为了解决上述问题，一方面，本发明提供了一种装置，包括：金属结构，形成在衬底上方；金属间介电层，形成在所述衬底上方，其中，所述金属结构的下部嵌入所述金属间介电层；以及倒杯形应力降低层，形成在所述金属结构上方，其中，所述金属结构的上部嵌入所述倒杯形应力降低层。
在所述的装置中，所述倒杯形应力降低层包括：第一部分，形成在所述金属间介电层上，其中，所述金属结构的上部被所述倒杯形应力降低层的所述第一部分包围；以及第二部分，形成在所述金属结构的上端以及所述倒杯形应力降低层的所述第一部分上。
在所述的装置中，所述倒杯形应力降低层的所述第一部分的厚度为约1000
Figure BDA00001791540400021
在所述的装置中：所述倒杯形应力降低层的所述第一部分由氮化硅形成；以及所述倒杯形应力降低层的所述第二部分由氮化硅形成。
在所述的装置中，所述金属结构由铜形成。
所述的装置还包括：金属通孔，形成在所述金属结构的下方。
在所述的装置中，所述金属结构通过采用单镶嵌工艺形成。
另一方面，本发明还提供了一种器件，包括：衬底，包含硅；介电层，形成在所述衬底上方；第一金属层，形成在所述介电层上；第一蚀刻终止层，形成在所述第一金属层上方；第一金属间介电层，形成在所述第一蚀刻终止层上；金属通孔，形成在所述第一金属间介电层中；第二蚀刻终止层，形成在所述第一金属间介电层上；第二金属间介电层，形成在所述第二蚀刻终止层上；应力降低层，形成在所述第二金属间介电层上；金属结构，包括：被所述第二蚀刻终止层包围的下部、被所述第二金属间介电层包围的中部、以及被所述应力降低层包围的上部；以及第三蚀刻终止层，形成在所述应力降低层以及所述金属结构的上端上。
所述的器件还包括形成在所述第一金属层中的第一金属线。
在所述的器件中，所述金属通孔电连接至所述金属结构。
在所述的器件中，所述金属结构由铜形成；以及所述金属通孔由铜形成。
在所述的器件中，所述金属结构通过采用单镶嵌工艺形成；以及所述金属通孔通过采用所述单镶嵌工艺形成。
在所述的器件中，所述应力降低层的厚度为约1000
Figure BDA00001791540400031
在所述的器件中，所述第三蚀刻终止层由与所述应力降低层相同的材料形成。
又一方面，本发明提供了一种方法，包括：在衬底上方形成第一金属间介电层；在所述第一金属间介电层上形成应力降低层；在所述应力降低层上形成第二金属间介电层；图案化所述第一金属间介电层、所述应力降低层和所述第二金属间介电层以形成开口；将金属材料填充到所述开口中以形成金属结构；对所述第二金属间介电层的表面实施化学机械平坦化工艺；以及在所述应力降低层以及所述金属结构的上端上形成蚀刻终止层。
所述的方法还包括：通过采用电化学镀工艺将所述金属材料填充到所述开口中。
所述的方法还包括：使用与所述应力降低层相同的材料形成所述蚀刻终止层。
所述的方法还包括：在所述金属结构的下方形成金属通孔，其中，将所述金属通孔电连接至所述金属结构。
所述的方法还包括：使用铜形成所述金属通孔；以及使用铜形成所述金属结构。
所述的方法还包括：采用单镶嵌工艺形成所述金属通孔；以及采用所述单镶嵌工艺形成所述金属结构。
附图说明
为了更充分地理解本发明及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1示出根据实施例的应力降低装置的剖视图；
图2示出具有图1中示出的应力降低装置的半导体器件的剖视图；
图3示出根据实施例的在沟槽图案化之后的半导体器件的剖视图；
图4示出根据实施例的在电化学镀工艺之后的半导体器件的剖视图；
图5示出根据实施例的在化学机械平坦化工艺之后的半导体器件的剖视图；以及
图6示出根据实施例的具有倒杯形应力降低层的半导体器件的剖视图。
除非另有说明，不同附图中的相应的标号和符号通常指相应的部件。绘制附图以清楚地示出各个实施例的相关方面而不必按比例绘制。
具体实施方式
在下面详细地论述本发明实施例的制造和使用。然而，应当理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅仅是制造和使用本发明的示例性具体方式，而不是用于限制本发明的范围。
将参考具体环境中的实施例即应力降低装置来描述本发明。但是，本发明也可以适用于各种半导体器件。
图1示出根据实施例的应力降低装置的剖视图。为了简明，仅示出半导体器件的相关部分。将在下面参考图2论述具有应力降低装置的半导体器件的详细剖视图。应力降低装置100包括倒杯形层(inverted cup shapedlayer)102、金属结构104、金属间介电(IMD)层106。根据实施例，IMD层106可以由诸如氧化物等的介电材料形成。倒杯形层102可以由氮化硅等形成。金属结构104可以由铜等形成。根据实施例，可以通过采用超厚金属(UTM)工艺形成金属结构104。具体而言，金属结构104可以是通过UTM工艺形成的嵌入式电感器的一部分。
如图1所示，倒杯形层102用作覆盖金属结构104的上端的罩盖(cap)。更具体地，金属结构104的左上角和右上角通过倒杯形层102加以保护。具有倒杯形层102的一个有利特征是围绕上角部的介电材料有助于降低应力从而阻止金属结构104和IMD层106碎裂。
图2示出具有图1中示出的应力降低装置的半导体器件的剖视图。如图2所示，在半导体管芯200上形成应力降低装置。半导体管芯200包括衬底202。衬底202可以是硅衬底。可选地，衬底202可以是绝缘体上硅衬底。衬底202还可以包括各种电路(未示出)。在衬底202上形成的电路可以是适合于特定应用的任何类型的电路。
根据实施例，电路可以包括各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件，诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等。可以将电路互连起来以执行一个或多个功能。功能可以包括存储器结构、处理结构、传感器、放大器、功率分配、输出/输入电路等。本领域普通技术人员将理解提供以上实例仅用于进一步解释本发明的应用的说明性目的而不意为以任何方式限制本发明。
在衬底202顶部上形成层间介电层204。层间介电层204可以由例如低K介电材料诸如氧化硅形成。可以通过本领域已知的任何合适的方法诸如旋涂、化学汽相沉积(CVD)以及等离子体增强化学汽相沉积(PECVD)形成层间介电层204。还应当注意到，本领域技术人员将了解层间介电层204还可以包括多个介电层。
在层间介电层204上方形成底部金属化层206a。如图2所示，底部金属化层206a可以包含金属线208a。金属线208a由金属材料诸如铜、铜合金、铝、银、金和它们的任何组合形成。可以通过任何合适的技术(例如沉积、镶嵌等)形成金属化层206a和206b。通常，使用一个或多个金属间介电层和相关金属化层将衬底202中的电路彼此互连起来以形成功能电路并进一步提供外部电路连接。
在底部金属化层206a上方形成顶部金属化层206b。如图2所示，在顶部金属化层206b中嵌有顶部金属线208b。具体而言，顶部金属线208b提供了用于半导体器件200的电路的导电通道。顶部金属线208b可以由金属材料诸如铜、铜合金、铝、银、金和它们的任何组合形成。可以通过合适的技术诸如CVD形成顶部金属线208b。可选地，可以通过溅射、电镀等形成顶部金属连接件214。
应当注意到，虽然图2示出了底部金属化层206a和顶部金属化层206b，但本领域技术人员应该了解，在底部金属化层206a和顶部金属化层206b之间形成一个或多个金属间介电层(未示出)和相关金属化层(未示出)。具体地，在底部金属化层206a和顶部金属化层206b上方形成的层可以由介电材料(例如，极低k介电材料)和导电材料(例如，铜)的交替层形成。
可以通过不同的制造工艺诸如超厚金属(UTM)技术形成位于顶部金属化层206b上方的层。如图2中所示，金属结构基本上可以比金属化层中的金属结构更厚和更宽。下面提供更多细节。
在衬底202上方形成第一蚀刻终止层(ESL)210。第一ESL层210可以由与邻近层具有不同蚀刻选择性的介电材料形成。根据实施例，第一ESL层210由非有机材料诸如氮化硅、碳氮化硅等形成。可以通过任何合适的技术诸如CVD或者PECVD技术形成第一ESL层210。使用第一ESL层210来阻止蚀刻剂损伤第一ESL层210下方的层(例如，顶部金属化层206b)。
在顶部金属化层206b上形成第一金属间介电层(IMD)212。第一IMD层212可以由介电材料诸如氧化物等形成。可以通过采用PECVD技术或者高密度等离子体化学汽相沉积(HDPCVD)等形成第一IMD层212。
在第一IMD层212的顶部上形成第二ESL层216。第二ESL层216可以与第一ESL层210相似，并因此为了避免不必要的重复而不作更详细的论述。如图2所示，在第一IMD层212和第一ESL层210的开口中形成金属通孔214。根据实施例，金属通孔214可以由铜形成。为了简明，在整个说明书中，金属通孔214可以可选地被称为铜通孔214。
在铜通孔214的顶部上形成金属结构218。根据实施例，金属结构218可以由铜形成。为了简明，在整个说明书中，金属结构218可以可选地被称为铜结构218。铜结构218可以被第二ESL层216、第二IMD层222以及倒杯形层220包围。具体而言，铜结构218的下部嵌入第二IMD层222以及铜结构218的顶部嵌入倒杯形层220。此外，倒杯形层220覆盖铜结构218的上端。倒杯形层220由非有机材料诸如氮化硅、碳氮化硅等形成。
在下面将参考图3至图6论述倒杯形层220的形成细节。
图3至图6示出了根据实施例的形成铜结构218的单镶嵌工艺的中间阶段。但是，作为本领域普通技术人员将了解到，下面论述的铜形成工艺仅仅是示例性工艺而不意为限制当前的实施例。可以可选地采用其他铜形成工艺，诸如双镶嵌工艺。此外，可以采用任何合适的铜形成工艺，并且所有这些工艺预期全部都包括在所论述的实施例的范围内。
图3示出根据实施例在沟槽图案化之后的半导体器件的剖视图。半导体器件包含铜通孔214。以单镶嵌工艺形成铜通孔214的方法是本领域公知的，并因此为了避免不必要的重复在本文不作论述。与如2中示出的层结构对比，图3中示出的半导体器件包括应力降低层304和在应力降低层304顶部上形成的第三IMD层302。为了形成图2中示出的铜结构218，通过去除如图3中示出的第二ESL层216、第二IMD层222、应力降低层304以及第三IMD层302的相应部分而形成沟槽。图3中示出的沟槽可以通过公知的蚀刻技术形成，为了避免不必要的重复在本文中对此不作论述。
图4示出根据实施例的在电化学镀工艺之后的半导体器件的剖视图。如图3中所示，可以图案化第二ESL层216、第二IMD层222、应力降低层304以及第三IMD层302以形成开口。在图案化之后，可以在开口上沉积薄阻挡层(未示出)。可以在薄阻挡层的顶部上沉积铜晶种层(未示出)。应用铜晶种层以提供在下面的材料上的更好的铜粘着性。此外，在后续电镀工艺期间，铜晶种层可以作为催化材料层起作用。可以应用电化学镀工艺来填充开口从而形成金属结构218，将其电连接至铜通孔214。
图5示出根据实施例的在化学机械平坦化(CMP)工艺之后的半导体器件的剖视图。在电化学镀工艺之后，应用CMP工艺来去除多余的铜并对表面进行抛光。如图5所示，在CMP工艺之后，可以去除第三IMD层302(未示出，但在图4中示出)以及一部分应力降低层304。将应力降低层304在CMP工艺之后的厚度定义为H。根据实施例，H是约1000
Figure BDA00001791540400071
图6示出根据实施例的具有倒杯形应力降低层的半导体器件的剖视图。在CMP工艺之后，在铜表面的顶部上以及应力降低层的表面上形成又一个ESL层602。应当注意到，ESL层602可以由与应力降低层304(在图5中示出)相同的材料(例如，SiN)形成。结果，将ESL层602和应力降低层304合并成一个整体，其具有如图6中示出的倒杯形状。图6中示出的倒杯形层有助于降低铜结构218和IMD层222之间的应力。总之，具有倒杯形层602的一个有利特征是铜结构218的上角部被倒杯形层602覆盖。结果，降低了第二IMD层222中的碎裂。
尽管已经详细地论述了本发明的实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明的精神和范围的情况下，在其中进行各种改变、替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明将很容易地理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (10)

1.一种装置，包括：
金属结构，形成在衬底上方；
金属间介电层，形成在所述衬底上方，其中，所述金属结构的下部嵌入所述金属间介电层；以及
倒杯形应力降低层，形成在所述金属结构上方，其中，所述金属结构的上部嵌入所述倒杯形应力降低层。
2.根据权利要求1所述的装置，其中，所述倒杯形应力降低层包括：
第一部分，形成在所述金属间介电层上，其中，所述金属结构的上部被所述倒杯形应力降低层的所述第一部分包围；以及
第二部分，形成在所述金属结构的上端以及所述倒杯形应力降低层的所述第一部分上。
3.根据权利要求2所述的装置，其中，所述倒杯形应力降低层的所述第一部分的厚度为约1000
Figure FDA00001791540300011
4.根据权利要求2所述的装置，其中：
所述倒杯形应力降低层的所述第一部分由氮化硅形成；以及
所述倒杯形应力降低层的所述第二部分由氮化硅形成。
5.根据权利要求1所述的装置，其中，所述金属结构由铜形成。
6.根据权利要求1所述的装置，还包括：
金属通孔，形成在所述金属结构的下方。
7.根据权利要求1所述的装置，其中，所述金属结构通过采用单镶嵌工艺形成。
8.一种器件，包括：
衬底，包含硅；
介电层，形成在所述衬底上方；
第一金属层，形成在所述介电层上；
第一蚀刻终止层，形成在所述第一金属层上方；
第一金属间介电层，形成在所述第一蚀刻终止层上；
金属通孔，形成在所述第一金属间介电层中；
第二蚀刻终止层，形成在所述第一金属间介电层上；
第二金属间介电层，形成在所述第二蚀刻终止层上；
应力降低层，形成在所述第二金属间介电层上；
金属结构，包括：
下部，被所述第二蚀刻终止层包围；
中部，被所述第二金属间介电层包围；以及
上部，被所述应力降低层包围；以及
第三蚀刻终止层，形成在所述应力降低层以及所述金属结构的上端上。
9.一种方法，包括：
在衬底上方形成第一金属间介电层；
在所述第一金属间介电层上形成应力降低层；
在所述应力降低层上形成第二金属间介电层；
图案化所述第一金属间介电层、所述应力降低层和所述第二金属间介电层以形成开口；
将金属材料填充到所述开口中以形成金属结构；
对所述第二金属间介电层的表面实施化学机械平坦化工艺；以及
在所述应力降低层以及所述金属结构的上端上形成蚀刻终止层。
10.根据权利要求9所述的方法，还包括：
在所述金属结构的下方形成金属通孔，其中，将所述金属通孔电连接至所述金属结构。
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