CN103229240B - 用于共享集成电路装置中的内部电源的方法和设备 - Google Patents
用于共享集成电路装置中的内部电源的方法和设备 Download PDFInfo
- Publication number
- CN103229240B CN103229240B CN201180056159.XA CN201180056159A CN103229240B CN 103229240 B CN103229240 B CN 103229240B CN 201180056159 A CN201180056159 A CN 201180056159A CN 103229240 B CN103229240 B CN 103229240B
- Authority
- CN
- China
- Prior art keywords
- regulator
- memory device
- enable
- terminal
- chip package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/221—Structures or relative sizes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US41643710P | 2010-11-23 | 2010-11-23 | |
| US61/416437 | 2010-11-23 | ||
| PCT/CA2011/000528 WO2012068664A1 (en) | 2010-11-23 | 2011-05-03 | Method and apparatus for sharing internal power supplies in integrated circuit devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103229240A CN103229240A (zh) | 2013-07-31 |
| CN103229240B true CN103229240B (zh) | 2015-05-20 |
Family
ID=46064267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201180056159.XA Expired - Fee Related CN103229240B (zh) | 2010-11-23 | 2011-05-03 | 用于共享集成电路装置中的内部电源的方法和设备 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US8625352B2 (https=) |
| EP (1) | EP2643835A1 (https=) |
| JP (1) | JP5623653B2 (https=) |
| KR (1) | KR20130140782A (https=) |
| CN (1) | CN103229240B (https=) |
| WO (1) | WO2012068664A1 (https=) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8913443B2 (en) * | 2011-09-19 | 2014-12-16 | Conversant Intellectual Property Management Inc. | Voltage regulation for 3D packages and method of manufacturing same |
| US9318186B1 (en) * | 2014-12-31 | 2016-04-19 | Nanya Technology Corporation | DRAM wordline control circuit, DRAM module and method of controlling DRAM wordline voltage |
| TWI560718B (en) * | 2015-03-27 | 2016-12-01 | Silicon Motion Inc | Data storage device and encoding method thereof |
| JP7685349B2 (ja) * | 2021-03-18 | 2025-05-29 | キオクシア株式会社 | 半導体記憶装置 |
| US11816357B2 (en) * | 2021-08-12 | 2023-11-14 | Micron Technology, Inc. | Voltage regulation distribution for stacked memory |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1190262A (zh) * | 1996-05-30 | 1998-08-12 | 东芝株式会社 | 单片混合型半导体集成电路器件及其检查方法 |
| US6031760A (en) * | 1997-07-29 | 2000-02-29 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of programming the same |
| JP2002312306A (ja) * | 2001-02-08 | 2002-10-25 | Samsung Electronics Co Ltd | 半導体メモリ装置及びメモリシステム |
| CN1838409A (zh) * | 2005-01-05 | 2006-09-27 | 三星电子株式会社 | 具有不同类型的多芯片封装的存储模块 |
| JP2006286048A (ja) * | 2005-03-31 | 2006-10-19 | Toshiba Corp | 半導体記憶装置 |
| US20080002490A1 (en) * | 2006-06-30 | 2008-01-03 | Hynix Semiconductor Inc. | Semiconductor memory device with internal voltage generator and method for driving the same |
| CN101290896A (zh) * | 2007-04-19 | 2008-10-22 | 矽品精密工业股份有限公司 | 可供堆叠的半导体装置及其制法 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5197029A (en) * | 1991-02-07 | 1993-03-23 | Texas Instruments Incorporated | Common-line connection for integrated memory array |
| US6750527B1 (en) * | 1996-05-30 | 2004-06-15 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having a plurality of wells, test method of testing the semiconductor integrated circuit device, and test device which executes the test method |
| JP2003036673A (ja) * | 2001-07-24 | 2003-02-07 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP2003132679A (ja) * | 2001-10-23 | 2003-05-09 | Hitachi Ltd | 半導体装置 |
| US7466160B2 (en) * | 2002-11-27 | 2008-12-16 | Inapac Technology, Inc. | Shared memory bus architecture for system with processor and memory units |
| JP4419049B2 (ja) * | 2003-04-21 | 2010-02-24 | エルピーダメモリ株式会社 | メモリモジュール及びメモリシステム |
| JP4068616B2 (ja) * | 2003-12-26 | 2008-03-26 | エルピーダメモリ株式会社 | 半導体装置 |
| KR100626385B1 (ko) * | 2004-09-13 | 2006-09-20 | 삼성전자주식회사 | 반도체 메모리 장치 및 그것을 포함하는 멀티칩 패키지 |
| US20070170979A1 (en) * | 2005-11-25 | 2007-07-26 | Giovanni Campardo | Charge pump systems and methods |
| JP2007180087A (ja) * | 2005-12-27 | 2007-07-12 | Seiko Epson Corp | 集積回路装置 |
| US7639540B2 (en) * | 2007-02-16 | 2009-12-29 | Mosaid Technologies Incorporated | Non-volatile semiconductor memory having multiple external power supplies |
| JP2008300469A (ja) * | 2007-05-30 | 2008-12-11 | Sharp Corp | 不揮発性半導体記憶装置 |
| CN101919145B (zh) | 2007-12-21 | 2013-07-17 | 桑迪士克科技股份有限公司 | 可自配置的多调压器专用集成电路核电力输送 |
| KR101542353B1 (ko) | 2007-12-21 | 2015-08-06 | 샌디스크 테크놀로지스, 인코포레이티드 | Asic 코어를 위한 다중 레귤레이터 전력 전달 시스템 |
| US7894230B2 (en) | 2009-02-24 | 2011-02-22 | Mosaid Technologies Incorporated | Stacked semiconductor devices including a master device |
| US8400781B2 (en) * | 2009-09-02 | 2013-03-19 | Mosaid Technologies Incorporated | Using interrupted through-silicon-vias in integrated circuits adapted for stacking |
-
2011
- 2011-05-03 JP JP2013540186A patent/JP5623653B2/ja not_active Expired - Fee Related
- 2011-05-03 US US13/099,791 patent/US8625352B2/en active Active
- 2011-05-03 WO PCT/CA2011/000528 patent/WO2012068664A1/en not_active Ceased
- 2011-05-03 EP EP11843041.2A patent/EP2643835A1/en not_active Withdrawn
- 2011-05-03 CN CN201180056159.XA patent/CN103229240B/zh not_active Expired - Fee Related
- 2011-05-03 KR KR1020137015142A patent/KR20130140782A/ko not_active Withdrawn
-
2014
- 2014-01-06 US US14/148,336 patent/US9236095B2/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1190262A (zh) * | 1996-05-30 | 1998-08-12 | 东芝株式会社 | 单片混合型半导体集成电路器件及其检查方法 |
| US6031760A (en) * | 1997-07-29 | 2000-02-29 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of programming the same |
| JP2002312306A (ja) * | 2001-02-08 | 2002-10-25 | Samsung Electronics Co Ltd | 半導体メモリ装置及びメモリシステム |
| CN1838409A (zh) * | 2005-01-05 | 2006-09-27 | 三星电子株式会社 | 具有不同类型的多芯片封装的存储模块 |
| JP2006286048A (ja) * | 2005-03-31 | 2006-10-19 | Toshiba Corp | 半導体記憶装置 |
| US20080002490A1 (en) * | 2006-06-30 | 2008-01-03 | Hynix Semiconductor Inc. | Semiconductor memory device with internal voltage generator and method for driving the same |
| CN101290896A (zh) * | 2007-04-19 | 2008-10-22 | 矽品精密工业股份有限公司 | 可供堆叠的半导体装置及其制法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103229240A (zh) | 2013-07-31 |
| US8625352B2 (en) | 2014-01-07 |
| US20140119136A1 (en) | 2014-05-01 |
| HK1186569A1 (en) | 2014-03-14 |
| KR20130140782A (ko) | 2013-12-24 |
| JP2014501016A (ja) | 2014-01-16 |
| US9236095B2 (en) | 2016-01-12 |
| WO2012068664A1 (en) | 2012-05-31 |
| JP5623653B2 (ja) | 2014-11-12 |
| EP2643835A1 (en) | 2013-10-02 |
| US20120127798A1 (en) | 2012-05-24 |
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Ref country code: HK Ref legal event code: DE Ref document number: 1186569 Country of ref document: HK |
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| C53 | Correction of patent of invention or patent application | ||
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Address after: Ontario, Canada Applicant after: Examine Vincent Zhi Cai management company Address before: Ontario, Canada Applicant before: Mosaid Technologies Inc. |
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| COR | Change of bibliographic data |
Free format text: CORRECT: APPLICANT; FROM: MOSAID TECHNOLOGIES INC. TO: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. |
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