CN103165531A - 管芯结构及其制造方法 - Google Patents

管芯结构及其制造方法 Download PDF

Info

Publication number
CN103165531A
CN103165531A CN2012101194679A CN201210119467A CN103165531A CN 103165531 A CN103165531 A CN 103165531A CN 2012101194679 A CN2012101194679 A CN 2012101194679A CN 201210119467 A CN201210119467 A CN 201210119467A CN 103165531 A CN103165531 A CN 103165531A
Authority
CN
China
Prior art keywords
substrate
otch
tube cores
width
tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012101194679A
Other languages
English (en)
Other versions
CN103165531B (zh
Inventor
林俊成
王英达
郭立中
卢思维
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN103165531A publication Critical patent/CN103165531A/zh
Application granted granted Critical
Publication of CN103165531B publication Critical patent/CN103165531B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/0557Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1418Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

提供了一种具有沿着侧壁的凸缘的管芯以及形成该管芯的方法。还提供了一种封装该管芯的方法。通过形成具有第一宽度的第一切口,以及然后在第一切口内形成第二切口,从而使得第二切口具有小于第一宽度的第二宽度,切割衬底(诸如,加工晶圆)。第二切口延伸穿过衬底,从而切割衬底。第一宽度和第二宽度之间的宽度差形成沿着管芯侧壁的凸缘。可以在衬底(例如,插件)上放置管芯,以及可以在管芯和衬底之间放置底部填充物。凸缘阻止或减少在邻近管芯之间向上吸引底部填充物的距离。可以在衬底上方形成模塑料。本发明提供了管芯结构及其制造方法。

Description

管芯结构及其制造方法
技术领域
本发明涉及半导体器件,具体而言,涉及管芯结构及其制造方法。
背景技术
半导体器件用于多种电子应用和其他应用。半导体器件包括形成在半导体晶圆上的集成电路,通过在半导体晶圆上方沉积许多类型的材料薄膜并且使材料薄膜图案化从而形成集成电路。可以对半导体晶圆进行切割以形成独立的管芯。
可以将管芯安装在另一个衬底(诸如,插件)上。将底部填充材料放置在管芯和另一衬底之间从而提供结构支撑并且保护其不受环境污染。在多芯片封装件中,可以彼此邻近放置多个管芯。在这些情况下,毛细力可以将邻近管芯之间的底部填充材料向上吸至管芯的表面。可以实施模塑(molding)步骤以形成包围独立的管芯的模塑料。可以从管芯侧的顶部部分地去除模塑料从而暴露出管芯的上表面。
发明内容
一方面,本发明提供了一种方法,包括:提供衬底;在第一区和第二区之间形成第一切口,所述第一切口具有第一宽度;以及在所述第一切口内形成第二切口,所述第二切口具有小于所述第一宽度的第二宽度,从而形成凸缘,所述第二切口延伸穿过所述衬底,从而将所述衬底切割成单独的管芯。
所述的方法还包括在形成所述第二切口之前将所述衬底放置在载带上。
在所述的方法中,通过导电凸块将所述衬底接合至所述载带。
所述的方法,还包括:将一个或多个所述管芯放置到第二衬底上;以及在一个或多个所述管芯和所述第二衬底之间放置底部填充物,所述底部填充物的上表面位于所述凸缘处。
在所述的方法中,所述第二衬底包括插件。
所述的方法还包括在位于邻近管芯之间的所述底部填充物的上方形成模塑料。
所述的方法还包括减薄所述模塑料。
在所述的方法中,所述凸缘具有约5μm至约200μm的宽度。
另一方面,本发明还提供了一种方法,包括:在衬底上放置多个管芯,所述管芯中的至少一个具有沿着侧壁形成的凸缘;在所述多个管芯和所述衬底之间放置底部填充物,所述底部填充物在所述多个管芯中的邻近管芯之间延伸;以及在位于所述多个管芯中的邻近管芯之间的所述底部填充物的上方放置模塑料。
所述的方法还包括将所述衬底分成多个元件,所述多个元件中至少之一具有两个或更多个管芯。
在所述的方法中,所述凸缘具有约5μm至约200μm的宽度。
所述的方法还包括减薄所述模塑料,从而暴露出所述多个管芯中至少之一。
又一方面,本发明提供了一种器件,包括:衬底;多个管芯,位于所述衬底上,所述多个管芯中的至少第一管芯具有沿着侧壁的凸缘;底部填充物,位于所述多个管芯和所述衬底之间;以及模塑料,位于所述多个管芯中的邻近管芯之间,所述底部填充物在所述多个管芯中的邻近管芯之间在所述模塑料和所述衬底之间延伸。
在所述的器件中,所述凸缘具有约5μm至约200μm的宽度。
在所述的器件中,所述多个管芯中至少之一的上表面被暴露出来。
在所述的器件中,所述衬底包括插件。
所述的器件还包括延伸穿过所述插件的一个或多个通孔。
在所述的器件中,自所述第一管芯的上表面到所述凸缘的距离是约50μm至约700μm。
在所述的器件中,所述多个管芯中至少之一的上表面被暴露出来。
在所述的器件中,所述底部填充物向上延伸至所述凸缘。
附图说明
为了更充分地理解本发明及其优点,现在将结合附图所进行的以下描述作为参考,其中:
图1至图7示出了制造半导体器件的各个中间阶段。
具体实施方式
在下面详细地论述实施例的制造和使用。然而,应当理解,本发明提供了许多可以在各种具体环境中实现的可应用的发明概念。所论述的具体实施例仅仅是制造及使用本发明的示例性具体方式,而不是用于限制本发明的范围。
在具体环境中描述了本文论述的实施例,即,将加工晶圆切割成独立的管芯并且将这些独立的管芯接合到另一衬底(诸如,插件)上。然而,提供这些实施例仅仅用于示例性目的,并且在其他实施例中可以使用本发明的各方面。此外,本文描述的工艺是简化的并且仅仅是示例性的,而非限制实施例或者权利要求的范围,并且为了说明和理解实施例而示出这些实例。
首先参考图1,根据实施例,示出了衬底102,在该衬底102上具有接合至载带(earrier tape)106的多个管芯区104。衬底102可以包括:例如,在其上形成有电路(未示出)的晶圆、插件(具有或者不具有有源/无源器件)、安装衬底、其组合等等。衬底102可以是体硅衬底、绝缘体上半导体(SOI)衬底、硅锗、锗、石英、蓝宝石、和/或玻璃等等。在实施例中,衬底102具有在其上形成的互连结构。一般地,互连结构包括一个或多个介电层、导电层(例如,金属化层)、以及通孔,起到将可以在衬底102上形成的各种电器件互连起来的作用。衬底102还可以包括通孔(TV)从而允许衬底102的相对面之间的和/或堆叠管芯之间的电互连。
衬底102示出了在切割形成单独的管芯之前的衬底。在图1中,线108示出了边界(例如,划线),可以在该边界处切割衬底102,从而限定管芯区104。还应当注意到示出五个第一划线108仅仅用于示例性目的,以及实际器件可以具有更多或更少的相应结构。管芯区104可以包括用于特定用途的任何合适的电路。
如图1中所示,衬底102安装在载体膜(诸如,载带106)上。通过第一导电元件112将衬底102连接至载带,该第一导电元件112可以由无铅焊料、共熔铅等等形成。在实施例中,载带106具有用于通过第一导电元件112将衬底102接合至载带106的粘合表面。在其他实施例中,在形成例如第一导电元件112之前可以接合衬底102。也可以使用其他类型的载体膜和/或载体衬底。
现在参考图2,根据实施例,在衬底102中形成第一切口220。在实施例中,使用锯来形成第一切口220,然而可以使用其他技术来形成第一切口220。例如,在其他实施例中,可以采用激光、蚀刻工艺等等来形成第一切口220。
如图2中所示出的,在实施例中,第一切口220部分延伸穿过衬底102。例如,在实施例中,对于厚度为约700μm的衬底,第一切口220可以具有约50μm至约700μm的深度。在另一实例中,第一切口220的深度可以是衬底厚度的约10%至约90%。在实施例中,第一切口220具有约50μm至约500μm的宽度。对于第一切口220,也可以使用更小或更大的其他宽度和深度。
现参考图3,第二切口322形成在第一切口220内并且延伸穿过衬底102的剩余部分。以这种方式,实施多个切割操作来将衬底102(参见图1和图2)切割成为多个管芯334。在实施例中,采用锯来形成第二切口322,然而可以使用其他技术来形成第二切口322。例如,在其他实施例中,可以采用激光、蚀刻工艺等等来形成第二切口322。在实施例中,第二切口322具有约10μm至约50μm的宽度。对于第二切口322,也可以使用更小或更大的其他宽度和深度。
如图3中所示,在实施例中,第二切口322窄于第一切口220。如将在下面更详细说明的,在衬底(诸如,插件)上放置管芯334,并且在管芯334和下面的衬底之间放置底部填充材料。当形成底部填充材料时,毛细力在邻近管芯334之间向上吸引底部填充材料,并且这种底部填充材料可以导致插件或其他衬底例如在固化工艺期间翘曲。
通过采用多个切割步骤形成不同宽度的切口,沿着管芯334的边缘形成凸缘(1edge)336。这些凸缘可以起到限制可以通过毛细力沿着管芯334的边缘向上吸引底部填充材料的距离的作用,这反过来可以减少下面的插件或其他衬底的翘曲。
在实施例中,凸缘336具有约5μm至约200μm的宽度。更小或更大的其他宽度也可以用于第一切口220。还应当注意到,底部填充物沿着管芯侧壁向上行进的距离可以由第一切口220的深度来控制。一般地,第一切口220越深,底部填充材料延伸得就越低。还应当注意到,可以根据底部填充材料的特性以及器件结构来调节凸缘336的尺寸。例如,如果底部填充材料更易受毛细力的影响,并且邻近管芯之间的间隔使得存在足够的毛细力,那么较大的凸缘是可取的。
图4示出了根据实施例的在将管芯334放置在第二衬底440上之后的管芯334。第二衬底440可以是例如插件、加工或未加工的半导体晶圆、封装衬底等等。在诸如图4中示出的实施例中,第二衬底440可以是硅晶圆、半导体衬底、玻璃、陶瓷、BT树脂、环氧树脂或者用于插件的另一衬底材料。在实施例中,第二衬底440可以包括一个或多个TV 442,从而提供管芯334和待在第二衬底440的相对表面上形成的电连接件之间的电连接,对此将在下面进行更详细的说明。将管芯334示出为相同的仅仅用于示例性目的。第二衬底440可以包括管芯、相同管芯、不同管芯、或其组合的任何合适的组合。
图4还示出了放置在管芯334和第二衬底440之间的底部填充材料444。底部填充材料444可以例如包括液体环氧树脂、可变形凝胶、硅橡胶等等,分布在管芯334和第二衬底440之间然后将其固化变硬。此外,这种底部填充材料444用于减少第一导电元件112中的碎裂并保护接点免受污染。
可以认为沿着管芯334的侧壁形成的凸缘336阻止或减小毛细力,从而降低底部填充材料444沿着管芯334的侧壁向上延伸的高度。
图5描述了模塑工艺之后的组装件(assembly)。可以在元件(例如,管芯334)上方形成密封件或者重叠模塑件(overmold)546从而保护元件免受环境和外部污染。在模塑操作中,在管芯334和第二衬底440的上方形成密封化合物。在压缩模塑工艺中,可以在压塑机中使用液体类型的热固性环氧树脂模塑料,可以将模塑料加热至使其变成更低粘性材料的升高的温度,并且在压缩下受力形成腔室,在该腔室中放置组装件,密封化合物包围管芯334和第二衬底440的管芯侧。
在使密封件546固化之后,如图6中所示,可以在顶部研磨操作过程中部分地去除密封件546从而暴露出位于第二衬底管芯侧上的管芯334的上表面。可以将管芯334的上表面暴露出来,例如,用于帮助散热。例如,在实施例中,可以将散热器或热散布机接合到管芯的上表面从而有助于冷却管芯334。
图6还示出了可以实施用于暴露出延伸至第二衬底440内的互连件(例如,TV 442)的背面减薄工艺。在与管芯334相对的面上实施背面减薄。可以通过物理研磨、化学蚀刻、及其组合等等实施减薄,直到互连件TV 442暴露在第二衬底440的底面上,如图6中所示。在背面减薄操作之后,作为非限制性实例,可以将第二衬底440减薄至厚度介于约30微米至约200微米之间。可以将第二衬底440减薄至100微米。
图7示出了根据实施例的沿着第二衬底440的背面形成的电连接件750。在图7中示出的实施例中,电连接件750包括形成在接触焊盘752上方的凸块或焊球,然而可以使用其他类型的电连接件。例如,当将第二衬底440安装到电路板或电路卡、晶圆、封装基板、其他插件等等时,可以在第二衬底440的相对面或连接面上形成C4焊料凸块或焊球从而形成外部连接或系统连接。第二衬底440的底面可以具有形成水平运行并将焊球安置(map)到不同TV的连接件的再分布层(“RDL”),从而提供焊球布置方面的灵活性。焊料凸块可以是基于铅的焊料或者无铅焊料,并且与后来用于将插件组装件安装至目标系统中的母板、系统板等等的焊料回流工艺兼容。接触焊盘752可以进行各种镀层处理以增加粘合性、提供渗透势垒、预防氧化、以及增加可焊性,包括镍、金、铂、钯、铜、及其合金,并且包括诸如无电镀镍浸金(“ENIG”)、无电镀镍无电镀钯浸金(“ENEPIG”)等的处理。
作为本领域普通技术人员将了解,上面的描述提供了实施例部件的一般性说明以及可以存在众多其他部件。例如,可以存在其他电路、衬垫、阻挡层、凸块下金属化结构、再分布层(RDL)等等。上面的描述意在仅仅为本文论述的实施例提供环境,并不意味着限制本发明或者对这些具体实施例的任何权利要求的范围。可以使用任何合适的工艺以形成上面论述的结构,并且在此对这些工艺不作更详细的论述。
此后,需要时可以实施其他加工步骤。例如,可以沿着(例如沿着切割线754)切割第二衬底440从而形成单独的多管芯封装件。
在实施例中,提供了一种方法。该方法包括:提供衬底;在第一区和第二区之间形成第一切口,第一切口具有第一宽度;以及在第一切口内形成第二切口,第二切口具有小于第一宽度的第二宽度,从而形成凸缘,第二切口延伸穿过衬底;然后将衬底切割成单独的管芯。
在另一实施例中,提供了另一种方法。该方法包括:在衬底上放置多个管芯,管芯中的至少之一具有沿着侧壁形成的凸缘;在多个管芯和衬底之间放置底部填充物,该底部填充物在多个管芯中的邻近管芯之间延伸;以及在位于多个管芯中的邻近管芯之间的底部填充物的上方放置模塑料。
在又一个实施例中,提供了一种器件。该器件包括:衬底;位于衬底上的多个管芯,多个管芯中的至少第一管芯具有沿着侧壁的凸缘;位于多个管芯和衬底之间的底部填充物;以及位于多个管芯中的邻近管芯之间的模塑料,底部填充物在多个管芯中的邻近管芯之间在模塑料和衬底之间延伸。
因此,通过参考某些实施例描述了本发明,可以注意到,公开的实施例在本质上是示例性的而非限制性的,以及在前面的公开内容中,预期涵盖大范围的变化、修改、改变和替换,并且,在一些情况下,在其他部件不具有相应的用途时,可以使用本发明的一些部件。根据对前面的实施例描述的仔细研究,许多这种变化和修改被本领域技术人员视为是明显的和可取的。因此,所附权利要求按照广义以及与本发明范围一致的方式进行解释是适当的。
尽管已经详细地描述了本发明及其优势,但应该理解,可以在不背离所附权利要求限定的实施例的精神和范围的情况下,在其中进行各种改变、替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明将很容易理解,根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此,所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (10)

1.一种方法,包括:
提供衬底;
在第一区和第二区之间形成第一切口,所述第一切口具有第一宽度;以及
在所述第一切口内形成第二切口,所述第二切口具有小于所述第一宽度的第二宽度,从而形成凸缘,所述第二切口延伸穿过所述衬底,从而将所述衬底切割成单独的管芯。
2.根据权利要求1所述的方法,还包括在形成所述第二切口之前将所述衬底放置在载带上。
3.根据权利要求2所述的方法,其中,通过导电凸块将所述衬底接合至所述载带。
4.根据权利要求1所述的方法,还包括:
将一个或多个所述管芯放置到第二衬底上;以及
在一个或多个所述管芯和所述第二衬底之间放置底部填充物,所述底部填充物的上表面位于所述凸缘处。
5.根据权利要求4所述的方法,其中,所述第二衬底包括插件。
6.根据权利要求4所述的方法,还包括在位于邻近管芯之间的所述底部填充物的上方形成模塑料。
7.根据权利要求6所述的方法,还包括减薄所述模塑料。
8.根据权利要求1所述的方法,其中,所述凸缘具有约5μm至约200μm的宽度。
9.一种方法,包括:
在衬底上放置多个管芯,所述管芯中的至少一个具有沿着侧壁形成的凸缘;
在所述多个管芯和所述衬底之间放置底部填充物,所述底部填充物在所述多个管芯中的邻近管芯之间延伸;以及
在位于所述多个管芯中的邻近管芯之间的所述底部填充物的上方放置模塑料。
10.一种器件,包括:
衬底;
多个管芯,位于所述衬底上,所述多个管芯中的至少第一管芯具有沿着侧壁的凸缘;
底部填充物,位于所述多个管芯和所述衬底之间;以及
模塑料,位于所述多个管芯中的邻近管芯之间,所述底部填充物在所述多个管芯中的邻近管芯之间在所述模塑料和所述衬底之间延伸。
CN201210119467.9A 2011-12-16 2012-04-20 管芯结构及其制造方法 Active CN103165531B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/328,746 US8828848B2 (en) 2011-12-16 2011-12-16 Die structure and method of fabrication thereof
US13/328,746 2011-12-16

Publications (2)

Publication Number Publication Date
CN103165531A true CN103165531A (zh) 2013-06-19
CN103165531B CN103165531B (zh) 2015-05-27

Family

ID=48588507

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210119467.9A Active CN103165531B (zh) 2011-12-16 2012-04-20 管芯结构及其制造方法

Country Status (2)

Country Link
US (1) US8828848B2 (zh)
CN (1) CN103165531B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104716106A (zh) * 2013-12-17 2015-06-17 三星电子株式会社 半导体封装件及其制造方法
CN105304509A (zh) * 2014-06-08 2016-02-03 联测总部私人有限公司 半导体封装和封装半导体装置的方法
CN108029230A (zh) * 2015-09-02 2018-05-11 高通股份有限公司 载带

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048233B2 (en) * 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9006908B2 (en) * 2012-08-01 2015-04-14 Marvell Israel (M.I.S.L) Ltd. Integrated circuit interposer and method of manufacturing the same
US9520323B2 (en) * 2012-09-11 2016-12-13 Freescale Semiconductor, Inc. Microelectronic packages having trench vias and methods for the manufacture thereof
US20140273354A1 (en) * 2013-03-15 2014-09-18 Applied Materials, Inc. Fabrication of 3d chip stacks without carrier plates
KR101579673B1 (ko) * 2014-03-04 2015-12-22 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
US10319639B2 (en) * 2017-08-17 2019-06-11 Semiconductor Components Industries, Llc Thin semiconductor package and related methods
WO2017199278A1 (ja) * 2016-05-16 2017-11-23 株式会社日立製作所 半導体装置
CN111627867A (zh) * 2019-02-28 2020-09-04 富泰华工业(深圳)有限公司 芯片封装结构及其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090200684A1 (en) * 2007-12-28 2009-08-13 Naomi Masuda Flip chip package with shelf and method of manufactguring there of
CN101521165A (zh) * 2008-02-26 2009-09-02 上海凯虹电子有限公司 芯片级封装方法
US20110147898A1 (en) * 2009-12-23 2011-06-23 Xerox Corporation Method for dicing a semiconductor wafer, a chip diced from a semiconductor wafer, and an array of chips diced from a semiconductor wafer

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6271815B1 (en) 1998-02-20 2001-08-07 University Of Hong Kong Handy information display system
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US6686225B2 (en) * 2001-07-27 2004-02-03 Texas Instruments Incorporated Method of separating semiconductor dies from a wafer
JP3530158B2 (ja) * 2001-08-21 2004-05-24 沖電気工業株式会社 半導体装置及びその製造方法
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6794273B2 (en) * 2002-05-24 2004-09-21 Fujitsu Limited Semiconductor device and manufacturing method thereof
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
AU2003291199A1 (en) * 2002-12-09 2004-06-30 Advanced Interconnect Technologies Limited Package having exposed integrated circuit device
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US7301222B1 (en) * 2003-02-12 2007-11-27 National Semiconductor Corporation Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
JP4342832B2 (ja) * 2003-05-16 2009-10-14 株式会社東芝 半導体装置およびその製造方法
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US7271479B2 (en) * 2004-11-03 2007-09-18 Broadcom Corporation Flip chip package including a non-planar heat spreader and method of making the same
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US7727875B2 (en) * 2007-06-21 2010-06-01 Stats Chippac, Ltd. Grooving bumped wafer pre-underfill system
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
US7651889B2 (en) * 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US8048781B2 (en) * 2008-01-24 2011-11-01 National Semiconductor Corporation Methods and systems for packaging integrated circuits
US8105875B1 (en) * 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US8501590B2 (en) * 2011-07-05 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for dicing interposer assembly

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090200684A1 (en) * 2007-12-28 2009-08-13 Naomi Masuda Flip chip package with shelf and method of manufactguring there of
CN101521165A (zh) * 2008-02-26 2009-09-02 上海凯虹电子有限公司 芯片级封装方法
US20110147898A1 (en) * 2009-12-23 2011-06-23 Xerox Corporation Method for dicing a semiconductor wafer, a chip diced from a semiconductor wafer, and an array of chips diced from a semiconductor wafer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104716106A (zh) * 2013-12-17 2015-06-17 三星电子株式会社 半导体封装件及其制造方法
CN105304509A (zh) * 2014-06-08 2016-02-03 联测总部私人有限公司 半导体封装和封装半导体装置的方法
CN108029230A (zh) * 2015-09-02 2018-05-11 高通股份有限公司 载带
CN108029230B (zh) * 2015-09-02 2020-09-18 高通股份有限公司 载带

Also Published As

Publication number Publication date
US8828848B2 (en) 2014-09-09
US20130154062A1 (en) 2013-06-20
CN103165531B (zh) 2015-05-27

Similar Documents

Publication Publication Date Title
CN103165531B (zh) 管芯结构及其制造方法
US10163821B2 (en) Packaging devices and methods for semiconductor devices
CN102844861B (zh) 对用于裸片翘曲减少的组装的ic封装衬底的tce补偿
KR102649471B1 (ko) 반도체 패키지 및 그의 제조 방법
CN109637934B (zh) 电子器件及制造电子器件的方法
JP5579402B2 (ja) 半導体装置及びその製造方法並びに電子装置
CN104377171A (zh) 具有中介层的封装件及其形成方法
US11823913B2 (en) Method of manufacturing an electronic device and electronic device manufactured thereby
US10529652B2 (en) Integrated circuit (IC) package with a solder receiving area and associated methods
US20100159643A1 (en) Bonding ic die to tsv wafers
CN103515305A (zh) 3d ic堆叠器件及制造方法
TW201642358A (zh) 半導體封裝組件及其製造方法
US9379097B2 (en) Fan-out PoP stacking process
TW201434097A (zh) 封裝一半導體裝置之方法及封裝裝置
US10325880B2 (en) Hybrid 3D/2.5D interposer
TW202105635A (zh) 熱增強封裝件及其製造方法
US9142523B2 (en) Semiconductor device and manufacturing method thereof
US8652939B2 (en) Method and apparatus for die assembly
US11721654B2 (en) Ultra-thin multichip power devices
CN112331645A (zh) 半导体封装装置
US9761570B1 (en) Electronic component package with multple electronic components
US7972904B2 (en) Wafer level packaging method
TW201804590A (zh) 半導體裝置及其製造方法
JP2013045987A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant