CN104716106A - 半导体封装件及其制造方法 - Google Patents

半导体封装件及其制造方法 Download PDF

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Publication number
CN104716106A
CN104716106A CN201410748653.8A CN201410748653A CN104716106A CN 104716106 A CN104716106 A CN 104716106A CN 201410748653 A CN201410748653 A CN 201410748653A CN 104716106 A CN104716106 A CN 104716106A
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China
Prior art keywords
semiconductor chip
semiconductor
interconnecting parts
package substrate
semiconductor package
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CN201410748653.8A
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English (en)
Inventor
赵汊济
赵泰济
任允赫
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN104716106A publication Critical patent/CN104716106A/zh
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Abstract

本发明提供了一种半导体封装件。至少一个半导体芯片安装在封装衬底上。模制层覆盖所述至少一个半导体芯片。模制层暴露出所述至少一个半导体芯片的最上面的半导体芯片的顶表面的一部分。

Description

半导体封装件及其制造方法
相关申请的交叉引用
本申请要求于2013年12月17日在韩国知识产权局提交的韩国专利申请No.10-2013-0157323的优先权，该申请的公开以引用方式全文并入本文中。
技术领域
本发明构思涉及半导体封装件及其制造方法。
背景技术
电子器件包括各种系统芯片(SoC)器件，以减轻重量和确保高性能。
可利用各种封装技术实现SoC器件。随着SoC器件的性能增强，从器件中产生更多的热，因此性能会降低。
发明内容
根据本发明的示例性实施例，提供了一种半导体封装件。至少一个半导体芯片安装在封装衬底上。模制层覆盖所述至少一个半导体芯片。模制层暴露出所述至少一个半导体芯片的最上面的半导体芯片的顶表面的一部分。
根据本发明构思的示例性实施例，提供了一种制造半导体封装件的方法。至少一个半导体芯片安装在封装衬底上。所述至少一个半导体芯片和封装衬底由模制框覆盖。将模制树脂溶液供应至由模制框、所述至少一个半导体芯片和封装衬底限定的内部空间中。模制树脂溶液硬化以形成模制层。在供应模制树脂溶液之前使封装衬底和半导体芯片弯曲。
附图说明
通过参照附图详细描述本发明构思的示例性实施例，本发明构思的这些和其它特征将变得更加清楚，其中：
图1是示出根据本发明构思的示例性实施例的半导体封装件的布局图；
图2A和图2B是沿着图1的线I-I'截取的剖视图；
图2C是图2A的半导体封装件的透视图；
图3是图2A的部分‘P1’的放大图；
图4A和图4B是图2A的部分‘P2’的放大图；
图5是示出安装在母板上的图2A或图2B的半导体封装件的剖视图；
图6A、图6B和图7至图10是示出制造图2A或图2B的半导体封装件的方法的剖视图；
图11A和图11B是示出图2A的半导体封装件的修改的示例性实施例的剖视图；
图12是示出根据本发明构思的示例性实施例的半导体封装件的布局图；
图13A是沿着图12的线I-I'截取的剖视图；
图13B和图15是沿着图12的线II-II'截取的剖视图；
图14是示出图13A和图13B的半导体封装件的透视图；
图16A和图16B是图13B的部分‘P2’的放大图；
图17至图19是示出制造图13B和图15的半导体封装件的方法的剖视图；
图20A和图20B是示出图13B的半导体封装件的修改的示例性实施例的剖视图；
图21是示出根据本发明构思的示例性实施例的半导体封装件的布局图；
图22是沿着图21的线I-I'截取的剖视图；
图23和图24是示出制造图22的半导体封装件的方法的剖视图；
图25和图26是示出根据本发明构思的示例性实施例的半导体封装件的剖视图；
图27是示出包括根据本发明构思的示例性实施例的半导体封装件的示例性封装模块的示意图；
图28是示出包括根据本发明构思的示例性实施例的半导体封装件的示例性电子系统的示意性框图；以及
图29是示出包括根据本发明构思的示例性实施例的半导体封装件的示例性存储卡的示意性框图。
具体实施方式
以下将参照附图详细地描述本发明构思的示例性实施例。然而，本发明构思可按照不同的形式实现，并且不应理解为限于本文阐述的实施例。在附图中，为了清楚起见，可夸大层和区的厚度。还应该理解，当一个元件被称作“位于”另一元件或衬底“上”时，所述一个元件可直接位于另一元件或衬底上，或者也可存在中间层。还应该理解，当一个元件被称作“结合至”或“连接至”另一元件时，所述一个元件可直接结合至或连接至另一元件，或者也可存在中间元件。在整个说明书和附图中，相同的附图标记可指代相同的元件。
图1是示出根据本发明构思的示例性实施例的半导体封装件的布局图。图2A和图2B是沿着图1的线I-I'截取的剖视图。图2C是图2A的半导体封装件的透视图。图3是图2A的部分‘P1’的放大图。图4A和图4B是图2A的部分‘P2’的放大图。
参照图1、图2A、图2B和图2C，半导体封装件200包括按顺序堆叠和安装在封装衬底10上的第一半导体芯片30和第二半导体芯片45。为了方便描述，半导体封装件200包括两个芯片30和45，但包括在半导体封装件中的芯片的数量不限于两个。芯片的数量可为至少一个。第一半导体芯片30包括穿通第一半导体芯片30的至少一个过孔35。利用倒装芯片接合技术通过第一内部焊料球38a将第一半导体芯片30安装在封装衬底10上。利用倒装芯片接合技术通过第二内部焊料球38b将第二半导体芯片45安装在第一半导体芯片30上。内部焊料球38a和38b可包括锡、铅和铜中的至少一个。半导体芯片30和45以及封装衬底10由模制层24覆盖。外部焊料球60接合至封装衬底10的底表面。
参照图3，第一半导体芯片30包括衬底部分30c和设置在衬底部分30c上的晶体管TR。晶体管TR由相互堆叠的层间绝缘层34覆盖。芯片互连部分33设置在层间绝缘层34之间。过孔35穿通层间绝缘层34的最下面的层间绝缘层和衬底部分30c，并且与至少一个芯片互连部分33接触。过孔35可包括诸如铜的金属。防扩散层32和绝缘层31共形地设置在过孔35与衬底部分30c之间以及过孔与最下面的层间绝缘层34之间。衬底部分30c的底表面由第一钝化层39覆盖。过孔35的底表面与第一导电焊盘41接触。第二导电焊盘36设置在层间绝缘层34的最上面的层间绝缘层上。第二导电焊盘36的一部分和最上面的层间绝缘层34由第二钝化层37覆盖。第一导电焊盘41和第二导电焊盘36分别与第一内部焊料球38a和第二内部焊料球38b接触。
第二半导体芯片45的结构可与上述第一半导体芯片30的结构相同或相似。第二半导体芯片45不需要包括参照图3描述的过孔35。
参照图4A和图4B，封装衬底10是一种多层印刷电路板。例如，封装衬底10包括芯层10c、设置在芯层10c上的上互连部分结构10a、设置在芯层10c下方的下互连部分结构10b。上互连部分结构10a包括上衬底绝缘层14a和设置在上衬底绝缘层14a之间的上互连部分12a。下互连部分结构10b包括下衬底绝缘层14b和设置在下衬底绝缘层14b之间的下互连部分12b。封装衬底10中的上互连部分12a的体积可与封装衬底10中的下互连部分12b的体积不同。例如，在图4A和图4B中，上互连部分12a的体积大于下互连部分12b的体积。在图4A中，上互连部分12a的厚度T1大于下互连部分12b的厚度T2。可替换地，在图4B中，上互连部分12a的面积大于下互连部分12b的面积，如图4B所示。
返回参照图1和图2A至图2C，例如，第一半导体芯片30和第二半导体芯片45中的至少一个可为存储器芯片。第一半导体芯片30和第二半导体芯片45中的至少一个可为具有知识产权(IP)块的逻辑芯片。IP块可对应于诸如中央处理器单元(CPU)、图形处理器单元(GPU)和/或通用串行总线(USB)的各种器件。所述IP块会产生热，从而在所述热未适当地释放的情况下会导致操作错误。为了防止这种操作错误，半导体芯片30和45的操作速度会降低。与其它部分产生的热相比产生更多热的部分可被称作热斑区H1。热斑区H1位于第一半导体芯片30或第二半导体芯片45的中心部分。需要将热斑区H1产生的热释放到半导体封装件200的外部，以防止操作错误和/或操作速度降低。
模制层24暴露出第二半导体芯片45的与热斑区H1重叠的中心顶表面S1(即，顶表面的中心部分)。因此，与中心顶表面S1由模制层24覆盖时的情况相比，热斑区H1产生的热可快速地释放到半导体封装件200的外部。模制层24覆盖半导体封装件200的除热斑区H1以外的其它部分。例如，模制层24覆盖封装衬底10的顶表面和第二半导体芯片45的除第二半导体芯片45的中心顶表面S1以外的其它部分。中心顶表面S1与热斑区H1重叠。可通过模制层24抑制半导体封装件200由于从中产生的热导致的翘曲。
与具有暴露最上面的半导体芯片45的整个顶表面的模制层的半导体封装件的结构相比，半导体封装件200的结构可抑制半导体封装件200遭受翘曲现象。另外，与具有完全覆盖半导体芯片30和45的模制层的半导体封装件相比，半导体封装件200可快速地释放半导体封装件200产生的热。半导体封装件200暴露出最上面的半导体芯片45的中心顶表面S1以释放热。例如，中心顶表面S1与半导体封装件200的热斑区H1重叠。半导体封装件200包括模制层24，除中心顶表面S1以外，模制层24完全覆盖半导体芯片30和45。因此，实现了热的释放，同时利用模制层24抑制了半导体封装件200的翘曲。
参照图2A和图2C，模制层24的顶表面S2弯曲。例如，顶表面S2凹陷。在这种情况下，模制层24具有布置为高于第二半导体芯片45的中心顶表面S1的四个上顶点PM。封装衬底10以及半导体芯片30和45可为基本平坦的。可替换地，在图2B中，模制层24的顶表面S2是基本平坦的。在这种情况下，封装衬底10以及半导体芯片30和45凸出。
返回参照图2A和图2B以及图4A和图4B，半导体芯片30和45的层间绝缘层34可具有张应力。为了方便描述，半导体封装件200的曲率被夸大。随着残余应力的量增大，半导体封装件200变得更加弯曲。例如，图2B的半导体封装件200比图2A的半导体封装件200具有更大的残余应力。如果互连部分12a和12b由金属(例如，铜)形成，则互连部分12a和12b的热膨胀系数高于层间绝缘层14a和14b的热膨胀系数。由于互连部分12a与12b之间的体积膨胀的差异，因此可在制造半导体封装件200的处理中弯曲半导体封装件200。这在稍后将参照图6A至图10来描述。
图5是示出安装在母板上的图2A或图2B的半导体封装件200的剖视图。
参照图5，图2A的半导体封装件200安装在母板250上。封装衬底10以及半导体芯片30和45是基本平坦的，并且模制层45的顶表面S2凹陷。图2B的半导体封装件200可安装在母板250上。如上所述，为了方便描述，夸大了图2B的半导体封装件200的曲率。
图6A、图6B和图7至图10是示出制造图2A或图2B的半导体封装件的方法的剖视图。
参照图6A和图6B，形成了封装衬底10。如参照图4A和图4B描述的那样，当形成封装衬底10时，封装衬底10的上互连部分12a和下互连部分12b的体积可彼此不同。封装衬底10可为多层印刷电路板。封装衬底10包括芯片安装区10d和设置在芯片安装区10d之间的非安装区10e。半导体芯片30和45可安装在芯片安装区10d的每个上。芯片安装区10d的每个可包括构成各种电路的上互连部分12a和下互连部分12b，如参照图4A和图4B描述的那样。上互连部分12a和下互连部分12b不需要设置在非安装区10e中。图6A的封装衬底10可经受高温。例如，高温的范围可在约200℃和约350℃之间。如图6B所示，当封装衬底10经受高温时，由于上互连部分12a和下互连部分12b之间的分布差异和/或上互连部分12a和下互连部分12b之间的体积膨胀差异导致芯片安装区10d变凸。可替换地，封装衬底10在安装半导体芯片30和45之前可为整体平坦的，如图6A所示。
参照图7，形成了半导体芯片30和45。可控制用于在半导体芯片30和45中形成层间绝缘层34的处理设备和/或处理方法，以使得当形成半导体芯片30和45时层间绝缘层34的残余应力是张应力。例如，可在范围在例如约200℃和约350℃之间的高温下执行半导体芯片30和45的堆叠。第一半导体芯片30和第二半导体芯片45可利用内部焊料球38a和38b通过倒装芯片接合技术按顺序堆叠和安装在芯片安装区10d的每个上。此时，可在等于或大于内部焊料球38a和38b的熔点的温度下执行加热处理。封装衬底10的芯片安装区10d可通过加热处理的处理温度变凸。由于在安装处理之前，芯片安装区10d在半导体芯片30和45为基本平坦的情况下变为向上凸，因此在安装处理之后，半导体芯片30和45可变为向上凸。在这种情况下，半导体芯片30和45的厚度范围可为约50μm和约100μm之间。可通过在安装处理之后执行的冷却处理稍微减轻封装衬底10以及半导体芯片30和45的凸出程度(或翘曲程度)。然而，由于封装衬底10与半导体芯片30和45的材料性质之间的差异，会保留一定的凸出程度(或翘曲程度)。例如，当图7的所得结构转移至将在以下描述的图8的下一处理阶段时可进行这种冷却处理。如果以连续方式执行图8的下一处理阶段，则可省略冷却处理。
参照图8，封装衬底10由模制框M1覆盖。随后将模制树脂溶液供应至模制框M1的内部空间中。此时，模制框M1与第二半导体芯片45的顶表面的中心部分接触，以防止模制树脂溶液覆盖第二半导体芯片45的中心顶表面。例如，模制树脂溶液填充模制框M1的内部空间的除第二半导体芯片45的中心顶表面以外的整个部分。可替换地，模制树脂溶液可部分填充所述内部空间，以暴露出第二半导体芯片45的中心顶表面。接着，模制树脂溶液通过热而硬化以形成模制层24。
参照图9，去除了模制框M1并且暴露出模制层24。第二半导体芯片45的中心顶表面S1不被模制层24覆盖。
参照图10，将外部焊料球60焊接至封装衬底10的底表面。
在图10的所得结构上执行分离处理以形成如图2A和图2B所示的单独的半导体封装件200。在分离处理中去除或切除了非安装区10e和非安装区10e上的模制层24。在半导体封装件200冷却至室温之后，单独的半导体封装件200的封装衬底10可变为基本平坦的。在这种情况下，在冷却处理中不需要完全去除残余应力。根据残余应力的量，半导体封装件200可具有图2A和图2B的弯曲形状。由于封装衬底10变为基本平坦，因此安装在封装衬底10上的半导体芯片30和45可变为基本平坦的。结果，模制层24的顶表面S2可变凹，如图2A所示。可替换地，如图2B所示，封装衬底10以及半导体芯片30和45凸出，并且模制层24的顶表面S2基本平坦。
在根据本发明构思的制造半导体封装件的示例性方法中，由于在制造半导体封装件的处理中施加的热，封装衬底10和/或半导体芯片30和45可首先凸出。在冷却封装衬底10之后，封装衬底10可变为基本平坦的。封装衬底10的这种平坦化可导致模制层24的顶表面凹陷。第二半导体芯片45的中心顶表面S1不需要由模制层24覆盖，并且可与设置在半导体封装件200的中心部分的热斑区H1的至少一部分重叠。例如，如图4A和图4B所示，在封装衬底10中，上互连部分12a的体积可大于下互连部分12b的体积，并且/或者半导体芯片30和45的层间绝缘层34可具有张应力的残余应力。因此，可在不执行形成暴露中心顶表面S1的开口的额外处理的情况下暴露出第二半导体芯片45的中心顶表面S1。结果，可简化半导体封装件200的制造处理。另外，可防止由形成开口的额外处理导致损坏第二半导体芯片45。
图11A和图11B是示出图2A的半导体封装件的示例性修改的实施例的剖视图。
参照图11A，半导体封装件201a包括热边界材料层47，其与图2A中的第二半导体芯片45的暴露的中心顶表面S1和模制层24的顶表面S2接触。散热构件49设置在热边界材料层47上。热边界材料层47可包括粘合剂层、热膏或热环氧树脂。粘合剂层、热膏和热环氧树脂中的至少一个可包括金属固体颗粒。散热构件49可为具有柔性的金属板或金属带。热边界材料层47的厚度根据热边界材料层47在第二半导体芯片45上的对应部分的位置而变化。例如，热边界材料层47在第二半导体芯片45的中心部分上可为最厚，并且在第二半导体芯片45的上顶点上可为最薄。半导体封装件201a的其它元件可与图2A的半导体封装件200的对应元件相同或相似。
参照图11B，半导体封装件201b包括按顺序堆叠在图2A中示出的第二半导体芯片45的暴露的中心顶表面S1和模制层24的顶表面S2上的热边界材料层47和散热构件49。热边界材料层47的厚度均匀。半导体封装件201b的其它元件可与参照图11A描述的半导体封装件201a的对应元件相同或相似。
图12是示出根据本发明构思的示例性实施例的半导体封装件的布局图。图13A是沿着图12的线I-I'截取的剖视图。图13B和图15是沿着图12的线II-II'截取的剖视图。图14是示出图13A和图13B的半导体封装件的透视图。图16A和图16B是图13B的部分‘P2’的放大图。
参照图3、图12、图13A、图13B、图14和图15，第一半导体芯片30和第二半导体芯片45按顺序堆叠和安装在半导体封装件202中的封装衬底10上。第一半导体芯片30可包括晶体管TR、层间绝缘层34、芯片互连部分33和至少一个过孔35，如参照图3描述的那样。第二半导体芯片45可包括除过孔35以外的晶体管TR、层间绝缘层34和芯片互连部分33。第一半导体芯片30和第二半导体芯片45中的一个可为逻辑芯片并且可具有热斑区H1。热斑区H1可设置在邻近于第一半导体芯片30或第二半导体芯片45的顶点部分的区中。第一半导体芯片30和第二半导体芯片45以及封装衬底10由模制层24覆盖。模制层24覆盖第二半导体芯片45的中心顶表面S1，而不覆盖第二半导体芯片45的上顶点PT。因此，热斑区H1或第二半导体芯片45的邻近于热斑区H1的部分不由模制层24覆盖，从而热斑区H1产生的热可通过暴露的上顶点PT释放至半导体封装件202的外部。
在图13A和图13B中，模制层24的顶表面S2向上凸并且为圆拱形，并且封装衬底10以及第一半导体芯片30和第二半导体芯片45基本平坦。可替换地，在图15中，模制层24的顶表面S2基本平坦，但是封装衬底10以及第一半导体芯片30和第二半导体芯片45的顶表面向下弯曲或凹陷。在这种情况下，第一半导体芯片30和第二半导体芯片45的层间绝缘层34的残余应力可为压应力。
图13A、图13B、图14和图15的封装衬底10可具有与图4A和图4B不同的多层印刷电路板。参照图16A和图16B，封装衬底10包括芯层10c、设置在芯层10c上的上互连部分结构10a和设置在芯层10c下方的下互连部分结构10b。上互连部分结构10a包括上衬底绝缘层14a和设置在上衬底绝缘层14a之间的上互连部分12a。下互连部分结构10b包括下衬底绝缘层14b和设置在下衬底绝缘层14b之间的下互连部分12b。上互连部分12a的体积小于下互连部分12b的体积。例如，在图16A中，上互连部分12a的厚度T1小于下互连部分12b的厚度T2。可替换地，如图16B所示，上互连部分12a的面积小于下互连部分12b的面积。互连部分12a和12b由金属(例如，铜)形成，并且与绝缘层14a和14b相比具有更高的热膨胀系数。互连部分12a和12b之间由于热导致的体积膨胀差异可导致封装衬底10在制造处理中变为向下凹。
半导体封装件202包括与热斑区H1重叠的暴露的部分，因此施加以制造半导体封装件202的热通过暴露的部分释放。因此，可减小半导体封装件202的翘曲。
半导体封装件202的其它元件可与参照图1、图2A至图2C、图3、图4A和图4B描述的对应元件相同或相似。
图17至图19是示出根据本发明构思的制造图13B和图15的半导体封装件的示例性方法的剖视图。
参照图6A和图17，形成了封装衬底10。如参照图16A和图16B描述的那样，当形成封装衬底10时，上互连部分12a和下互连部分12b的体积可彼此不同。封装衬底10可为多层印刷电路板。封装衬底10包括芯片安装区10d和设置在芯片安装区10d之间的非安装区10e。半导体芯片30和45安装在芯片安装区10d的每个上。芯片安装区10d的每个包括构成各种电路的上互连部分12a和下互连部分12b，如参照图16A和图16B描述的那样。上互连部分12a和下互连部分12b不需要设置在非安装区10e中。在图17中，如果封装衬底10受到高温，则芯片安装区10d通过上互连部分12a和下互连部分12b之间的分布差异以及上互连部分12a和下互连部分12b之间的体积膨胀差异向下凹。可替换地，在安装半导体芯片30和45之前，封装衬底10可为整体平坦的。
参照图18，形成了半导体芯片30和45。可控制用于形成半导体芯片30和45中的层间绝缘层34的处理设备和/或处理方法，以使得当形成半导体芯片30和45时，层间绝缘层34的残余应力可为压应力。可利用内部焊料球38a和38b通过倒装芯片接合技术将第一半导体芯片30和第二半导体芯片45按顺序堆叠和安装在芯片安装区10d的每个上。此时，可在等于或大于内部焊料球38a和38b的熔点的温度下执行加热处理。封装衬底10的芯片安装区10d可通过加热处理的处理温度变为向下凹。由于在安装处理之前，芯片安装区10d在半导体芯片30和45基本平坦的情况下变为向下凹，因此在安装处理之后，半导体芯片30和45可变为向下凹。可通过在安装处理之后执行的冷却处理稍微减轻封装衬底10以及半导体芯片30和45的凹陷状态。然而，由于封装衬底10以及半导体芯片30和45的材料的性质的差异，会保留封装衬底10以及半导体芯片30和45的一定程度的凹陷状态。可替换地，如果按照连续的方式执行制造处理，则可省略这种冷却处理。
参照图19，封装衬底10由模制框M1覆盖，并且随后将模制树脂溶液供应至模制框M1内以整体填充模制框M1的内部空间。模制框M1与第二半导体芯片45的顶点PT接触。因此，模制树脂溶液不覆盖与模制框M1接触的第二半导体芯片45的顶点PT。可替换地，可将模制树脂溶液的供应量控制为利用模制树脂溶液部分填充模制框M1的内部空间，以使得第二半导体芯片45的顶点PT以及与其相邻的部分不由模制树脂溶液覆盖。施加热使模制树脂溶液硬化以形成模制层24。
如图15所示，去除模制框M1以暴露出模制层24的表面。此时，暴露出第二半导体芯片45的顶点PT。外部焊料球60焊接至封装衬底10的底表面。执行分离处理以形成单独的半导体封装件202。在分离处理中，去除或切除非安装区10e和非安装区10e上的模制层24。释放在这些处理中施加的热，从而单独的半导体封装件202的封装衬底10可变得基本平坦。由于封装衬底10变得基本平坦，因此安装在封装衬底10上的半导体芯片30和45可变得基本平坦。结果，模制层24的顶表面S2变凸，如图13A和图13B所示。可替换地，如图15所示，封装衬底10以及半导体芯片30和45可保持凹陷，并且模制层24的顶表面S2基本平坦。
在根据本发明构思的制造半导体封装件的示例性方法中，封装衬底10和/或半导体芯片30和45可预先形成为凹陷的，从而暴露出与热斑区H1的至少一部分重叠的第二半导体芯片45的顶点PT。例如，在封装衬底10中，上互连部分12a的体积可小于下互连部分12b的体积，并且/或者半导体芯片30和45的层间绝缘层34可形成为具有压应力的残余应力。因此，在不用形成暴露出顶点PT的开口的额外处理的情况下，可暴露出第二半导体芯片45的顶点PT。结果，可简化半导体封装件202的制造处理。另外，可防止由于形成开口的额外处理导致损坏第二半导体芯片45。
在前述制造半导体封装件的方法中，可根据设置在半导体芯片中的热斑区的位置确定通过模制层暴露的部分。可控制半导体芯片的层间绝缘层的残余应力并且/或者可控制封装衬底中的互连部分的体积以使它们彼此不同，因此，可控制半导体芯片和/或封装衬底的翘曲程度，以暴露出邻近于热斑区的部分。
图20A和图20B是示出根据本发明构思的图13B的半导体封装件的示例性修改的实施例的剖视图。
参照图20A，半导体封装件203a包括热边界材料层47，其与图13B的第二半导体芯片45的暴露的顶点PT和模制层24的顶表面S2接触。半导体封装件203a还包括设置在热边界材料层47上的散热构件49。在图20A中，热边界材料层47的厚度根据热边界材料层47在第二半导体芯片45上的对应部分的位置而变化。例如，在第二半导体芯片45的中心部分上，热边界材料层47可为最薄的，并且在第二半导体芯片45的上顶点上，热边界材料层47可为最厚的。半导体封装件203a的其它元件可与图13B的半导体封装件202的对应元件相同或相似。
参照图20B，半导体封装件203b包括热边界材料层47，其与图13B的第二半导体芯片45的暴露的顶点PT和模制层24的顶表面S2接触。半导体封装件203b还包括设置在热边界材料层47上的散热构件49。在这种情况下，热边界材料层47的厚度基本均匀。
图21是示出根据本发明构思的示例性实施例的半导体封装件的布局图。图22是沿着图21的线I-I'截取的剖视图。
参照图21和图22，半导体封装件204包括具有开口51的模制层24。开口51与半导体芯片30和45的至少一个的热斑区H1重叠。开口51暴露出第二半导体芯片45的顶表面S1。在图22中，模制层24、封装衬底10以及半导体芯片30和45的顶表面基本平坦。然而，本发明构思不限于此。例如，模制层24、封装衬底10以及半导体芯片30和45的顶表面可向上凸或向下凹。半导体封装件204的其它元件可与上述半导体封装件的对应元件相同或相似。
模制层24可包括至少一个开口51。至少一个开口51的位置可不同。半导体封装件204还可包括图20A和图20B的热边界材料层47和散热构件49。
图23和图24是示出制造图22的半导体封装件的方法的剖视图。
参照图23，半导体芯片30和45按顺序堆叠和安装在封装衬底10的芯片安装区10d上。
参照图24，封装衬底10由模制框M2覆盖。此时，模制框M2包括从模制框M2的内部顶表面向下突出的突起53。突起53与第二半导体芯片45的顶表面接触。将模制树脂溶液提供至模制框M2的内部空间中以填充该内部空间。通过施加的热使模制树脂溶液硬化以形成模制层24。
可执行与上述那些相同的后续处理或相似的后续处理。
模制框M2的突起53可具有各种形状，从而暴露出与芯片30和45的热斑重叠的半导体芯片45的顶表面以及简化半导体封装件204的制造处理。这种简化的处理可防止损坏半导体芯片45。
图25和图26是示出根据本发明构思的示例性实施例的半导体封装件的剖视图。
参照图25，半导体封装件205包括一个半导体芯片45。模制层24暴露出半导体芯片45的中心顶表面S1但是覆盖半导体芯片45的边缘。模制层24的顶表面S2是弯曲的。半导体封装件205的其它元件可与图2A的半导体封装件200的对应元件相同或相似。
参照图26，层叠封装(PoP)器件包括根据当前实施例的示例性实施例的半导体封装件206。层叠封装(PoP)器件206包括第一子半导体封装件101和安装在第一子半导体封装件101上的第二子半导体封装件102。第一子半导体封装件101可具有与图25的半导体封装件205基本相同的结构。第二子半导体封装件102包括上封装衬底70以及安装在上封装衬底70上的上半导体芯片80a和80b。上半导体芯片80a和80b利用通过线接合技术形成的线72电连接至上封装衬底70。上模制层76覆盖上半导体芯片80a和80b以及上封装衬底70。第一子半导体封装件101的封装衬底10通过穿通第一子半导体封装件101的模制层24的互连焊料球75电连接至第二子半导体封装件102的上封装衬底70。热边界材料层47设置在第一子半导体封装件101与第二子半导体封装件102之间。半导体封装件206的其它元件可与图25的半导体封装件205的对应元件相同或相似。
利用本发明构思的示例性实施例描述了半导体封装件200、201a、201b、202、203a、203b、204、205和206的各种示例性结构和制造方法。半导体封装件200、201a、201b、202、203a、203b、204、205和206可按照各种方式彼此结合。
上述半导体封装技术可应用于各种半导体器件和包括所述半导体器件的封装模块。
图27是示出根据本发明构思的示例性封装模块的示意图。参照图27，封装模块1200包括利用四方扁平封装(QFP)技术封装的第一半导体集成电路芯片1220和第二半导体集成电路芯片1230。可根据本发明构思的示例性实施例形成半导体集成电路芯片1220和1230。芯片1220和1230安装在模块板1210上以形成封装模块1200。封装模块1200可通过设置在模块板1210的一侧上的外部连接端子1240连接至外部电子器件。
前述半导体封装技术可应用于电子系统。图28是示出根据本发明构思的示例性电子系统的示意性框图。电子系统1300包括根据本发明构思的示例性实施例的半导体封装件。参照图28，电子系统1300包括控制器1310、输入/输出(I/O)单元1320和存储器装置1330。控制器1310、I/O单元1320和存储器装置1330可通过数据总线1350彼此通信。数据总线1350可对应于电信号通过其传输的路径。例如，控制器1310可包括微处理器、数字信号处理器、微控制器和与其中的任一个具有相似功能的其它逻辑器件中的至少一个。控制器1310和存储器装置1330的每个可包括根据本发明构思的示例性实施例的至少一个半导体封装件。I/O单元1320可包括键区、键盘和显示单元中的至少一个。存储器装置1330是一种构造为存储数据的器件。存储器装置1330可存储数据和/或通过控制器1310执行的命令。存储器装置1330可包括易失性存储器装置和/或非易失性存储器装置。例如，存储器装置1330可包括闪速存储器装置。例如，应用根据本发明构思的技术的闪速存储器装置可安装在诸如移动装置或台式计算机的信息处理系统中。闪速存储器装置可实现为固态盘(SSD)。在这种情况下，电子系统1300可在存储器装置1330中存储大量数据。电子系统1300还可包括将电子数据发送至通信网络或从通信网络接收电子数据的接口单元1340。接口单元1340可支持无线和/或线缆通信。例如，接口单元1340可包括用于无线通信的天线或用于线缆通信的收发器。虽然附图中未示出，但是电子系统1300还可包括应用芯片集和/或相机图像处理器(CIS)。
电子系统1300可实现为移动系统、个人计算机、工业计算机或多功能逻辑系统。例如，移动系统可为个人数字助理(PDA)、便携式计算机、网络平板、无线电话、移动电话、笔记本计算机、数字音乐播放器、存储卡或信息发送/接收系统之一。如果电子系统1300是一种能够执行无线通信的设备，则电子器件1300可用于诸如通信系统的通信接口协议中，所述通信系统诸如CDMA、GSM、NADC、E-TDMA、WCDMA、CDMA2000、Wi-Fi、市政Wi-Fi、蓝牙、DECT、无线USB、Flash-OFDM、IEEE 802.20、GPRS、iBurst、WiBro、WiMAX、高级WiMAX、UMTS-TDD、HSPA、EVDO、高级LTE或MMDS。
根据本发明构思的示例性实施例的半导体封装件可应用于存储卡。图29是示出根据本发明构思的示例性存储卡的示意性框图。存储卡1400包括根据本发明构思的示例性实施例的半导体封装件。存储卡1400包括非易失性存储器装置1410和存储器控制器1420。非易失性存储器装置1410和存储器控制器1420可存储数据或可读存储的数据。非易失性存储器装置1410可包括应用根据本发明构思的半导体封装技术的至少一个非易失性存储器装置。存储器控制器1420可响应于主机1430的读/写请求从非易失性存储器装置1410读数据/将数据存储到非易失性存储器装置1410中。
根据本发明构思的示例性实施例，模制层不覆盖半导体芯片的邻近于热斑区的区域，而覆盖半导体芯片的其它区域。因此，在制造处理中施加至半导体芯片的热可通过半导体芯片的暴露的区域释放，因此可减小半导体封装件的翘曲。
根据本发明构思的示例性实施例，可在形成模制层之前控制封装衬底和/或半导体芯片中的翘曲的量，以在不使用形成开口的额外处理的情况下暴露出半导体芯片的一部分。因此，可简化制造处理。
根据本发明构思的示例性实施例，可利用模制框而不利用额外处理将模制层形成为包括开口。因此，可简化制造处理。
虽然已经参照本发明构思的示例性实施例显示并描述了本发明构思，但是本领域普通技术人员应该理解，在不脱离由权利要求限定的本发明构思的精神和范围的情况下，可对其作出形式和细节上的各种改变。

Claims (20)

1.一种半导体封装件，包括：
至少一个半导体芯片，其安装在封装衬底上；以及
模制层，其覆盖所述至少一个半导体芯片，其中所述模制层暴露出所述至少一个半导体芯片的最上面的半导体芯片的顶表面的一部分。
2.根据权利要求1所述的半导体封装件，其中，所述最上面的半导体芯片的顶表面的暴露的部分对应于所述最上面的半导体芯片的顶表面的中心部分。
3.根据权利要求1所述的半导体封装件，其中，所述最上面的半导体芯片的顶表面的暴露的部分对应于所述最上面的半导体芯片的上顶点。
4.根据权利要求1所述的半导体封装件，其中，所述模制层的顶表面弯曲。
5.根据权利要求4所述的半导体封装件，还包括：
堆叠在所述模制层上的热边界材料层和散热构件。
6.根据权利要求5所述的半导体封装件，其中，所述热边界材料层的厚度根据所述热边界材料层在半导体芯片上的对应部分的位置而变化。
7.根据权利要求1所述的半导体封装件，其中，所述封装衬底包括上互连部分和下互连部分，其中在所述封装衬底中，所述上互连部分比所述下互连部分高，并且
其中，所述上互连部分的体积与所述下互连部分的体积不同。
8.根据权利要求7所述的半导体封装件，其中，所述上互连部分的厚度与所述下互连部分的厚度不同。
9.根据权利要求7所述的半导体封装件，其中，所述上互连部分的面积与所述下互连部分的面积不同。
10.根据权利要求1所述的半导体封装件，其中，所述至少一个半导体芯片中的一个包括热斑区，并且
其中，所述最上面的半导体芯片的顶表面的暴露的部分与所述热斑区重叠。
11.根据权利要求1所述的半导体封装件，其中，所述至少一个半导体芯片包括具有张应力的层间绝缘层，并且
其中，所述最上面的半导体芯片的顶表面的暴露的部分对应于所述最上面的半导体芯片的顶表面的中心部分。
12.根据权利要求1所述的半导体封装件，其中，所述至少一个半导体芯片包括具有压应力的层间绝缘层，并且
其中，所述最上面的半导体芯片的顶表面的暴露的部分对应于所述最上面的半导体芯片的上顶点。
13.一种制造半导体封装件的方法，该方法包括步骤：
将至少一个半导体芯片安装在封装衬底上；
用模制框覆盖所述至少一个半导体芯片和所述封装衬底，以形成通过所述模制框、所述至少一个半导体芯片和所述封装衬底限定的内部空间，
将模制树脂溶液供应至所述内部空间中；以及
使所述模制树脂溶液硬化以形成模制层，
其中，在供应所述模制树脂溶液之前使所述封装衬底和半导体芯片弯曲。
14.根据权利要求13所述的方法，其中，所述封装衬底包括上互连部分和下互连部分，并且其中，所述上互连部分的体积与所述下互连部分的体积不同。
15.根据权利要求14所述的方法，其中，如果所述上互连部分的体积大于所述下互连部分的体积，则所述封装衬底变凸，并且其中，所述模制框与最上面的半导体芯片的顶表面的中心部分接触，并且所述模制层不覆盖所述中心部分。
16.根据权利要求14所述的方法，其中，如果所述下互连部分的体积大于所述上互连部分的体积，则所述封装衬底变凹，并且其中，所述模制框与所述模制层的顶点接触。
17.根据权利要求13所述的方法，其中，安装所述至少一个半导体芯片的步骤包括：将所述封装衬底加热至预定温度以使得所述封装衬底弯曲。
18.根据权利要求14所述的方法，其中，所述至少一个半导体芯片包括多个堆叠的层间绝缘层，其具有确定所述至少一个半导体芯片的翘曲程度的残余应力。
19.根据权利要求13所述的方法，还包括步骤：
在形成所述模制层之后，执行分离处理以将单独的半导体封装件彼此分开，
其中，在分离处理之后，将所述封装衬底和半导体芯片冷却至室温，以使得所述封装衬底和半导体芯片变得实质上平坦，从而使得所述模制层具有弯曲的顶表面。
20.根据权利要求13所述的方法，其中，所述模制框包括与半导体芯片的顶表面接触的突起。
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