CN103137591A - 电子器件及制造电子器件的方法 - Google Patents

电子器件及制造电子器件的方法 Download PDF

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Publication number
CN103137591A
CN103137591A CN2012105063421A CN201210506342A CN103137591A CN 103137591 A CN103137591 A CN 103137591A CN 2012105063421 A CN2012105063421 A CN 2012105063421A CN 201210506342 A CN201210506342 A CN 201210506342A CN 103137591 A CN103137591 A CN 103137591A
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Prior art keywords
layer
electronic device
carrier
semiconductor substrate
weld
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CN2012105063421A
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奥利弗·艾兴格
吴国财
亚历山大·海因里希
迈克尔·于尔斯
康拉德·勒斯利
托比亚斯·施密特
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及电子器件及制造电子器件的方法。该电子器件包括载体、附接至载体的半导体衬底、和布置在载体与半导体衬底之间的层系统。层系统包括布置在半导体衬底上的电接触层。功能层布置在电接触层上。粘附层布置在功能层上。焊接层布置在粘附层和载体之间。

Description

电子器件及制造电子器件的方法
技术领域
本发明涉及电子器件及制造电子器件的方法。
背景技术
为了制造电子器件，常常将半导体芯片、半导体管芯、半导体衬底或半导体晶片安装在例如引线框的载体上。目前唯一可用的具有高温循环和高温贮存可靠性的功率半导体芯片的高导电附着材料是AuSn扩散焊料粘片。此处粘片（die attach）材料是含金量大约为80%的金锡合金。因此，由于常常成为粘片处理中的问题的高成本，金锡方案受限于低焊料层厚度。
发明内容
本发明的一个方面涉及一种电子器件，其包括：具有金属表面的载体；附接所述载体的半导体衬底；以及布置在所述半导体衬底与所述载体之间的层系统，所述层系统包括：布置在所述半导体衬底上的电接触层；布置在所述电接触层上的功能层；布置在所述功能层上的粘附层；以及布置在所述粘附层与所述载体之间的焊接层。
本发明的另一个方面涉及一种电子器件，包括：引线框；布置在所述引线框上方的半导体芯片；以及布置在所述半导体芯片和所述引线框之间的层系统，所述层系统包括：布置在所述半导体芯片上的Al或Ti层；布置在所述Al或Ti层上的Ti、TiW或W层；布置在所述Ti、TiW或W层上的Cu或Ag层；布置在所述Cu或Ag层与所述引线框之间的Sn层。
本发明的又一个方面涉及一种制造电子器件的方法，该方法包括：提供半导体衬底；在所述半导体衬底上沉积电接触层；在所述电接触层上沉积功能层；在所述功能层上沉积粘附层；在所述粘附层上沉积焊接层；在所述焊接层上沉积保护层；以及将所述半导体衬底附接到载体上。
附图说明
包括有附图用于提供进一步理解本发明并且附图结合到说明书中并构成说明书的一部分。这些附图示出了实施方式并与说明书一起用来说明实施方式的原理。由于参考如下详细的描述能好地被理解，所以也容易明白其他实施方式和实施方式的很多预期优点。附图中的元件彼此间不一定是按比例绘制。相似的参考标号表示相应的类似部分。
图1示出了根据实施方式的电子器件的示意性截面侧视图。
图2a和图2b示出了用于说明粘结过程的基本机制的示意性截面侧视图。
图3示出了用于说明根据实施方式的制造电子器件的方法的流程图；以及
图4示出了载体和半导体衬底与层堆叠体的示意性截面侧视图，以说明根据实施方式的制造电子器件的方法。
具体实施方式
现参照附图描述各个方面和实施方式，其中整个附图中相似参考标号通常是指类似的元件。在下面的描述中，为了便于说明，阐述了许多具体细节，以提供对实施方式的一个或多个方面的透彻理解。但是对于本领域的技术人员显而易见的是，实施方式的一个或多个方面可以不同于这些具体细节的方式实现。在其他情况下，以示意性的形式示出已知的结构和元件，以便更好描述实施方式的一个或多个方面。需要理解的是，在不脱离本发明范围的情况下，可以采用其他实施方式，并且可以进行结构上或逻辑上的变化。还应当注意的是，附图不是或不一定是按比例绘制的。
此外，尽管实施方式的特定特征和方面仅关于多个实施方案中的一种而被公开，但是这样的特征或方面可以和其他实施方案的一个或多个其他特征或方面结合，因为该结合对于给定或特定的应用可能是所期望或有利的。此外，就在详细描述或权利要求中使用的术语“包括”，“含有”，“带有”或其他变体而言，这样的术语类似于术语“包含”。可能使用术语“耦接”和“连接”以及其衍生词。应当理解的是，不管两个元件是直接物理接触或电接触、还是彼此不直接接触，这些术语可用于表明两个元件彼此协作或交互。此外，术语“示例性”仅是指例子，而不是指最好的或最佳的。因此，下面的详细描述不应被认为是限制性的，本发明的范围由所附的权利要求书定义。
电子器件和用于制造电子器件的方法的实施方式可以使用不同类型的半导体芯片或结合在在半导体芯片中的电路，其中包括逻辑集成电路、模拟集成电路、混合信号集成电路、传感器电路、MEMS（微机电系统）、功率集成电路、具有集成无源器件的芯片等。实施方式也可使用包含MOS晶体管结构或垂直晶体管结构的半导体芯片，例如IGBT（绝缘栅双极型晶体管）结构，或概括地讲，如下的晶体管结构：至少一个的电接触端子被设置在半导体芯片的第一主面上并且至少另外一个电接触端子被设置在与半导体芯片的第一主面的相反的该半导体芯片的第二主面上。
在几个实施方式中，层或层堆叠体被应用到另一个层或层堆叠体，或者材料被应用或沉积到层上。应当理解的是，任何如“应用（applied）”或“沉积”的术语是指基本涵盖将层应用到另外的层上的所有类型和技术。特别地，它们是指涵盖了层作为一个整体被一次性应用的技术，例如层压技术，以及层以顺序方式沉积的技术，例如，溅射、电镀、模塑、CVD等。
参看图1，其示出了根据实施方式的电子器件的示意性截面侧视图。图1中的电子器件10包括具有金属表面的载体1、半导体衬底2、和布置在半导体衬底2与载体1之间的层系统3。层系统3包括布置在该半导体衬底2上的电接触层3.1、布置在电接触层3.1上的功能层3.2、布置在功能层3.2上的粘附层3.3以及布置在粘附层3.3与载体1之间的焊接层3.4。
根据电子设备10的一个实施方式，半导体衬底2由硅基半导体材料组成，例如由Si、SiC或另一硅基材料制成的基板，或者由化合物半导体材料组成，例如III-V族材料，如GaN。半导体衬底可以包括在其下表面的由高掺杂n+或p+区域形成的电接触端子。
根据电子设备10的一个实施方式，电接触层3.1包括Al、Ti、Ag或Cr的单一元素层，或含有一个或多个这些元素且可能还有其它元素的合金。
根据电子设备10的一个实施方式，功能层3.2由阻挡层组成。特别地，功能层由Ti、TiW或W的材料组成，或者由含有一种或几种这些材料的合金组成。
根据电子设备10的一个实施方式，粘附层3.3包括铜、金、银、铂或镍的单一元素层、或含有一种或多种这些元素且可能还有其它元素的合金。
根据电子设备10的一个实施方式，焊接层3.4包括锡、锌、铟、镓、铋或镉的单一元素层、或含有一种或多种这些元素且可能还有其它元素的合金。
根据电子设备10的一个实施方式，焊接层3.4包括单一元素焊接材料，其在沉积过程中不易相形成。此外，焊接材料本身可以不使用贵金属，因此便宜许多。由于较低的成本，它可以比锡金合金更厚地应用，从而使粘片处理本身更容易。根据焊接材料的不同，焊接温度也可以显著降低，由于通过焊接材料的等温凝固结合到焊料互连产生的应力更小，可靠性更高。
根据电子设备10的一个实施方式，载体1由金属载体组成，特别地，由铜、镍或铁组成、或由含有一种或几种这些元素且可能还有其它元素的合金组成。
根据电子设备10的一个实施方式，载体1涂覆有一个或多个金属层。这种情况下，载体1自己可由非金属载体组成，例如由如氧化铝的陶瓷材料制成的载体。特别地，最上面的金属层由金、银、铜、钯或铂组成，或由包括一种或几种这些元素的合金组成。
根据电子设备10的一个实施方式，金属间相形成于载体1与焊接层3.4之间，或者布置于载体1上的金属层与焊接层3.4之间。
根据电子设备10的一个实施方式，金属间相形成于粘附层3.3与焊接层3.4之间。
根据电子设备10的一个实施方式，粘附层3.3以及载体1的表面或者涂覆在载体表面上的金属层的表面由相同基材组成。特别地，这些基材由Cu、Ag、NiV、Ni或NiNiP组成。
根据电子设备10的一个实施方式，载体1由引线框组成。
根据电子设备10的一个实施方式，层系统3不含金。
根据电子设备10的一个实施方式，半导体衬底2的厚度范围从5μm到500μm。
根据电子设备10的一个实施方式，电接触层3.1的厚度范围从100nm到1μm。
根据电子设备10的一个实施方式，功能层3.2的厚度范围从50nm到200nm。
根据电子设备10的一个实施方式，粘附层3.3的厚度范围从200nm到2μm。
根据电子设备10的一个实施方式，焊接层3.4的厚度范围从1μm到5μm。
值得注意的是以上厚度范围都覆盖了所述增量值（incrementalvalue）。
发现当粘附层3.3和载体1的表面（即载体1的基材或涂覆在载体1上的最上面的金属层）由相同的基材（例如Cu/Cu、Ag/Ag、NiV/Ni或NiV/NiNiP，这获得二元或准二元合金系统，在焊料互连中形成特征层结构）构成时，可以得到良好的结果。层结构基本上为二元合金相图中所示的相分数，该结构可与，在此情况下，Cu/Sn的双面扩散偶（two-sideddiffusion couple）相媲美。
参照图2a和图2b，为了说明根据实施方式中的层结构以说明粘结机制，示出了示意性截面侧视图。在图2a中，示出了载体1以及在粘结处理之前层堆叠体（layer stack）3中只有粘附层3.3和焊接层3.4被示出。图2b示出了粘结处理之后的层结构。可以看出，在焊接层3.4的两侧金属间相层已经形成。在图2b中，第一金属间相层3.5形成于粘附层3.3和焊接层3.4之间，第二金属间相层3.6形成于焊接层3.4和载体1之间。第一金属间相层3.5富含粘附层3.3的金属，而第二金属间相层3.6富含载体1的表面的金属。剩余中间焊接层3.4仍然富含原来的焊接层3.4的金属。如果载体1的材料和粘附层3.3的材料相同并且也依赖于该层的厚度，那么也可以形成只有一个均质层的合金相，而不是焊接层3.4、第一金属间相层3.5和第二金属间相层3.6。取决于所使用的材料组合，也可以在所述互连内形成超过两个的不同的层。
参看图3，其示出了用于说明根据实施方式的电子器件的制造方法的流程图。方法30包括提供半导体衬底（31），在半导体衬底上沉积电接触层（32），在电接触层上沉积功能层（33），在功能层上沉积粘附层（34），在粘附层上沉积焊接层（35），在焊接层上沉积保护层（36），以及将半导体衬底附接到载体上（37）。
根据方法30的一个实施方式，此方法进一步包括通过物理气相沉积法或溅射法，特别是在一个相同的处理装置中，来沉积电接触层、功能层、粘附层、焊接层以及保护层中的一个或多个。
根据方法30的一个实施方式，电接触层由Al或Ti层组成，功能层由Ti、TiW或W层组成，粘附层由Cu或Ag层组成，焊接层由Sn层组成，以及保护层由Ag或Au层组成。
方法30的更多实施方式可通过将与图1和图2的实施方式相关的上述任何特征结合到图3来完成。
图4示出了载体以及半导体衬底与层堆叠体的示意性截面侧视图，以说明根据实施方式的电子设备的制造方法。图4实质上示出了载体41，特别为引线框，以及粘结至载体41的半导体衬底42。为此，层堆叠体43随后被沉积在半导体衬底42的下表面。在第一步骤电接触层43.1沉积在半导体衬底42的下表面。在第二步骤功能层43.2沉积在电接触层43.1上。在第三步骤粘附层43.3沉积在功能层43.2上。在第四步骤焊接层43.4沉积在粘附层43.3上。在第五步骤保护层43.5沉积在焊接层43.4上。沉积处理可通过物理气相沉积法或溅射法实现。
根据一个实施方式，保护层43.5的厚度范围从50nm到300nm。因此保护层43.5可被制得很薄，以至于在图1所示的最终产品中实际上消失了。保护层43.5防止焊接层43.4的氧化。
在图4的实施方式中，一个或多个金属层41.1沉积在载体41。金属层41.1或在两个以上的金属层时最上面的金属层由Au、Ag、Cu、Pd或Pt、或一种或几种这些元素的合金组成。
最后，在半导体衬底42上制成层堆叠体43之后，半导体衬底42与层堆叠体43一起分别粘结在载体41的上表面或者最上面的金属层41.1的上表面。
此外，由半导体衬底42和层堆叠体43构成的系统能以300°C的粘片温度下被焊接，相比目前的AuSn焊接层附接时的350°C，粘片应力较低。
尽管本发明已经示出和描述了一个或多个实施方案，在不脱离所附权利要求的精神和范围的情况下，可对所示出的实例进行变更和/或修改。特别是关于上述部件或结构（组件、装置、电路、系统等）实现的各种功能时，除非另有说明，否则用于描述这些部件的术语（包括“手段”的引用）旨在对应任何执行上述部件的具体功能的部件或结构（即功能上相同），即使结构上与执行本发明的所示出的示例性实施方案中的功能的公开结构并不等价。

Claims (24)

1.一种电子器件，包括：
具有金属表面的载体；
附接所述载体的半导体衬底；以及
布置在所述半导体衬底与所述载体之间的层系统，所述层系统包括：
布置在所述半导体衬底上的电接触层；
布置在所述电接触层上的功能层；
布置在所述功能层上的粘附层；以及
布置在所述粘附层与所述载体之间的焊接层。
2.根据权利要求1所述的电子器件，其中，所述半导体衬底包括硅基半导体材料。
3.根据权利要求1所述的电子器件，其中，所述电接触层包括Al、Ti、Ag或Cr的单一元素层、或含有一种或多种这些元素的合金。
4.根据权利要求1所述的电子器件，其中，所述功能层包括阻挡层。
5.根据权利要求1所述的电子器件，其中，所述功能层包括Ti、TiW或W、或者含有这些材料的合金。
6.根据权利要求1所述的电子器件，其中，所述粘附层包括Cu、Au、Ag、Pt或Ni的单一元素层、或含有一种或多种这些元素的合金。
7.根据权利要求1所述的电子器件，其中，所述焊接层包括Sn、Zn、In、Ga、Bi或Cd的单一元素层、或含有一种或多种这些元素的合金。
8.根据权利要求7所述的电子器件，其中，所述焊接层包括Sn、Zn、In、Ga、Bi或Cd中的一种或多种的合金并且还包括AuSn、SnAg、CuSn或CuSnAg。
9.根据权利要求1所述的电子器件，其中，所述载体包括Cu、Ni或Fe、或含有一种或多种这些元素的合金。
10.根据权利要求1所述的电子器件，其中，所述载体的表面涂覆有一个或多个金属层。
11.根据权利要求1所述的电子器件，其中，最上面的金属层包括Au、Ag、Cu、Pd或Pt、或者一种或多种这些元素的合金。
12.根据权利要求1所述的电子器件，其中，在所述粘附层与所述焊接层之间形成有金属间相。
13.根据权利要求1所述的电子器件，其中，在所述载体与所述焊接层之间、或者布置在所述载体上的金属层与所述焊接层之间形成有金属间相。
14.根据权利要求1所述的电子器件，其中，所述粘附层和载体表面或涂覆在所述载体表面上的金属层的表面是由相同的基材构成。
15.根据权利要求14所述的电子器件，其中，所述基材包括Cu、Ag、NiV、Ni或NiNiP。
16.根据权利要求1所述的电子器件，其中，所述载体包括引线框。
17.根据权利要求1所述的电子器件，其中，所述层系统不含Au。
18.一种电子器件，包括：
引线框；
布置在所述引线框上方的半导体芯片；以及
布置在所述半导体芯片和所述引线框之间的层系统，所述层系统包括：
布置在所述半导体芯片上的Al或Ti层；
布置在所述Al或Ti层上的Ti、TiW或W层；
布置在所述Ti、TiW或W层上的Cu或Ag层；
布置在所述Cu或Ag层与所述引线框之间的Sn层。
19.根据权利要求18所述的电子器件，其中，所述引线框包括Cu。
20.根据权利要求18所述的电子器件，其中，所述层系统不含Au。
21.根据权利要求18所述的电子器件，其中，所述引线框的表面涂覆有一个或多个金属层。
22.一种制造电子器件的方法，该方法包括：
提供半导体衬底；
在所述半导体衬底上沉积电接触层；
在所述电接触层上沉积功能层；
在所述功能层上沉积粘附层；
在所述粘附层上沉积焊接层；
在所述焊接层上沉积保护层；以及
将所述半导体衬底附接到载体上。
23.根据权利要求22所述的方法，其中，沉积所述电接触层、所述功能层、所述粘附层、所述焊接层和所述保护层中的一个或多个包括通过物理气相沉积法沉积。
24.根据权利要求22所述的方法，其中，
所述电接触层包括Al或Ti层，
所述功能层包括Ti、TiW或W层，
所述粘附层包括Cu或Ag层，
所述焊接层包括Sn层，以及
所述保护层包括Ag或Au层。
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