CN102980917B - 传感器装置及方法 - Google Patents

传感器装置及方法 Download PDF

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Publication number
CN102980917B
CN102980917B CN201210328529.7A CN201210328529A CN102980917B CN 102980917 B CN102980917 B CN 102980917B CN 201210328529 A CN201210328529 A CN 201210328529A CN 102980917 B CN102980917 B CN 102980917B
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graphene layer
semiconductor chip
plastic material
electrode
chip
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CN102980917A (zh
Inventor
克劳斯·埃里安
伊姆加德·埃舍尔-珀佩尔
京特·鲁赫尔
霍斯特·托伊斯
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Infineon Technologies AG
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Infineon Technologies AG
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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Abstract

本发明公开了一种传感器装置及方法。在基板上形成石墨烯层。将塑性材料沉积在石墨烯层上,以至少部分地覆盖石墨烯层。将基板分成至少两个基板件。

Description

传感器装置及方法
技术领域
本发明涉及一种包括传感器的电子装置,并且更具体地,涉及一种包括流体、化学或生物成分(biocomponent)传感器。
背景技术
在包括传感器的装置的研制中可能要考虑特殊要求,特别地,当设计传感器装置的灵敏度和封装时。例如,一些传感器,诸如流体、化学或生物成分传感器,可能需要一开口,待检测的物质通过该开口施加至传感器。这种封装可能变得大、复杂且昂贵。然而,电子装置的制造商和消费者都期望装置是廉价、尺寸减小且还具有增加的装置功能。
发明内容
本发明公开了一种传感器装置及方法。
根据本发明的一个方面,提供了一种方法,包括:在基板上形成石墨烯层;将塑性材料沉积在石墨烯层上,以至少部分地覆盖石墨烯层;以及将基板分成至少两个基板件。
根据本发明的另一方面,提供了一种制造传感器装置的方法,包括:在包括多个集成电路和多个第一芯片电极的晶片上形成石墨烯层,其中所述石墨烯层接合至所述第一芯片电极;将塑性材料沉积在所述石墨烯层上,以至少部分地覆盖所述石墨烯层;以及将所述晶片分成半导体芯片,其中所述半导体芯片中的至少一个包括电连接至所述第一芯片电极的集成电路。
根据本发明的另一方面,提供了一种制造传感器装置的方法,包括:形成包括多个集成电路和多个第一芯片电极的晶片;将所述晶片分成多个半导体芯片;将所述多个半导体芯片中的至少两个半导体芯片设置在临时载体上,以使所述第一芯片电极面向所述临时载体;用封装材料覆盖所述至少两个半导体芯片;在用所述封装材料覆盖所述至少两个半导体芯片之后去除所述临时载体;在所述至少两个半导体芯片和所述封装材料之上形成石墨烯层,其中所述石墨烯层接合至所述第一芯片电极;将塑性材料沉积在所述石墨烯层上,以至少部分地覆盖所述石墨烯层;以及通过部分地去除所述封装材料使所述至少两个半导体芯片相互分离。
根据本发明的再一方面,提供了一种传感器装置,包括:基板;石墨烯层,所述石墨烯层位于所述基板之上;塑性材料,所述塑性材料位于所述石墨烯层上,以至少部分地覆盖所述石墨烯层;以及至少两个电极,其中所述石墨烯层接合至所述至少两个电极。
附图说明
包括附图以提供对实施方式的进一步理解并且包含并构成本说明书的一部分。这些附图示出了实施方式并且与描述一起用于解释实施方式的原理。其它实施方式和实施方式的许多预期优点将容易理解,因为通过参照以下的详细描述它们变得更好理解。附图的元件无需相对于彼此按照比例绘制。相同的附图标记指出相应的相似部件。
图1A-图1C示意性示出了方法的一个实施方式的横截面视图;
图2示意性示出了传感器装置的一个实施方式的横截面视图;
图3A和图3B示意性示出了传感器装置的横截面视图;
图4示意性示出了传感器装置的一个实施方式的横截面视图;
图5示意性示出了传感器装置的一个实施方式的横截面视图;
图6示意性示出了传感器装置的一个实施方式的横截面视图;
图7A-图7E示意性示出了用于生产传感器装置的方法的一个实施方式的横截面视图;
图8A-图8E示意性示出了用于生产传感器装置的方法的一个实施方式的横截面视图;
图9示意性示出了传感器装置的一个实施方式的横截面视图;
图10A-图10D示意性示出了用于生产传感器装置的方法的一个实施方式的横截面视图;
图11示意性示出了传感器装置的一个实施方式的横截面视图;
图12示意性示出了传感器装置的一个实施方式的横截面视图;
图13A-图13M示意性示出了用于生产传感器装置的方法的一个实施方式的横截面视图;
图14示意性示出了图13G中示出的结构的俯视图;以及
图15示意性示出了传感器装置的一个实施方式的横截面视图。
具体实施方式
在以下的详细描述中,参照附图,附图形成描述的一部分,并且在附图中通过实例的方式示出可以实践本发明的特定实施方式。在这个方面,方向性术语,诸如“顶部”、“底部”、“前方”、“后方”、“居前”、“拖尾”等参照正在描述的附图的方位而使用。因为实施方式的部件可以定位在多个不同的方位上,所以方向性术语用于描述的目的而绝非用于限定的目的。应该理解的是,在不背离本发明的范围的情况下,可以使用其它实施方式,并且可以做出结构上或逻辑上的改变。以下的详细描述因此不应在限制的意义上采用,并且本发明的范围由所附权利要求限定。
应该理解的是,除非另外具体地指明,本文中描述的多个示例性实施方式的特征可以相互结合。
如在该说明书中所采用的,术语“接合(couple)”和/或“电接合”并非意味着表示元件必须直接接合在一起;“接合”和/或“电接合”的元件之间可以设置中间元件。
下面描述可以包括半导体芯片的装置的实施方式。半导体芯片可以是不同的类型,可以通过不同的技术制造,并且可以包括例如集成电子、光电或机电回路和/或无源元件。半导体芯片可以例如设计为逻辑集成电路、模拟集成回路、混合信号集成回路、存储器回路或集成无源元件。它们可以包括控制回路,微处理器或微机电部件。半导体芯片不需要由例如Si、SiC、SiGe、GaAs、AlGaAs的特定半导体材料制成,并且此外,可以包含不是半导体的无机和/或有机材料,诸如,例如绝缘体、塑料或金属。
下面描述的传感器装置可以包括外部接触元件,诸如,例如引线(lead)或焊料沉积物或封装上的接触垫。外部接触元件可以代表封装的外部端子。它们可以从封装的外部接近并且因此可以允许以从封装的外部与装置进行电接触。此外,外部接触元件可以导热并且可以用作用于消散由半导体芯片或嵌入到半导体封装中的芯片产生的热的散热器。外部接触元件可以由任何期望的导电材料构成,例如,由诸如铜、铝或金的金属、金属合金或导电有机材料构成。焊料沉积物,诸如焊料球或焊料块,可以代表外部接触元件或者可以沉积在外部接触元件上。
传感器装置可以包括用于形成封装本体(例如模制本体)的封装材料,该封装本体可以是电绝缘的。该封装材料可以是介质材料并且可以由任何适当的硬质塑料、热塑性塑料或热固性材料或层压材料(预浸料坯)制成。封装材料可以包括填充材料。在其沉积之后,封装材料可以仅部分地硬化并且可以在施加能量(例如,热、UV光等)之后完全地硬化以形成封装本体。可以采用多种技术来用封装本体覆盖半导体芯片,例如,压缩模塑、喷射模塑、粉料模塑、液体模塑、分配或层压。
在一个实施方式中,封装本体可以用于制造所谓的扇出(fan-out)型封装。在扇出型封装中,外部接触垫和/或将半导体芯片连接至外部接触垫的导体迹线(trace)中的至少一些在侧面位于半导体芯片的轮廓的外部或者至少与半导体芯片的轮廓相交。因此,在扇出型封装中,半导体芯片的封装的周缘外部典型地(另外地)用于将封装电接合至外部应用,诸如例如应用板,或者,接合到堆叠的封装应用中,另一个封装。封装的包围半导体芯片的该外部使封装关于半导体芯片的底座(footprint)的接触面积有效地增大,因此导致在封装垫尺寸以及关于后面的加工(例如二级装配)的间距方面的不严格的约束。
在基板(例如晶片或人造晶片或其它载体)上形成石墨烯层(graphene layer)。石墨烯层可以在将基板分成单独的装置之前施加到基板上。通过实例的方式,如果基板是晶片,那么石墨烯层可以在前端加工过程中的晶片级加工期间形成在晶片上。
石墨烯层可以通过旋涂工艺施加。此外,石墨烯层可以通过石墨的微机械裂解或者通过CVD(化学气相沉积)工艺施加。通过实例的方式,旋涂的石墨烯膜可以通过用于产生石墨氧化物的石墨的化学氧化和剥落而产生,其随后通过使用例如液体无水肼作为还原剂和用于分散大的、高质量的石墨烯片的溶剂而还原成石墨烯,并且通过使用离心解决方案来使该材料沉积而获得很好地分散的单层石墨烯片。
图1A至图1C示意性示出了用于形成如图2中所示的传感器装置100的方法的一个实施方式。根据图1A,提供基板1。基板1可以具有板的形式。其可以由不同种类的材料制成。通过实例的方式,基板1可以是半导体晶片、所谓的人造晶片或者由诸如例如聚酰亚胺的塑料制成的板。
将石墨烯层2沉积在基板1的一个主要表面上。在一个实施方式中,石墨烯层2可以是未结构化的层,其可以完全地覆盖基板1的相应主要表面。在另一个实施方式中,石墨烯层2可以作为构造层而形成,其仅部分地覆盖基板1的相应主要表面。
将塑性材料3沉积在石墨烯层2之上(图1C)。塑性材料3可以完全地或者部分地覆盖石墨烯层2。在一个实施方式中,塑性材料3可以以预结构化的图案形式沉积在石墨烯层2上,以仅覆盖石墨烯层2的特定区域。在一个实施方式中,塑性材料3可以作为未结构化的连续层而沉积并且可以然后构造为仅覆盖石墨烯层2的特定区域。
塑性材料3可以由选择性地控制石墨烯层2的覆盖区域暴露于环境中的物质的材料制成。塑性材料3的选择取决于待制造的传感器装置的期望功能。根据选定的塑性材料3以及其对于不同物质的特异性,传感器装置将对不同的物质灵敏。
通过实例的方式,可以设置对于诸如例如CO2、H2O、NO2、NH3等D特定成分或分子敏感的化学传感器。此外,可以设置对于例如DNA、微生物、特定细胞、血液中的氧含量等敏感的生物成分传感器。并且此外,可以设置诸如例如气体传感器或液体传感器的流体传感器装置,例如,以感测上述物质中的一种或多种。
在一个实施方式中,塑性材料3可以包括聚对苯二甲酸乙二醇酯。聚对苯二甲酸乙二醇酯对CO2的渗透性比聚对苯二甲酸乙二醇酯对O2、碳氢化物(carbon hydride)或H2O的渗透性大多于一个数量级。那样,CO2传感器的选择性可以显著地增加。
在一个实施方式中,塑性材料3可以包括聚偏二氯乙烯。聚偏二氯乙烯可以使湿度传感器对O2和CO2的灵敏度增加多于三个数量级。此外,存在对于多种特定化学成分、分子、生物成分或其它物质提供不同的渗透性并且因此提供不同的选择性的多种其它材料。
在一个实施方式(在图1A至图1C中未示出)中,可以在将塑性材料3沉积在石墨烯层2上之前构造石墨烯层2。
在一个实施方式(在图1A至图1C中未示出)中,可以在将塑性材料3沉积在石墨烯层2上之后通过将沉积的塑性材料3用作掩膜(mask)来构造石墨烯层2。下面将参照实施方式进一步解释构造石墨烯层2的全部这些可能工艺。
塑性材料3,在本领域中也被称作滴胶封装(glob top)材料,可以通过例如分配、印刷或者CVD工艺沉积在石墨烯层2上。在一个实施方式中,将塑性材料以预构造形式沉积在石墨烯层2上。通过实例的方式,分配或者印刷过程可用于将诸如例如塑性材料3的岛状物(island)的结构沉积在石墨烯层2上。在一个实施方式中,将塑性材料3作为未结构化的连续层沉积在石墨烯层2上。在该实施方式中,在石墨烯层2上构造塑性材料3可以通过使用光刻方法和/或蚀刻方法提供。
如图1C中示出的,然后通过分离基板1和可能的石墨烯层2以及塑性材料3使传感器装置100彼此分开。通过实例的方式,锯切、切割、蚀刻或者激光束可以用于分离步骤。
下面描述的石墨烯传感器装置的操作原理基于吸附在于塑性材料3下方延伸的石墨烯层2的表面上的物质所导致的它们的导电率(或电阻)的改变。石墨烯层2的导电率(或电阻)对被吸附物高度敏感,达到石墨烯的表面的该种被吸附物通过如上所述的塑性材料3的组成来控制。此外,石墨烯对不同物质的选择性可以通过石墨烯层2的可调表面化学性质来控制。关于这一点应该注意的是,如在本文中使用的术语石墨烯应该在广义上理解。特别地,旨在使术语石墨烯还可以包括具有可修改的化学功能的石墨烯基层,诸如石墨烯衍生物和/或所谓的化学改性石墨烯。
由塑性材料3覆盖的石墨烯层2的导电率或电阻的改变可以通过施加至石墨烯层3的至少两个电接触(electrical contact)来感测。通过实例的方式,图3A和图3B示出了施加至石墨烯层2的两个电接触11,电接触11以隔开的关系布置。在一个实施方式(图3A)中,电接触11沉积在石墨烯层2的上表面上。在一个实施方式(图3B)中,提供电触点11以连接至石墨烯层2的下表面。在这两个实施方式中,电接触11设置成使得石墨烯层2在电接触11之间的长度被分散选择性塑性材料3完全地覆盖。在图3A和图3B中示出的实施方式的原理可以应用于本文中描述的其它实施方式。
图4示出了传感器装置的一个实施方式的横截面视图。在本实施方式中,传感器装置100封装在封装本体14中。封装本体14具有开口17以使塑性材料3暴露于环境。
如下面将进一步更加详细地说明的,封装本体14可以通过模塑(例如,压缩模塑、喷射模塑、粉料模塑、或液体模塑)制成。典型地,在模塑工艺中下模塑半部和上模塑半部用于限定其中形成封装本体14的腔体。
在一个实施方式中,在模塑工艺过程中形成使塑性材料3暴露的开口17。通过实例的方式,上模塑半部可以设有突出到模塑腔体中且压在塑性材料3的上表面上的圆顶状件(dome,凸圆)或柱。那样开口17可以通过模塑工具的圆顶状件而凹入。在另一个实施方式中,开口17可以在模塑工艺以及通过机械加工(例如通过机械或激光钻孔或研磨)形成封装本体14之后形成。
图5示出了传感器装置的一个实施方式的横截面视图。在该传感器装置中传感器装置100容纳在由例如塑料制成的中空壳体18中。与图4中示出的实施方式类似,中空壳体18具有使塑性材料3的上表面的一部分暴露的开口17。开口17的壁可以紧密地连接至塑性材料3的上表面以避免环境中的任何物质进入中空壳体18内的空间。
图6示出了传感器装置的一个实施方式的横截面视图。在该实施方式中,传感器装置100由封装传感器装置100的上表面的层压材料19覆盖。该层压材料可以是具有开口17的聚合物箔(polymer foil)。此外,与在图4和图5中示出的实施方式类似,开口17使塑性材料3的表面的一部分暴露。
在一个实施方式中,层压材料19可以在将基板1分成单独的传感器装置100之前层压在图1C中示出的结构上,在这种情形中,层压材料19可以具有与塑性材料3的图案和/或待从图1C中示出的结构分离的传感器装置100的图案对准的开口17的图案。
应该注意的是,在图4至图6的实施方式中传感器装置100可以装配有如图3A和/或图3B中示出的电接触11。
传感器装置100的功能可以极大地取决于基板1的设计。如果基板1包括含有集成电路的半导体芯片,那么由电接触11感测到的导电率或电阻的变化可以直接测量,并且如果期望的话,通过集成电路处理。为了这个目的,集成电路可以包括模拟电路(诸如例如测试电桥)、数字电路(诸如例如逻辑电路)、半导体存储器、输入/输出电路、和/或混合电路。此外,基板1可以包括加热器和/或温度接收元件和/或用于根据温度接收元件的输出控制加热器的控制电路。加热器、温度接收元件和控制电路每个都可以在包含在基板1中的半导体芯片中或在芯片外(off-chip)实施。
在一个实施方式中,基板1是如例如在芯片卡或智能卡中使用的塑料板。通过实例的方式,图6中的实施方式可以示出了设计为或包含传感器装置的芯片卡或智能卡。在这种智能卡或芯片卡中,石墨烯层2可以沉积在嵌入到塑料板中的半导体芯片(未示出)之上或者可以沉积在诸如例如聚酰亚胺板的板之上。在后面的情形中,塑料板或者介质基板上的导体迹线可以用于电连接至石墨烯层2。应该指出的是,还可以将塑料板用作基板1,而其中没有嵌入任何半导体芯片。在这种情形中,石墨烯层2的导电率可以通过设计为与卡上的外部电极接触的外部装置测量,该卡例如通过导体迹线连接至石墨烯层2。
图7A至图7E示意性示出了用于制造如图7E中示出的半导体装置200的方法,或者如果安装在板上,则如图9中示出的。在图7A至图7E中示出的方法是图1A至图1C中示出的方法的实施。下面描述的制造方法的细节因此可以同样地应用于图1A至图1C中示出的方法。反之亦然,结合附图1A至图1C描述的细节同样地可应用于图7A至图7E的方法。此外,半导体装置200是半导体装置100的实施。下面描述的半导体装置200的细节因此可以同样地施加于半导体装置100,并且反之亦然。
在图7A至图7E中的实施方式中,基板1是由半导体材料制成的晶片20。半导体晶片20可以包括其中嵌入集成电路的体硅(bulk silicon)。下面被称为芯片电极21的芯片接触垫位于半导体晶片20的第一主要面22上。芯片电极21与图3B中示出的实施方式的电接触11相对应。嵌入到半导体晶片20中的集成电路可以经由芯片电极21进行电接触。芯片电极21可以由例如铝或铜的金属制成,并且可以具有任何期望的形状和尺寸。应该注意的是,在图7A至图7E中示出的芯片电极21是旨在接合至石墨烯层2以感测其导电率或电阻的芯片电极。然而,半导体晶片20可以设有在图7B至图7E中未示出的旨在用于例如供电、I/O电路、加热器、温度接收元件等的其它芯片电极。
如图7A中示出的,可以在半导体晶片20的第一主要面22上形成绝缘层23。可以以多种方式制造绝缘层23。例如,绝缘层23可以由气相或者从溶液沉积,或者可以层压在第一主要面22上。此外,薄膜技术方法可以用于绝缘层23的应用。绝缘层23可以由诸如聚对二甲苯、光致抗蚀剂材料、酰亚胺、环氧树脂、脲醛、硅酮的聚合物制成。绝缘层23的厚度可以高达10μm或更高。绝缘层23还可以是例如二氧化硅、氮化硅或像陶瓷的无机材料(诸如硅碳化合物)的硬钝化层。
为了电连接至嵌入到半导体晶片20中的集成电路,绝缘层23可以在如图7A中示出的布置芯片电极21的区域中开口。绝缘层23中的开口24可以,例如,通过使用光刻方法和/或蚀刻方法形成。应该指出的是,绝缘层23的槽脊(land)、条或圆25可以留在芯片电极21的至少一些上并且可以例如位于芯片电极21的中心部分中。
图7B示出了石墨烯层2的沉积。石墨烯层2可以作为未结构化的连续层沉积在晶片级(wafer level)处。因此,石墨烯层2可以沉积在绝缘层23上并沉积在通过绝缘层23的开口暴露的芯片电极21上,并且可以与芯片电极21电接触。石墨烯层2的沉积工艺可以与上面参照其它实施方式描述的一个或多个工艺相同或者类似。因此,为了简明起见,省略了对相应描述的重复。
然后可以如图7C中示出的构造石墨烯层。在一个实施方式中,光致抗蚀剂层可以沉积,例如,旋涂在石墨烯层2的顶部上(未示出)。通过暴露于具有适当波长的光通过掩膜和随后的显影,在光致抗蚀剂层中形成凹槽。随后,如果光致抗蚀剂层是正色调,可以通过使用适当的溶剂或蚀刻剂例如通过使用O2等离子体蚀刻方法去除石墨烯2的通过凹槽暴露的部分。如果光致抗蚀剂材料是负色调,通过溶剂或蚀刻剂去除所有未暴露的区域。在与嵌入到半导体晶片20中的集成电路中的每个相关联的每两个芯片电极21之间,石墨烯层2的剩余部分可以是连续的,并且可以在其它地方具有凹槽。
根据图7D,将塑性材料3沉积在石墨烯层2的剩余部分之上。该步骤与结合图1C中描述的工艺相对应,并且进行参照以避免重复。在一个实施方式中,塑性材料3可以完全地覆盖并且不透气地密封石墨烯层2的剩余部分。在一个实施方式中,塑性材料3至少在其在芯片电极21之间延伸的长度上覆盖石墨烯层2的剩余部分。在所有情形中,在两个芯片电极21之间的一位置处吸附在石墨烯层2上的环境中的物质必须渗透分散选择性塑性材料3。
如已经关于其它实施方式提及的,塑性材料3的沉积可以例如通过分配或者印刷以预结构化的方式完成。如果塑性材料3以预结构化的方式沉积,那么绝缘层23的剩余部分可以帮助沉积工艺。通过实例的方式,如果沉积在半导体晶片20上的塑性材料3是粘性液体,那么绝缘层23的槽脊、条或圆25可以用作障碍物以防止液体分配在半导体晶片20的表面上。那样,槽脊、条或圆25,与液体塑性材料3的粘性一起,可以确保塑性材料3在其在芯片电极21之间延伸的长度上的厚度的最小高度例如大于10μm、50μm或者甚至100μm。那样,可以改进塑性材料3的选择性或者设定最小选择性。
如图7E中示出的,然后可以例如,通过锯切、切割、蚀刻或例如隐形切割的激光烧蚀将半导体晶片20分割成单个半导体芯片30。在图7E中示出了这些半导体芯片30中的仅三个。在图7E中示出的半导体芯片30可以是图2中示出的基板件的一个特定实施。
如图7E中示出的,可以将焊料沉积物26设置在芯片电极21上。焊料沉积物26可以通过所谓的“植球(ball placement)”施加至芯片电极21,其中将由焊料材料构成的预成形的球施加至芯片电极21。作为“植球”的替代方案,焊料沉积物26可以例如,通过之后是热处理工艺的使用焊料浆的丝网印刷术施加。焊接材料可以由例如由以下材料构成的金属合金形成:SnPb、SnAg、SnAgCu、SnAgCuNi、SnAu、SnCu以及SnBi。
在一个实施方式中,将焊接沉积物26施加在晶片级上,即在将半导体晶片20分割成单个半导体芯片30的步骤之前。
在一个实施方式中,将焊接沉积物26施加在单个半导体芯片30上,即在将半导体晶片20分割成为半导体芯片30的步骤之后。
在一个实施方式中,将焊接沉积物26附设至与石墨烯层2直接电连接的芯片电极21。这允许直接外部接近石墨烯层2。附加的焊接沉积物26可以附设至未直接连接至石墨烯层2的芯片电极21(未示出)。
在一个实施方式中,将焊接沉积物26仅附设至不与石墨烯层2直接电连接的芯片电极21(未示出)。在这种情形中,具体地说,形成在半导体芯片30中的集成电路典型地包括感测或测量电路和/或评估电路和/或I/O电路。当然,这些电路中的一个或多个还可以包含在上述实施方式的半导体芯片30中。
参见图9,焊接沉积物26可以用于将装置200电接合至其它部件。
图8A-图8E示意性示出了用于生产半导体装置200的方法的一个实施方式。在图8A和图8B中示出的方法步骤与图7A和图7B中的方法步骤相对应,并且参照对应的描述。
根据图8C,将塑性材料3沉积在连续的(即,未结构化的)石墨烯层2上。塑性材料3的沉积可以以与结合图7D描述的相同的方式完成。
根据图8D,构造石墨烯层2。在该实施方式中,塑性材料3(在本领域中也被称作滴胶封装材料)用作用于构造石墨烯层3的掩膜。即,石墨烯层2的未被塑性材料3覆盖的区域,可以通过溶剂或蚀刻剂去除。通过实例的方式,可以使用O2等离子体蚀刻工艺。因此,石墨烯层2的剩余部分的设计或图案与塑性材料3(图8D)的设计或图案相一致。作为用于构造石墨烯层2的掩膜而提供的塑性材料3确保了石墨烯层2被塑性材料3完全地覆盖并且密封。
如图8E中所示,然后可以将半导体晶片20分割成半导体芯片30。该方法步骤与图7E中示出的方法步骤类似,并且参照所附描述以避免重复。
图9示出了安装在诸如例如PCB(印刷电路板)的载体40上的传感器装置200的横截面视图。在此,通过实例的方式,传感器装置200以倒装定向安装在载体40上。传感器装置200是完成的传感器装置,并且在本领域中也被称作晶片级封装。
图10A至图10D示出了制造传感器装置300的方法的一个实施方式,在图10D中示出了其横截面。为了制造传感器装置300,可以设置在图10B中的横截面中示出的引线框架50。引线框架50可以包括一个或多个冲模垫(die pad,下垫板)51和多个引线52。引线框架50可以由金属或金属合金制成,具体地说铜、同合金、铁、镍、铝、或者其它适当的材料。此外,引线框架50可以镀有例如铜、银、铁、镍或镍磷的导电材料。引线框架50的形状不限于任何尺寸或几何形状。引线框架50可以通过使金属板穿孔制成。
如图10B中示出的,将半导体芯片30(图10A)设置在冲模垫51之上。在本实施方式中,将半导体芯片30安装在冲模垫51上,芯片电极21背离冲模垫51。半导体芯片30可以通过使用适当的粘合剂材料附设至冲模垫51。
应该指出的是,半导体芯片30可以通过上述方法中的任一种制造。具体地说,半导体芯片30可以通过图7A至图7E以及图8A至图8E中示出的方法中的一个制造,省略附设焊接沉积物26的步骤。
如在图10B中进一步示出的,芯片电极21可以通过引线接合法连接至引线框架的引线52。在引线接合法中,接合线53的顶端被引线接合工具压在半导体芯片30的芯片电极21上并且施加热和/或超生波能量以形成金属连接。引线接合工具接着使线53延伸至引线框架50上的焊盘(bonding pad)并且自动点焊至该焊盘。
如图10C中所示,可以将图10B中示出的引线接合结构设置在模塑工具60中。模塑工具60可以包括下半部61和上半部62。使下半部61和上半部62在一起并且闭合,半部61和62限定腔体63,在图10B中示出的结构容纳在该腔体中。上半部62可以具有压在塑性材料3的上表面上的圆顶状件或柱64。除了圆顶状件或柱64抵靠在塑性材料3的顶部表面上并且引线框架50的引线52通过模塑工具固定之外,在图10A中示出的结构可以不具有与腔体63的壁接触的周边区域。因此,半导体芯片30、绝缘层23、芯片电极21、石墨烯层2的暴露部分(如果有)、以及塑性材料3通过引入到腔体63中的封装材料完全地过模塑。该工艺可以伴随有热和压力的施加。在固化之后,封装材料是刚性的并且形成封装本体65(图10D)。封装本体65具有与上模塑半部62的柱或圆顶状件64的形状相一致的开口17,开口17使塑性材料3的中央部分暴露。开口17可以具有等于或小于芯片电极21之间的距离的横向尺寸。如图10D中示出的,封装本体65还可以完全地覆盖半导体芯片30的底部和半导体芯片30的侧面。因此半导体芯片30可以被封装本体65和塑性材料3不透气地密封,并且引线52是图10B中示出的结构的通过封装本体65暴露或者从封装本体突出的唯一构件。
如图11中示出的,在图10A中示出的结构还可以以倒装定向安装在引线框架50上。为此目的,图10A中示出的结构装配有焊接沉积物26以形成与如图7E中示出的传感器装置200类似的装置。传感器装置200然后例如通过焊接回流工艺安装在引线框架50上。随后,将安装在引线框架50上的传感器装置200设置在模塑工具中以制造封装本体67。该模塑工具与如图10C中示出的模塑工具60类似,除了圆顶状件或柱64形成下模塑半部61而不是上模塑半部62的一部分并且穿过引线框架50的引线52之间的开口之外。图11中示出的传感器装置400的制造工艺可以与上面结合图10A至图10D说明的制造工艺相同。此外,与图10D中示出的传感器装置300类似,传感器装置400的封装本体67可以完全地封装芯片30、芯片电极21、绝缘层23、石墨烯层2(如果还未被塑料3覆盖)以及除了其中央表面部分之外的塑性材料3。此外,封装本体的用于使塑性材料3的中央部分暴露的开口的尺寸可以等于或小于芯片电极21之间的距离。
图12示出了传感器装置500的一个实施方式的横截面视图。传感器装置500使用诸如例如所谓的TSLP(轻薄小型无引线封装)的无引线封装。这种类型的封装可以包括包含金属芯片垫502以及隔开的并通过聚合物材料505相互电绝缘的金属接触垫503、504的载体。与传统的引线框架技术(其中引线或者接触垫典型地由穿孔或蚀刻来构造)相比,在无引线封装中使用的该构造方法允许高很多的封装密度。此外,增强了设计的可变形,因为垫502、503、504可以是孤立的,然而在传统的引线技术中,每个接触垫或引线均必须悬置在引线框架的框架结构处。
结构化的绝缘层510可以在载体502、503、504、505上延伸并且可以覆盖芯片垫502与接触垫503、504之间的区域。结构化的绝缘层510可以用作用于电连接至接触垫503、504、石墨烯层2以及可能地电连接至芯片电极(未示出)导电线路511的支撑基座。石墨烯层2和塑性材料3的布置与前述实施方式相同并且为了简明起见而省略。
图13A至图13M示意性示出了制造传感器装置600的方法,在图15中示出了其横截面。图13A至图13M中示出的方法是图1A至图1C中示出的方法的实施。下面描述的制造方法的细节因此可以同样地应用于图1A至图1C中的方法。反之亦然,结合图1A至图1C描述的处理步骤可以应用于下面参照图13A至图13M描述的方法。
如图13A中所示,半导体晶片可以包括其中嵌入有集成电路的体硅。芯片电极21可以包括第一芯片电极21a和第二芯片电极21b。芯片电极21a和21b可以由例如铝或铜的金属或者以上参照芯片电极21描述的任何其它金属制成。
根据图13B,将绝缘层23沉积在晶片20的第一主要面22上。绝缘层23可以例如由与以上参照其它实施方式描述的相同的材料制成。因此,具体地说,绝缘层23可以是聚合物层或者硬钝化层或者由下硬钝化层和上聚合物层组成的层。
如图13B中示出的,将绝缘层23构造为使第一芯片电极21a和第二芯片电极21b暴露。可以应用上面提及的用于构造绝缘层23的所有方法步骤。
如图13C中示出的,然后可以例如通过锯切、切割、蚀刻或激光烧蚀将半导体晶片20分割成半导体芯片30。
为了封装半导体芯片30,如图13D中示出的,设置临时载体80。临时载体80可以是例如金属(诸如镍、钢或不锈钢)、层压材料、膜或材料堆的刚性材料的板。临时载体80可以具有其上可以设置半导体芯片30的至少一个平面。胶带81,例如,双面粘性带,可以层压在临时载体80上。
如图13E中示出的,将半导体芯片30安装在临时载体80上。半导体芯片30可以固定在胶带81上。为了将半导体芯片30附设至临时载体80,可以使用其它类型的附设材料或诸如例如真空保持件的装置。
如图14中示出的,半导体芯片30可以以阵列布置,半导体芯片30以一定距离相互隔开。临时载体80可以是圆形的(参见图14)或者方形的。临时载体80可以具有任何适当的尺寸,例如约为0.2m或0.3m或更大的直径D。
再次参照图13E,可以将半导体芯片30布置在临时载体80之上,半导体芯片的第一主要面22包含面向临时载体80的第一和第二芯片电极21a、22b。在这种情形中,绝缘层23可以直接与胶带81接触。
在将半导体芯片30安装在临时载体80上之后,用封装材料封装半导体芯片,形成封装本体90,如图13F中示出的。封装材料可以覆盖封装芯片30的与第一主要面22相对的第二主要面29,并且还覆盖半导体芯片30的侧面28。半导体芯片30之间的间隙也填充有封装材料。例如,封装材料可以是硬质塑料或者膜复位模塑材料。封装材料可以基于环氧材料并且可以含有包括玻璃(SiO2)或例如Al2O3的其它电绝缘矿物填充材料或有机填充材料的小颗粒的填充材料。模塑材料可以例如通过压缩模塑、喷射模塑、颗粒模塑、粉料模塑、或液体模塑施加。在本领域中嵌入半导体芯片30的封装本体90也被称作人造晶片。
替代地,封装材料可以是具有电绝缘箔或片的形状的聚合物材料,其层压在半导体芯片30的顶部以及临时载体80上。并且在这种情形中,半导体芯片30之间填充有聚合物材料。聚合物材料可以例如是预浸料坯(简称为预浸渍纤维),其是例如玻璃或碳纤维的纤维垫与例如硬质塑性材料的树脂的组合。对于预浸料坯的层压来说,可以使用与PCB生产中相同的或者类似的工艺步骤。
然后从临时载体80上释放封装在封装本体90中的半导体芯片30,并且从封装材料和绝缘层23上剥离胶带81,如图13G中示出的。胶带81可以具有热释放特性,这允许在热处理过程中去除胶带81。在适当的温度下执行从临时载体80上去除胶带81,温度取决于胶带81的热释放特性并且通常高于150°C。
在释放临时载体80和胶带81之后,绝缘层23的背离半导体芯片30的面和封装本体90的底部表面形成大致公共的平面P。如下面描述的以及在图13H至图13K中示出的,可以将再分配层(redistribution layer)施加至平面P。
可以将介质层91沉积在平面P上,如图13H中示出的。可以以多种方式制造介质层91。例如,介质层91可以由气相或者从溶液沉积,或者可以层压在平面P的表面上。此外,薄膜技术方法可以用于介质层91的施加。介质层91可以由聚合物(诸如例如聚对二甲苯、光致抗蚀剂材料、酰亚胺、环氧树脂、硬质塑料、硅酮、氮化硅)或像陶瓷的无机材料(诸如硅碳化合物)制造。还可以省略介质层91。
为了与嵌入到半导体芯片30中的集成电路电连接,介质层91可以在如图13H中示出的布置第一和第二芯片电极21a、21b的区域中开口。介质层91中的开口92可以例如通过使用光刻方法和/或蚀刻方法形成。
可以将金属层93施加至介质层91并且如图13I中示出的构造。根据一个实施方式,金属层93可以由电镀工艺制造。通过实例的方式,在第一步骤中,可以将种子层(seedlayer)(未示出)沉积在介质层91上并且可以由通过光蚀工艺结构化的光致抗蚀剂层(未示出)覆盖。随后可以通过金属材料的电沉积加固种子层的通过光致抗蚀剂层暴露的部分。在金属材料的电沉积过程中,种子层用作电极。可以在无掩膜的区域中将铜或其它金属或金属合金镀在种子层上并且达到通常大于3μm的期望的高度。这样,可以制造金属电极93a和导体迹线93b。在图13I中示出的实施方式中,金属电极93a电连接至第一芯片电极21a,并且导体迹线93b电连接至第二芯片电极21b。
根据图13J,可以将介质层94沉积在金属层93的顶部上。介质层94可以在一定区域中开口以使金属电极93a的一部分和导体迹线93b的一部分暴露。导体迹线93b的暴露部分用作外部接触垫。金属电极93a的暴露部分用作用于与石墨烯层2电连接的电接触。介质层94可以通过使用与上面结合介质层91描述的相同或类似的材料和加工步骤制造。
如图13K中示出的,结构化的石墨烯层2形成为在至少两个电接触之间延伸,这些电接触由与一个半导体芯片30相关联的金属电极93a的暴露部分形成。石墨烯层2可以通过使用与上面结合前述实施方式描述的相同的或类似的材料和加工步骤沉积并构造。结构化的石墨烯层2可以在其周边区域中直接覆盖介质层94,可以在其中心区域中直接覆盖介质层91并且可以在周边区域与中心区域之间的区域中直接连接至金属电极93a。
如图13L中示出的,然后将塑性材料3沉积在石墨烯层2上。塑性材料3可以通过使用与上面结合前述实施方式描述的相同的或类似的材料和加工步骤沉积并构造。具体地说,可以根据在图7A至图7E中示出的实施方式将塑性材料3沉积在预结构化的石墨烯层2上,或者如在图8A至图8E的实施方式中描述的,塑性材料3可以沉积在未结构化的石墨烯层2上并且用作掩膜以构造石墨烯层2。
可以将焊接沉积物26设置在由导体轨道93b的暴露部分提供的外部接触垫上,如图13M中示出的。焊接沉积物26可以通过所谓的“植球”或者诸如例如之后是热处理工艺的丝网印刷术的其它方法施加。焊接沉积物26可以例如由上述材料制成并且可以用于将图15中示出的装置600电连接至其它部件,例如PCB。
如在图13M中通过虚线分割线示出的,装置600通过封装本体90的分离以及可能地层91、93、94的再分配构造(例如通过锯切、切割、蚀刻或者激光束)而相互分开。
通过上述方法制成的传感器装置600(图15)是完成的传感器装置,并且在本领域中也被称作嵌入式晶片级封装。该封装可以是扇出型封装。即,封装本体90允许再分配层延伸超出半导体芯片30的轮廓。因此焊接沉积物26不需要布置在半导体芯片30的轮廓内,而是可以分配在较大区域上。用于焊接沉积物26的布置的增大的区域,意味着焊接沉积物26可以布置在距离彼此较大的距离处和/或与当所有的焊接沉积物26布置在半导体芯片30的轮廓内时的情形相比可以增加焊接沉积物26的最大数量。通过增加传感器装置600的外部端子(例如,焊接沉积物26)的数量,可以增强传感器装置600的功能和性能。通过实例的方式,半导体芯片30中的集成电路可以构造为具有诸如处理器功能、逻辑功能、存储器功能等的增强的功能。
本文中描述的所有实施方式的传感器装置可以用于例如诸如气体或液体的检测,特别是氮氧化物、二氧化碳、一氧化碳、亚硫酸氢、甲烷等。此外,所有这些传感器装置都可以用作例如室内空气质量传感器、用于控制内燃机的传感器、爆炸剂检测器、选择性火检测器等。
此外,尽管相对于多个实施中的仅一个公开了本发明的实施方式的特定特征或者方面,但是该特征或方面可以如所期望的与其它实施中的一个或多个其它特征或方面相结合并且对于任何给定或特定的应用来说是有利的。此外,就在具体实施方式中或在权利要求中使用的术语“包括”、“具有”、“带有”、或者它的其它变形来说,这些术语旨在以类似的方式涵盖术语“包含”。此外,应该理解的是,本发明的实施方式可以在离散电路、部分集成电路或者完全集成电路或者编程装置中实施。此外,术语“示例性的”仅仅意味着作为一个实例,而非最好的或最佳的。还应该理解的是,为了简化和容易理解的目的,本文中描述的特征和/或元件相对于彼此以特定尺寸示出,并且该实际尺寸可能与本文中示出的有很大不同。
尽管本文中示出并描述了特定实施方式,但是本领域普通技术人员可以理解的是,在不背离本发明的范围的情况下,多种替代和/或等同的实施可以替换示出并描述的特定实施方式。本申请旨在涵盖本文中说明的具体实施方式的修改或变型。因此,旨在使本发明仅受权利要求及其等同物限制。

Claims (25)

1.一种制造传感器装置的方法,所述方法包括:
在作为传感器材料的基板上形成石墨烯层;
将塑性材料沉积在所述石墨烯层上,以至少部分地覆盖所述石墨烯层,其中,所述塑性材料由选择性地控制所述石墨烯层的覆盖区域暴露于环境中的物质的材料制成,根据选定的塑性材料以及其对于不同物质的特异性,所述传感器装置将对不同的物质灵敏;以及
然后将所述基板分成至少两个单独的基板件。
2.根据权利要求1所述的方法,其中,所述塑性材料选择性地控制所述石墨烯层的被覆盖部分暴露于环境中的物质。
3.根据权利要求1所述的方法,还包括在将所述塑性材料沉积在所述石墨烯层上之前构造所述石墨烯层。
4.根据权利要求1所述的方法,还包括在将所述塑性材料沉积在所述石墨烯层上之后,通过将沉积的所述塑性材料用作掩膜来构造所述石墨烯层。
5.根据权利要求1所述的方法,其中,沉积所述塑性材料包括通过分配、印刷或化学气相沉积工艺将所述塑性材料沉积在所述石墨烯层上。
6.根据权利要求1所述的方法,所述方法还包括:
以封装材料封装每个基板件以形成封装本体,所述封装本体具有用于使所述塑性材料暴露的开口。
7.根据权利要求6所述的方法,其中,通过模制形成所述封装本体,并且通过模制工具的突出到模制腔体中的圆顶状件形成所述开口。
8.根据权利要求6所述的方法,其中,所述封装材料包括层压材料。
9.一种制造传感器装置的方法,所述方法包括:
在包括多个集成电路和多个第一芯片电极的半导体晶片上形成石墨烯层,其中,所述石墨烯层接合至所述第一芯片电极;
将塑性材料沉积在所述石墨烯层上,以至少部分地覆盖所述石墨烯层,其中,所述塑性材料由选择性地控制所述石墨烯层的覆盖区域暴露于环境中的物质的材料制成,根据选定的塑性材料以及其对于不同物质的特异性,所述传感器装置将对不同的物质灵敏;以及
然后将所述半导体晶片分成多个半导体芯片,其中,所述半导体芯片中的至少一个包括电连接至所述第一芯片电极的集成电路。
10.根据权利要求9所述的方法,所述方法还包括:
将所述半导体芯片附接至引线框架的冲模垫;以及
将所述半导体芯片的第二芯片电极结合至所述引线框架的引线。
11.根据权利要求10所述的方法,所述方法还包括:
以封装材料封装所述半导体芯片和所述引线框架以形成封装本体,所述封装本体具有用于使所述塑性材料暴露的开口。
12.根据权利要求10所述的方法,所述方法还包括:
将所述半导体芯片和所述引线框架设置在中空壳体中;以及
将所述半导体芯片的所述第二芯片电极结合至延伸到所述中空壳体中的引线。
13.一种制造传感器装置的方法,所述方法包括:
形成包括多个集成电路和多个第一芯片电极以及第二芯片电极的晶片;
将所述晶片分成多个半导体芯片;
将所述多个半导体芯片中的至少两个半导体芯片设置在临时载体上,以使所述第一芯片电极和所述第二芯片电极面向所述临时载体;
用封装材料覆盖所述至少两个半导体芯片;
在用所述封装材料覆盖所述至少两个半导体芯片之后去除所述临时载体;
在所述至少两个半导体芯片和所述封装材料之上形成石墨烯层,其中,所述石墨烯层接合至所述第一芯片电极;
将塑性材料沉积在所述石墨烯层上,以至少部分地覆盖所述石墨烯层,其中,所述塑性材料由选择性地控制所述石墨烯层的覆盖区域暴露于环境中的物质的材料制成,根据选定的塑性材料以及其对于不同物质的特异性,所述传感器装置将对不同的物质灵敏;以及
通过部分地去除所述封装材料使所述至少两个半导体芯片相互分离。
14.根据权利要求13所述的方法,其中,所述塑性材料选择性地控制所述石墨烯层的被覆盖部分暴露于环境中的物质。
15.根据权利要求13所述的方法,还包括在将所述塑性材料沉积在所述石墨烯层上之前构造所述石墨烯层。
16.根据权利要求13所述的方法,还包括在沉积所述塑性材料之后,通过将沉积的所述塑性材料用作掩膜来构造所述石墨烯层。
17.根据权利要求13所述的方法,所述方法还包括:
将包括至少一个聚合物层和至少一个结构化金属层的电再分配结构施加在所述半导体芯片和所述封装材料之上;
将所述第二芯片电极电连接至所述至少一个结构化金属层;以及
在至少部分地超出每个半导体芯片的侧面轮廓的位置处将焊接球附接至所述至少一个结构化金属层。
18.一种制造传感器装置的方法,所述方法包括:
在半导体芯片之上形成石墨烯层;
将塑性材料形成在所述石墨烯层上,以至少部分地覆盖所述石墨烯层,其中,所述塑性材料由选择性地控制所述石墨烯层的覆盖区域暴露于环境中的物质的材料制成,根据选定的塑性材料以及其对于不同物质的特异性,所述传感器装置将对不同的物质灵敏;以及
在所述半导体芯片之上形成第一电极和第二电极,其中,所述石墨烯层接合至所述第一电极和所述第二电极,其中,所述半导体芯片包括接合至所述第一电极和所述第二电极并构造成测量所述第一电极和所述第二电极之间的电阻的集成电路。
19.根据权利要求18所述的方法,还包括形成传感器壳体,所述传感器壳体至少部分地容纳所述半导体芯片并具有使所述塑性材料暴露于所述传感器壳体外部的环境的开口。
20.根据权利要求19所述的方法,其中,所述传感器壳体包括模制的封装材料。
21.根据权利要求19所述的方法,其中,所述传感器壳体包括中空壳体。
22.根据权利要求18所述的方法,其中,所述半导体芯片是未封装的半导体芯片。
23.根据权利要求18所述的方法,其中,所述塑性材料包括聚对苯二甲酸乙二醇酯和聚偏二氯乙烯中的一种或多种。
24.根据权利要求18所述的方法,其中,所述半导体芯片是嵌入式晶片级封装。
25.根据权利要求18所述的方法,其中,所述半导体芯片是无引线封装。
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Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9475709B2 (en) 2010-08-25 2016-10-25 Lockheed Martin Corporation Perforated graphene deionization or desalination
EP2573804A1 (en) * 2011-09-21 2013-03-27 Nxp B.V. Integrated circuit with sensor and manufacturing method thereof
KR102071841B1 (ko) 2011-12-21 2020-01-31 더 리전트 오브 더 유니버시티 오브 캘리포니아 상호 연결 주름진 탄소 기반 네트워크
US9779884B2 (en) 2012-03-05 2017-10-03 The Regents Of The University Of California Capacitor with electrodes made of an interconnected corrugated carbon-based network
TWI434949B (zh) * 2012-03-14 2014-04-21 Nat Univ Tsing Hua 化學氣相沈積生成石墨烯之方法
KR101374145B1 (ko) * 2012-04-19 2014-03-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US8941396B2 (en) * 2012-04-25 2015-01-27 Eastman Kodak Company Electronic sensing system with environmental sensor patch
US9610546B2 (en) 2014-03-12 2017-04-04 Lockheed Martin Corporation Separation membranes formed from perforated graphene and methods for use thereof
US10653824B2 (en) 2012-05-25 2020-05-19 Lockheed Martin Corporation Two-dimensional materials and uses thereof
US9744617B2 (en) 2014-01-31 2017-08-29 Lockheed Martin Corporation Methods for perforating multi-layer graphene through ion bombardment
US9834809B2 (en) 2014-02-28 2017-12-05 Lockheed Martin Corporation Syringe for obtaining nano-sized materials for selective assays and related methods of use
US9870895B2 (en) 2014-01-31 2018-01-16 Lockheed Martin Corporation Methods for perforating two-dimensional materials using a broad ion field
TW201504140A (zh) 2013-03-12 2015-02-01 Lockheed Corp 形成具有均勻孔尺寸之多孔石墨烯之方法
US9248709B2 (en) 2013-06-13 2016-02-02 Infineon Technologies Ag RFID-tag, a TPMS device, a tire, a receiver device and a method for providing information related to identification of a tire
US9572918B2 (en) 2013-06-21 2017-02-21 Lockheed Martin Corporation Graphene-based filter for isolating a substance from blood
KR101467116B1 (ko) 2013-09-25 2014-12-01 성균관대학교산학협력단 표면 처리 방법
US10107867B2 (en) 2013-11-12 2018-10-23 Infineon Technologies Ag Sensor arrangement, battery cell and energy system
WO2015116857A2 (en) 2014-01-31 2015-08-06 Lockheed Martin Corporation Processes for forming composite structures with a two-dimensional material using a porous, non-sacrificial supporting layer
CN106232205A (zh) 2014-03-12 2016-12-14 洛克希德马丁公司 由有孔石墨烯形成的分离膜
DE102014007137A1 (de) * 2014-05-16 2015-11-19 Dräger Safety AG & Co. KGaA Elektrode für einen elektronischen Gassensor, Herstellungsverfahren für eine Elektrode und Verwendung einer Elektrode
EP2765410B1 (en) 2014-06-06 2023-02-22 Sensirion AG Gas sensor package
EP2952886B1 (en) * 2014-06-06 2020-09-23 Sensirion AG Method for manufacturing a gas sensor package
CA2952233C (en) 2014-06-16 2023-07-25 The Regents Of The University Of California Hybrid electrochemical cell
DE102014212282B4 (de) * 2014-06-26 2023-11-09 Infineon Technologies Ag Graphen-Gassensor zur Messung der Konzentration von Kohlendioxid in Gasumgebungen
US10352726B2 (en) 2014-07-22 2019-07-16 Brewer Science, Inc. Thin-film resistive-based sensor
MX2017002738A (es) 2014-09-02 2017-08-02 Lockheed Corp Membranas de hemodialisis y hemofiltracion basadas en un material de membrana bidimensional y metodos que emplean las mismas.
US8981346B1 (en) * 2014-09-30 2015-03-17 The United States Of America As Represented By The Secretary Of The Navy Capacitive-based graphene sensor
US20160118353A1 (en) * 2014-10-22 2016-04-28 Infineon Techologies Ag Systems and Methods Using an RF Circuit on Isolating Material
MX2017006315A (es) 2014-11-18 2017-08-21 Univ California Compuesto de red a base de carbono corrugada interconectada (iccn) porosa.
EP3045909B1 (en) 2015-01-14 2020-11-04 Sensirion AG Sensor package
KR101665242B1 (ko) 2015-03-20 2016-10-11 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이의 제조 방법
EP3076436A1 (en) 2015-03-30 2016-10-05 Nokia Technologies OY A method and apparatus for providing a transistor
KR102327738B1 (ko) 2015-06-18 2021-11-17 삼성전기주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
CA2994549A1 (en) 2015-08-05 2017-02-09 Lockheed Martin Corporation Perforatable sheets of graphene-based material
WO2017023377A1 (en) 2015-08-06 2017-02-09 Lockheed Martin Corporation Nanoparticle modification and perforation of graphene
CN106706710A (zh) * 2015-11-11 2017-05-24 中国科学院上海微系统与信息技术研究所 基于硫掺杂石墨烯的氮氧化物气体传感器及其制备方法
AU2016378400B2 (en) 2015-12-22 2021-08-12 The Regents Of The University Of California Cellular graphene films
CA3009208A1 (en) 2016-01-22 2017-07-27 The Regents Of The University Of California High-voltage devices
WO2017165548A1 (en) 2016-03-23 2017-09-28 The Regents Of The University Of California Devices and methods for high voltage and solar applications
CN109074967B (zh) 2016-04-01 2022-07-08 加利福尼亚大学董事会 在碳布上直接生长聚苯胺纳米管用于柔性高性能超级电容器
JP2019521055A (ja) 2016-04-14 2019-07-25 ロッキード・マーチン・コーポレーション グラフェン欠陥の選択的界面緩和
WO2017180135A1 (en) 2016-04-14 2017-10-19 Lockheed Martin Corporation Membranes with tunable selectivity
WO2017180134A1 (en) 2016-04-14 2017-10-19 Lockheed Martin Corporation Methods for in vivo and in vitro use of graphene and other two-dimensional materials
CA3020874A1 (en) 2016-04-14 2017-10-19 Lockheed Martin Corporation Two-dimensional membrane structures having flow passages
WO2017180133A1 (en) 2016-04-14 2017-10-19 Lockheed Martin Corporation Methods for in situ monitoring and control of defect formation or healing
KR20190019907A (ko) 2016-04-14 2019-02-27 록히드 마틴 코포레이션 자유-플로팅 방법을 사용한 대규모 이송을 위한 그래핀 시트 취급 방법
CN107492528A (zh) 2016-06-13 2017-12-19 恩智浦美国有限公司 具有石墨烯条带的柔性半导体装置
US11097951B2 (en) 2016-06-24 2021-08-24 The Regents Of The University Of California Production of carbon-based oxide and reduced carbon-based oxide on a large scale
JP7109790B2 (ja) 2016-08-31 2022-08-01 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア 炭素系材料を含むデバイス及びその製造
DE102017210585B3 (de) * 2017-06-23 2018-09-27 Robert Bosch Gmbh Bondpadschichtsystem, Gassensor und Verfahren zur Herstellung eines Gassensors
US11133134B2 (en) 2017-07-14 2021-09-28 The Regents Of The University Of California Simple route to highly conductive porous graphene from carbon nanodots for supercapacitor applications
US10677768B2 (en) 2017-07-29 2020-06-09 Infineon Technologies Ag Gas sensing systems and methods of operation thereof
TWI650152B (zh) * 2017-08-08 2019-02-11 研能科技股份有限公司 空氣過濾防護器
TWI651110B (zh) * 2017-08-22 2019-02-21 研能科技股份有限公司 空氣過濾防護器
CN108209897A (zh) * 2018-01-30 2018-06-29 四川东鼎里智信息技术有限责任公司 一种可穿戴产品的移动医疗助理系统
CN108332772A (zh) * 2018-02-08 2018-07-27 四川东鼎里智信息技术有限责任公司 一种基于石墨烯的远程红外线体能恢复控制系统
CN108294740A (zh) * 2018-02-08 2018-07-20 四川东鼎里智信息技术有限责任公司 一种石墨烯心率传感系统
CN108363488A (zh) * 2018-02-08 2018-08-03 四川东鼎里智信息技术有限责任公司 一种可穿戴全息传送系统
CN108254107A (zh) * 2018-02-08 2018-07-06 四川东鼎里智信息技术有限责任公司 一种石墨烯压力传感系统
KR102528016B1 (ko) * 2018-10-05 2023-05-02 삼성전자주식회사 솔더 부재 실장 방법 및 시스템
US11189588B2 (en) 2018-12-31 2021-11-30 Micron Technology, Inc. Anisotropic conductive film with carbon-based conductive regions and related semiconductor assemblies, systems, and methods
US10854549B2 (en) 2018-12-31 2020-12-01 Micron Technology, Inc. Redistribution layers with carbon-based conductive elements, methods of fabrication and related semiconductor device packages and systems
CN112244840B (zh) * 2019-07-02 2023-08-04 复旦大学附属中山医院 一种石墨碳盘状电极及其制备方法和使用方法
US10938032B1 (en) 2019-09-27 2021-03-02 The Regents Of The University Of California Composite graphene energy storage methods, devices, and systems
CN111732071A (zh) * 2020-06-12 2020-10-02 西安邮电大学 一种石墨烯薄膜衬底的制备方法及其应用
US11573203B2 (en) * 2020-09-21 2023-02-07 Texas Instruments Incorporated Humidity sensor
US11932946B2 (en) 2021-11-10 2024-03-19 Lyten, Inc. Tuning porous surface coatings using a plasma spray torch
US20230212729A1 (en) * 2021-11-10 2023-07-06 Lyten, Inc. Tuned porous surface coatings

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5401376A (en) * 1993-04-09 1995-03-28 Ciba Corning Diagnostics Corp. Electrochemical sensors
WO2009089268A2 (en) * 2008-01-07 2009-07-16 Wisys Technology Foundation, Inc. Method and apparatus for identifying and characterizing material solvents and composite matrices and methods of using same
WO2009154212A1 (ja) * 2008-06-19 2009-12-23 味の素株式会社 加工食品及びその製造方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19929026B4 (de) * 1999-06-25 2011-02-24 Robert Bosch Gmbh Verfahren zur Herstellung eines Drucksensors
TW569424B (en) 2000-03-17 2004-01-01 Matsushita Electric Ind Co Ltd Module with embedded electric elements and the manufacturing method thereof
JP3619773B2 (ja) * 2000-12-20 2005-02-16 株式会社ルネサステクノロジ 半導体装置の製造方法
DE10232053A1 (de) * 2002-07-16 2004-02-05 Robert Bosch Gmbh Aufprallsensor
JP4173024B2 (ja) * 2003-02-14 2008-10-29 富士通メディアデバイス株式会社 電子部品の製造方法及びそのベース基板
WO2005001895A2 (en) * 2003-06-12 2005-01-06 Georgia Technology Research Corporation Patterned thin film graphite devices and method for making same
WO2005057654A2 (en) * 2003-12-10 2005-06-23 Philips Intellectual Property & Standards Gmbh Wire-bonded semiconductor component with reinforced inner connection metallization
JP2006073586A (ja) * 2004-08-31 2006-03-16 Renesas Technology Corp 半導体装置の製造方法
US8012420B2 (en) 2006-07-18 2011-09-06 Therm-O-Disc, Incorporated Robust low resistance vapor sensor materials
DE102006058010B9 (de) * 2006-12-08 2009-06-10 Infineon Technologies Ag Halbleiterbauelement mit Hohlraumstruktur und Herstellungsverfahren
US7732859B2 (en) * 2007-07-16 2010-06-08 International Business Machines Corporation Graphene-based transistor
JP4450031B2 (ja) * 2007-08-22 2010-04-14 株式会社デンソー 半導体部品
EP3540436B1 (en) * 2007-09-12 2023-11-01 President And Fellows Of Harvard College High-resolution molecular sensor
DE102008005153A1 (de) * 2008-01-18 2009-07-23 Robert Bosch Gmbh Druckmessmodul
US20090236608A1 (en) * 2008-03-18 2009-09-24 Georgia Tech Research Corporation Method for Producing Graphitic Patterns on Silicon Carbide
US8698226B2 (en) 2008-07-31 2014-04-15 University Of Connecticut Semiconductor devices, methods of manufacture thereof and articles comprising the same
US8858003B2 (en) * 2008-10-27 2014-10-14 Microchip Technology Incorporated Physical force capacitive touch sensors having conductive plane and backlighting
WO2010065517A1 (en) * 2008-12-01 2010-06-10 The Trustees Of Columbia University In The City Of New York Electromechanical devices and methods for fabrication of the same
US20120003438A1 (en) * 2009-02-20 2012-01-05 University Of Florida Research Foundation, Inc. Graphene processing for device and sensor applications
US8211782B2 (en) 2009-10-23 2012-07-03 Palo Alto Research Center Incorporated Printed material constrained by well structures
US8105928B2 (en) * 2009-11-04 2012-01-31 International Business Machines Corporation Graphene based switching device having a tunable bandgap
US20120255860A1 (en) * 2009-12-24 2012-10-11 Proxim Diagnostics Carbon-based electrodes with graphene modification
US8080441B2 (en) * 2010-01-12 2011-12-20 Cree, Inc. Growing polygonal carbon from photoresist
KR20110098441A (ko) * 2010-02-26 2011-09-01 삼성전자주식회사 그라핀 전자 소자 및 제조방법
US20110227043A1 (en) * 2010-03-19 2011-09-22 International Business Machines Corporation Graphene sensor
JP2012015481A (ja) * 2010-06-01 2012-01-19 Sony Corp 電界効果トランジスタの製造方法、電界効果トランジスタおよび半導体酸化グラフェンの製造方法
KR20110133352A (ko) * 2010-06-04 2011-12-12 삼성테크윈 주식회사 미세 구조물, 이를 구비하는 미세 전자 기계 시스템, 및 그 제조 방법
KR101878750B1 (ko) * 2010-06-18 2018-07-17 삼성전자주식회사 알칼리 금속 함유 단일층 그라펜 및 이를 포함하는 전기소자
CN102959708B (zh) * 2010-06-29 2016-05-04 柯立芝照明有限公司 具有易弯曲基板的电子装置
US20120212242A1 (en) * 2011-02-22 2012-08-23 Dioxide Materials Inc Graphene-Based Sensor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5401376A (en) * 1993-04-09 1995-03-28 Ciba Corning Diagnostics Corp. Electrochemical sensors
WO2009089268A2 (en) * 2008-01-07 2009-07-16 Wisys Technology Foundation, Inc. Method and apparatus for identifying and characterizing material solvents and composite matrices and methods of using same
WO2009154212A1 (ja) * 2008-06-19 2009-12-23 味の素株式会社 加工食品及びその製造方法

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US20150287788A1 (en) 2015-10-08
DE102012108305B4 (de) 2015-10-29
US20140264255A1 (en) 2014-09-18
CN102980917A (zh) 2013-03-20
US8759153B2 (en) 2014-06-24

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