CN102956684A - 集成晶胞的掩埋场环场效应晶体管植入空穴供应通路 - Google Patents

集成晶胞的掩埋场环场效应晶体管植入空穴供应通路 Download PDF

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CN102956684A
CN102956684A CN2012102967710A CN201210296771A CN102956684A CN 102956684 A CN102956684 A CN 102956684A CN 2012102967710 A CN2012102967710 A CN 2012102967710A CN 201210296771 A CN201210296771 A CN 201210296771A CN 102956684 A CN102956684 A CN 102956684A
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source electrode
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heavy doping
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semiconductor power
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马督儿·博德
安荷·叭剌
哈姆扎·耶尔马兹
管灵鹏
胡军
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

本发明提出了一种形成在半导体衬底上的半导体功率器件，包括在轻掺杂区上方的半导体衬底的顶面附近的重掺杂区。该半导体功率器件还包括一个本体区、一个源极区以及一个设置在半导体衬底的顶面附近的栅极，以及一个设置在半导体衬底的底面处的漏极。该半导体功率器件还包括在重掺杂区中打开源极沟槽，并用导电沟槽填充材料填充，与顶面附近的源极区电接触。该半导体功率器件还包括一个掩埋场环区，设置在源极沟槽下方，掺杂物的导电类型与重掺杂区的导电类型相反。在一个可选实施例中，该半导体功率器件还包括被源极沟槽侧壁包围的掺杂区，掺杂物的导电类型与掩埋场环区的导电类型相同，作为电荷供应通路。

Description

集成晶胞的掩埋场环场效应晶体管植入空穴供应通路
技术领域
本发明主要关于半导体功率器件。更确切的说，本发明是关于集成晶胞的场效应晶体管（BUF-FET）植入空穴供应通路，用于制备带有掩埋场环的改良型功率器件结构的新型结构和方法，以便保持很高击穿电压，同时获得很低的漏源电阻RdsA。
背景技术
配置和制备高压半导体功率器件的传统技术，仍然遇到进一步改善性能的困境和局限。在垂直半导体功率器件中，漏源电阻之间存在一个取舍，也就是说，导通状态电阻（通常用RdsA表示（即Rdsx有源区））作为性能特征，以及功率器件可承受的击穿电压。击穿电压（BV）和RdsA之间的关系通常可以表示为：RdsA与（BV）2.5成正比。为了降低RdsA，可以制备掺杂浓度较高的外延层。然而，重掺杂外延层也降低了半导体功率器件可承受的击穿电压。
为了解决上述性能取舍造成的困难和局限，已经提出了多种器件结构。图1A表示传统的浮动岛和厚底部沟槽氧化物金属氧化物半导体（FITMOS）场效应晶体管（FET）的剖面图，厚底部沟槽氧化物金属氧化物半导体场效应晶体管在沟槽栅极中配置厚底部氧化物，以及在沟槽栅极下方配置浮动P-掺杂岛，以改善电场形状。浮动岛中P-掺杂物的电荷补偿有利于提高N-外延掺杂浓度，从而降低RdsA。此外，沟槽栅极中的厚底部氧化物降低了栅漏耦合，从而降低了栅漏电荷Qgd。在顶部外延层和浮动岛附近的底层上承载较高的击穿电压，也是该器件所具有的优势。然而，浮动P区使开关时产生较高的动态导通电阻。
在美国专利5637898中，Baliga提出了一种具有高击穿电压和低导通状态电阻的功率晶体管。如图1B所示的功率晶体管为半导体衬底在中的垂直场效应晶体管，包括在漂流区中具有底部的沟槽，作为绝缘栅电极，以便根据开启栅极偏压的应用，调节通道和漂流区的导电性。绝缘栅电极包括一个在通道中的导电栅极，以及一个布满通道和漂流区附近的沟槽侧壁的绝缘区。绝缘区具有一个在沟槽侧壁和栅极之间的非均匀剖面区，通过抑制沟槽底部的高电场拥挤现象，增强晶体管的正向电压闭锁性能。绝缘区沿侧壁部分的厚度较大，沿漂流区附近延伸，沿侧壁部分的厚度较小，沿通道区附近延伸。漂流区也是非均匀掺杂的，具有线性阶梯掺杂结构，沿漏极区到通道区的方向递减，提供很低的导通状态电阻。本器件中的电荷补偿是通过栅极电极获得的。然而，大栅极电极的存在显著提高了该结构的栅漏电容，产生较高的开关损耗。此外，具有漂流区中线性阶梯掺杂，额外地增加了制备的复杂性。
在美国专利7335944中，Banerjee等人提出了如图1C所示的晶体管，包括第一和第二沟槽，限定半导体衬底中的台面结构。第一和第二场板部件分别设置在第一和第二沟槽中，每个第一和第二场板部件与台面结构被电介质层隔开。台面结构包括多个部分，每个部分都有一个基本恒定的掺杂浓度梯度，每个部分的梯度至少比另一部分的梯度大10%，也就是说，漂流区中的掺杂结构梯度变化作为漂流区的垂直深度的函数。每个场板都通过电连接到源极电极。在本器件中，通过连接到源极上的场板实现了电荷补偿。然而，制备这种结构需要复杂的制备工艺，包括深沟槽和厚衬里氧化物。
基于上述原因，有必要提出一种半导体功率器件的新型器件结构和新制备方法，降低导通状态电阻，同时提高功率器件可承受的击穿电压，从而解决上述困难和局限。
发明内容
因此，本发明的一个方面在于，提出了一种新型、改良的半导体功率器件结构和制备方法，使半导体功率器件具有较低的RdsA，同时维持很高的可承载击穿电压。
确切地说，本发明的一个方面在于，提出了一种新型、改良的半导体功率器件结构和制备方法，使半导体功率器件具有较低的RdsA，通过在半导体衬底的顶面附近制备一个重掺杂外延层，然后在重掺杂外延层中制备导电沟槽，连接到源极电极，掩埋的场环形成在每个源极沟槽下方，用作重掺杂漂流区的电荷补偿层，使它可以在承受高电压的同时，保持低串联电阻。
本发明的另一个方面在于，提出了一种新型、改良的半导体功率器件结构和制备方法，包括顶面作为一个带有电荷补偿漂流区的MOSFET，还提供用多晶硅填充的沟槽，连接到源极电极，包括底部掺杂区，作为掩埋场环，某些导电沟槽在沟槽侧壁附近含有掺杂区，作为电荷供应通路。
本发明的另一个方面在于，提出了一种新型、改良的半导体功率器件结构和制备方法，用于制备一种半导体功率器件，这种半导体功率器件在器件的顶面附近，含有一个重掺杂外延层，由上方的MOS电容器和底部的掩埋场环提供电荷补偿，以及一个没有电荷补偿的轻掺杂第二外延层，在重掺杂第一外延层的下方，沟槽提供到掩埋场环的接口，用于较深的电荷补偿，从而使器件减小导通状态电阻的同时，保持高击穿电压。
本发明的一个较佳实施例主要提出了一种形成在半导体衬底中的半导体功率器件，包括一个重掺杂区，在半导体衬底的顶面附近，被重掺杂区承载着的轻掺杂区上方。该半导体功率器件还包括一个源极区和一个栅极，设置在半导体衬底的顶面附近，以及一个漏极，设置在半导体衬底的底面上。该半导体功率器件还包括源极沟槽，在重掺杂区内打开，用导电沟槽填充，填充材料与顶面附近的源极区电接触。该半导体功率器件还包括掩埋场环区，设置在源极沟槽下方，并用导电类型与重掺杂区相反的掺杂物掺杂。在一个较佳实施例中，半导体功率器件还包括被源极沟槽侧壁包围的掺杂区，用导电类型与掩埋场环区相同的掺杂物掺杂，作为电荷供应通路。
此外，本发明提出了一种在半导体衬底中制备半导体功率器件的方法。该方法包括，制备承载着轻掺杂中间层的半导体衬底，轻掺杂中间层带有一个重掺杂顶层。该方法还包括在重掺杂层中打开多个源极通道，然后在每个源极通道下方，植入一个掩埋场环。该方法还包括用导电沟槽填充材料填充源极沟槽，将半导体衬底顶面上的源极电极电连接到设置在平面栅极附近的源极区，平面栅极通过延伸到半导体衬底顶面上的栅极绝缘层绝缘。在一个可选实施例中，在源极沟槽下方植入掩埋场区的步骤还包括，进行倾斜植入，以便在沟槽侧壁附近构成掺杂区，沿源极沟槽作为电荷供应通路，从重掺杂区延伸到轻掺杂中间层。
阅读以下详细说明并参照附图之后，本发明的这些和其他的特点和优势，对于本领域的技术人员而言，无疑将显而易见。
附图说明
图1A至1C表示传统的半导体功率器件的三种不同结构的剖面图。
图2A表示掩埋场环场效应晶体管（BUF-FET）的剖面图。
图2B表示带有空穴供应通路的掩埋场环场效应晶体管（BUF-FET）的剖面图。
图3A至4B表示用于制备图2A和2B所示的半导体功率器件的制备工艺的一系列剖面图。
具体实施方式
图2A和2B表示掩埋场环场效应晶体管（Buried field ring field effect transistor，简称BUF-FET）100和本发明所述的带有功率器件的空穴供应通路的BUF-FET 102的两个剖面图。BUF-FET 100和102形成在半导体衬底中，半导体衬底具有一个第一导电类型的重掺杂区105，例如N型衬底的浓度约为1e20cm-3。第一导电类型的轻掺杂区110，例如N-型掺杂区110的浓度约为1e14cm-3至5e15cm-3，位于重掺杂衬底105上方。重掺杂区112，也是第一导电类型，浓度约为1e15cm-3至5e16cm-3，位于轻掺杂区110上方。还可选择，由于N型衬底105、轻掺杂N-型层110以及重掺杂N-型层112都具有一个单晶结构，因此可以将它们统称为半导体衬底。此外，轻掺杂N-型层110通常称为底部或下部半导体层，重掺杂N-型层112通常称为上部半导体层。BUF-FETs 100和102为垂直器件，漏极（或集电极）电极120设置在衬底底面，源极（或发射极）电极130设置在顶面上。BUF-FETs 100和102还包括多个沟槽104，垫有电介质层（例如氧化层145），并用多晶硅层填充。沟槽104的底部终止在重掺杂N-型层112中，或延伸到轻掺杂N-型层110的顶面内。填充在沟槽104中的多晶硅层140，连接到源极电极130。源极区125形成在沟槽104周围的顶面附近，并且电连接到源极电极130。平面栅极135形成在N-型层112的顶面上，覆盖着沟槽104侧壁附近的区域，以及覆盖在源极区125的顶面上。重掺杂N-型层112降低了该区域中的RdsA，并且通过上方的MOS电容器和底部的掩埋场环进行电荷补偿。N-型掺杂外延层110没有电荷补偿，因此应该是轻掺杂的。
在一些可选实施方式中，至少在一部分沟槽104的侧壁附近的N-型层112中形成有本体区115，本体区115位于重掺杂N-型层112的顶部，形成在本体区115内并邻近于沟槽104侧壁的源极区125位于N-型层112的顶面附近。平面栅极135及其下方的栅极氧化物层还至少覆盖在本体区115的顶面上，以便当平面栅极135处于工作状态时，可以在本体区115中形成一个源极区125和N-型层112之间的并位于本体区115的顶面附近的电流传导通道。
在BUF-FET 100和102中，沟槽多晶硅140短接至源极电极，用于电荷补偿。此外，沟槽104底面下方的P-掺杂区150作为掩埋场环（BUF）。与BUF-FET 100相比，BUF-FET 102还包括一个P-掺杂区160作为空穴-供应通路，P-掺杂区160包围着某些沟槽104’的沟槽侧壁，用于进一步降低RdsA。BUF-FET 100和102的顶端晶胞结构，与绝缘栅双极晶体管（IGBT）大致相同，其中沟槽深度约为6微米，衬里氧化层（liner oxide layer，也称作衬垫氧化层）145的厚度约为5500埃。传统的IGBT和BUF-FET 100、102之间的区别在于，BUF-FET 100、102的外延层包括两个外延层110和112，上部外延层112用砷掺杂，下部外延层110用磷掺杂。在下部外延层110中扩散磷离子，可以防止沟槽源极下面的掩埋场环区150阻塞的电流通路。下文还将详细介绍，打开沟槽后可以植入掩埋场环区150，其中掩埋场环区150的掺杂浓度为4.5e12cm-3，植入能量约为500KeV。设计沟槽104（或104’）之间的台面结构区域，以降低结型场效应管JFET电阻，使JFET电阻对RdsA的影响可以忽略。优化结构之后，RdsA可以降至20至80毫欧cm2。为了进一步降低RdsA，同时保持高击穿电压，要在N-外延层112下方较深处制备一个掩埋场环（BUF）掺杂区150。BUF-FET 100和102可以一起形成在半导体器件的不同区域中。掩埋场环（BUF）掺杂区150用于为半导体器件的有源区域中的重掺杂N-外延层112提供电荷补偿，也作为器件边缘的终接的掩埋场环。
图3A至4B表示本发明所述器件的处理步骤的一系列剖面图。图3A表示初始半导体衬底，包括N+底部半导体层105，一个轻掺杂N-半导体层110位于衬底105上方，以及一个重掺杂N-半导体层112位于轻掺杂区110上方。在图3B中，利用沟槽掩膜103，在顶部半导体层112中打开多个沟槽104。在图3C中，通过沟槽104，植入P-型掺杂离子，以便在沟槽104下方形成掩埋的场环区150。在这一过程中，利用植入掩膜（图中没有表示出）阻止某些沟槽植入，并通过额外的倾斜P-掺杂植入，构成空穴-供应通路P-掺杂区160，包围所选沟槽的沟槽侧壁，如图4A所示。在图3D和4B中，除去植入掩膜之后，用电介质（例如氧化物）145内衬沟槽。继续进行标准处理工艺，制成如图2A和2B所示的器件。
尽管本发明已经详细说明了现有的较佳实施例，但应理解这些说明不应作为本发明的局限。例如，虽然上述示例中的导电类型表示的是n-通道器件，但是通过转换导电类型的极性，本发明也可用于p-通道器件。本领域的技术人员阅读上述详细说明后，各种变化和修正无疑将显而易见。因此，应认为所附的权利要求书涵盖本发明的真实意图和范围内的全部变化和修正。

Claims (20)

1.一种形成在半导体衬底中的半导体功率器件，其特征在于，所述的半导体衬底具有一个在顶面附近的重掺杂上层，以及一个设置在重掺杂上层下方的轻掺杂下层；
一个源极区和一个栅极，设置在半导体衬底的顶面附近，以及一个漏极，设置在半导体衬底的底面处；
在重掺杂上层中打开的源极沟槽，垫有沟槽绝缘层，并用导电沟槽填充材料填充，导电沟槽填充材料与顶面上方的源极电极电接触，并且与源极区电接触；以及
一个掩埋场环区，设置在源极沟槽下方，并用导电类型与重掺杂上层相反的掺杂物掺杂。
2.如权利要求1所述的半导体功率器件，其特征在于，重掺杂上层和轻掺杂下层为N型掺杂层，掩埋场环区用P型掺杂物掺杂。
3.如权利要求1所述的半导体功率器件，其特征在于，半导体衬底还包括一个重掺杂的N底层，作为半导体衬底的漏极。
4.如权利要求2所述的半导体功率器件，其特征在于，重掺杂上层的掺杂浓度范围约为1e15cm-3至5e16cm-3，下方的轻掺杂下层的掺杂浓度范围约为1e14cm-3至5e15cm-3。
5.如权利要求3所述的半导体功率器件，其特征在于，重掺杂的N底层的掺杂浓度约为1e19cm-3至1e21cm-3。
6.如权利要求1所述的半导体功率器件，其特征在于，重掺杂上层和轻掺杂下层为N型掺杂层，分别掺杂砷掺杂物和磷掺杂物。
7.如权利要求1所述的半导体功率器件，其特征在于，源极沟槽垫有氧化层，并用多晶硅填充，多晶硅作为导电沟槽的填充材料。
8.如权利要求1所述的半导体功率器件，其特征在于，源极沟槽的深度约为6微米，垫有厚度约为5500埃的氧化层，并用多晶硅填充，多晶硅作为导电沟槽填充材料。
9.如权利要求1所述的半导体功率器件，其特征在于，源极沟槽下方的掩埋场环区为P-型掺杂区，掺杂浓度约为1e12cm-3至1e13cm-3。
10.如权利要求1所述的半导体功率器件，其特征在于，还包括：包围着源极沟槽侧壁的电荷供应通路区，用导电类型与掩埋场区相同的掺杂物掺杂。
11.一种用于在半导体衬底中制备半导体功率器件的方法，其特征在于，包括以下步骤：
掺杂半导体衬底，以构成轻掺杂下层以及重掺杂上层，其中重掺杂上层在轻掺杂下层上方的顶面附近；
在重掺杂上层内打开多个源极连接沟槽；
在源极连接沟槽下方植入掩埋场环区，掺杂物的导电类型与重掺杂上层的导电类型相反；
用沟槽绝缘层衬垫源极连接沟槽，并用导电沟槽填充材料填充源极连接沟槽；并且
制备一个本体区、一个源极区以及一个在半导体衬底顶面附近的栅极，并且制备一个源极电极金属层，连接到源极区以及源极连接沟槽中的导电沟槽填充材料。
12.如权利要求11所述的方法，其特征在于，制备重掺杂上层和轻掺杂下层的步骤，包括制备重掺杂上层和轻掺杂下层，作为N型掺杂层，并且植入掩埋场环区，作为P型掩埋场环区。
13.如权利要求11所述的方法，其特征在于，在半导体衬底上制备半导体功率器件，重掺杂的N底层作为半导体衬底的漏极。
14.如权利要求12所述的方法，其特征在于，制备重掺杂上层和轻掺杂下层作为N型掺杂层的步骤，还包括制备重掺杂上层，掺杂浓度范围约为1e15cm-3至5e16cm-3，下方的轻掺杂下层的掺杂浓度范围约为1e14cm-3至5e15cm-3。
15.如权利要求13所述的方法，其特征在于，在带有重掺杂N底层的半导体衬底上制备半导体功率器件，还包括在重掺杂N底层上制备半导体功率器件，重掺杂N底层的掺杂浓度范围约在1e19cm-3至1e21cm-3之间。
16.如权利要求11所述的方法，其特征在于，制备重掺杂上层和轻掺杂下层的步骤，还包括分别用砷掺杂物和磷掺杂物掺杂重掺杂上层和轻掺杂下层。
17.如权利要求11所述的方法，其特征在于，用沟槽绝缘层衬垫源极连接沟槽的步骤，还包括用氧化层衬垫源极连接沟槽，并用多晶硅填充源极连接沟槽，多晶硅作为导电沟槽填充材料。
18.如权利要求11所述的方法，其特征在于，打开源极连接沟槽的步骤，包括在重掺杂上层中深度约为6微米处打开源极连接沟槽，用厚度约为5500埃的氧化层衬垫源极连接沟槽。
19.如权利要求11所述的方法，其特征在于，在源极沟槽下方植入掩埋场环区的步骤，包括植入P-型掺杂物，构成掩埋场环区，掺杂浓度范围约在1e14cm-3至1e16cm-3之间。
20.如权利要求11所述的方法，其特征在于，在源极沟槽下方植入掩埋场环区的步骤，还包括进行斜角度植入，以便在源极沟槽侧壁周围构成电荷供应通路区，源极沟槽侧壁掺杂物的导电类型与掩埋场环区的导电类型相同。
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