CN102947917A - 通过加工引发的单轴向应变控制介电薄膜内的铁电性 - Google Patents
通过加工引发的单轴向应变控制介电薄膜内的铁电性 Download PDFInfo
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Abstract
本发明涉及通过加工引发的单轴向应变控制介电薄膜内的铁电性。一种控制集成电路设备部件铁电特性的方法，包括在衬底上成形铁电性可控的介电层；并且紧靠铁电性可控的介电层成形应力施加结构，从而通过应力施加结构在铁电性可控的介电层内引发基本单轴向的应变；其中铁电性可控的介电层包括以下中的一个或多个：铁电性氧化物层以及在没有施加应力时不会表现出铁电性质的通常无铁电性的材料层。
Description
技术领域
本发明主要涉及半导体器件，并且尤其涉及通过其中加工引发的应变控制介电薄膜内的铁电性。
背景技术
集成铁电性材料在微电子领域具有很多当前或未来潜在的用途，包括例如铁电性场效应晶体管(FET)存储器、铁电性金属-绝缘体-金属(MIM)电容存储器以及超低功率/电压的互补金属氧化物半导体(CMOS)逻辑电路等。
目前由于要求很多(例如远高于室温的铁电迁移温度(Tc)、高剩余极化强度、良好的保持性、低疲劳等)，因此只有很少几种很好的用于此类应用的备选铁电性材料。一种这样的值得生产的材料是锆钛酸铅(Pb[ZrxTi1-x]O3，0<x<1或者通过其化学式写为PZT)。PZT是一种具有钙钛矿型晶体结构的陶瓷材料，其表现出明显的铁电性，即在存在电场时产生自发电极化强度(电偶极子)。但是，在微电子应用中使用PZT的一个缺点是向生产线内引入了铅(Pb)，这会造成环境问题。而且，PZT会在极化切换和累积切换循环中表现出很可观的损耗。
另一种这样的铁电性材料是SrBi2Ta2O9或SBT。SBT的一种相关缺点(除了SBT的组成具有三种金属离子的复杂性以外)涉及加工控制问题，例如高加工温度。其他可能的铁电性备选材料对于某些应用来说具有过低的迁移温度Tc或者过低的自发或剩余极化强度Pr。例如，BaTiO3具有的Tc约为120℃，这对于室温下的应用来说过于接近室温。
因此，另一些方法关注的是通过引入双轴向应变来显著提高和/或调节铁电性材料的Tc或Pr。铁电性薄膜内的双轴向应变迄今为止已经通过铁电性材料在具有低晶格失配的衬底(例如氧化物)上的相干外延而实验性地实现。例如，BaTiO3薄膜内(通过钪酸盐衬底例如DyScO3或GdScO3上的相干外延实现)的双轴向应变能够得到比散装BaTiO3单晶体高出近500℃的铁电迁移温度Tc和高出至少250%的剩余极化强度Pr。在此情况下，应变是双轴向和压缩性的。另外，双轴向应变也可以通过外延在其他的铁电性材料例如PbTiO3或BiFeO3中实现。还有另一些方法关注的是通过引入双轴向应变而在通常的非铁电性材料中引发铁电性。例如，SrTiO3薄膜内(通过钪酸盐衬底例如DyScO3或GdScO3上的相干外延实现)的双轴向应变能够得到室温下的铁电性。
但是，铁电性材料通过外延的双轴向应变具有其自身的局限性。例如，硅上直接外延要求将分子束外延(MBE)沉积用于高质量外延。在此，应变无法调节，并且一旦达到临界厚度应变就会弛豫。因此，只能在有限的厚度范围内获得可调的铁电性质。而且，铁电性氧化物例如BaTiO3在Si上的直接外延会因为相对于硅导带为负或者非常小的带偏移而导致很高的漏电流。
发明内容
在一个示范性实施例中，一种控制集成电路设备部件铁电特性的方法包括在衬底上成形铁电性可控的介电层；并且紧靠铁电性可控的介电层成形应力施加结构，从而通过应力施加结构在铁电性可控的介电层内引发基本单轴向的应变，其中铁电性可控的介电层包括以下中的一个或多个：铁电性氧化物层以及在没有施加应力时不会表现出铁电性质的通常无铁电性的材料层。
在另一个实施例中，一种铁电性场效应晶体管(FET)器件包括设置在栅电极和衬底之间的铁电性可控栅极介电层；以及紧靠铁电性可控介电层成形的应力施加结构，从而通过应力施加结构在铁电性可控的介电层内引发基本单轴向的应变，其中铁电性可控的栅极介电层包括以下中的一个或多个：铁电性氧化物层以及在没有施加应力时不会表现出铁电性质的通常无铁电性的材料层。
在又一个实施例中，一种铁电性金属-绝缘体-金属(MIM)电容器包括成形在衬底上的下电极层；电容器介电层，包括成形在下电极上的铁电性可控介电层；成形在铁电性可控介电层上的上电极层；以及紧靠铁电性可控介电层成形的应力施加结构，从而在铁电性可控的介电层内引发基本单轴向的应变；其中铁电性可控的栅极介电层包括以下中的一个或多个：铁电性氧化物层以及在没有施加应力时不会表现出铁电性质的通常无铁电性的材料层。
附图说明
参照示范性附图，其中相同的元件在各附图中被标记为相同：
图1是根据本发明实施例具有栅极介电层的FET的截面图，栅极介电层通过应变工程设计而铁电性可控；
图2示出了成形的外延源极和漏极区域，在图1中FET的铁电性可控栅极介电层上提供了基本单轴向的应变；
图3示出了根据本发明实施例在具有栅极介电层的FET上成形的压缩性氮化物应力层，栅极介电层通过应变工程设计而铁电性可控；
图4示出了根据本发明的另一个实施例在具有栅极介电层的FET上成形的拉伸性氮化物应力层，栅极介电层通过应变工程设计而铁电性可控；以及
图5(a)到5(d)是示出了根据本发明的另一个实施例成形具有介电层的MIM电容器的一系列截面图，介电层通过应变工程设计而铁电性可控。
具体实施方式
本文中公开了用于通过加工引发的薄膜应变来控制介电薄膜内铁电性的方法和结构。某些示范性实施例被用于引发铁电性，其中在无应变时通常无铁电性的材料例如SrTiO3或CaMnO3在有应变时就变得有铁电性。另一些示范性实施例调节介电薄膜现有的铁电性，其中调节铁电性材料在其加工状态下的性质(Tc、Pr)，由此拓宽可用于微电子应用的可行材料(例如BaTiO3)的频谱以及提高现有铁电性器件(例如基于PZT的器件)的性能。
在本文介绍的实施例中，首先沉积在硅或其他类型半导体衬底(例如绝缘体上硅(SOI)、Ge、III/V等)上的铁电性可控材料例如通常无铁电性的材料或铁电性材料通过CMOS型技术基本单轴向地应变。如本文中所用的“基本单轴向”描述了沿表面的一个方向例如x方向或y方向引发的应变。这就与例如沿其表面在两个方向(x-y)上引发应变的双轴向应变薄膜形成了对比。但是应该理解，“基本单轴向”也可以描述主要是沿一条轴线(例如x轴)的应变，同时沿另外的轴线也有少量的、“微量的”或者非零的应变分量。另外，如本文中所述的“CMOS型”技术可以包括例如靠近硅沟道区域的源极/漏极锗化硅(SiGe)区域、氮化物内衬区域及其组合。
在任何情况下，都不需要外延介电薄膜，并且压缩性和拉伸性(单轴向)应变(利用氮化硅)均可实现，而且能够调节应变水平，由此显著地调节Tc和Pr。在铁电性氧化物内实施加工引发的应变由此可以通过芯片技术中常见的目前用于提高晶体管沟道迁移率的集成方案实现。通过加工引发的应变调节铁电性的介电薄膜的实用实施例包括但不限于FET和MIM电容器。
首先参照图1，示出了成形在衬底102例如硅或SOI内的FET100的截面图。成形在浅沟槽隔离(STI)区域104之间的晶体管包括图案化的栅电极106、邻接栅电极106的侧壁隔板108以及栅电极106和衬底102之间的栅极介电层110。在此，用于栅极介电层110的常规材料(例如二氧化硅)被包含铁电性可控层的介电叠层代替。同样地，铁电性可控层可以是例如铁电性材料层或者是在向其施加外部应力后才表现出铁电性质的通常无铁电性的材料层。栅极介电层110内包含的铁电性可控层的非限制性示例包括BaTiO3、PZT、SBT、SrTiO3(STO)、Ba1-xSrxTiO3(BST)、PbTiO3、CaMnO3和BiFeO3。
在散装SrTiO3的情况下，氧旋转是形成无极性的反铁畸变基态的原因。铁电畸变和反铁畸变两者可以在适当的应变下共存，并且这些不稳定状态之间耦合的改变能够使其通往新的基态(即铁电体)。因此，没有明显的根本理由说明为什么(导致单轴向应变或者可能导致更复杂应变分布的)单轴向应力不会导致这种强相关复合氧化物的基态改变。
尽管图1中所示的栅极介电层110被示出为有图案化的栅电极以使隔板108也靠接栅极介电层110的侧壁，但是应该意识到栅极介电层110也可以相对于栅电极110单独图案化以使(例如)隔板108位于栅极介电层110的顶部。除了铁电性可控层以外，介电层110还可以在铁电性可控层和衬底102之间包括一个或多个缓冲层。而且，图1中示出的介电层110还可以包括设置在铁电性可控层以及栅电极110和/或衬底102之间的一个或多个附加介电层。
正如图1中还可以注意到的那样，源极和漏极区域112已经例如通过蚀刻被去除以为不同半导体材料例如锗化硅(SiGe)或掺杂碳的硅(Si:C)的外延生长让路。图2中示出了外延材料114。因此，单轴向的压缩性或拉伸性应变不仅会在栅极介电层110下方晶体管的沟道区域内引发，而且也会在栅极介电层110自身内引发。例如，在外延材料114是SiGe之处，引发的单轴向应变是压缩性的。可选地，如果外延材料114是Si:C，那么引发的单轴向应变就是拉伸性的。因此，栅极介电层110上外延引发的应力就引发和/或调节了栅极介电层110的铁电性质。在更进一步设想的实施例中，源极和漏极区域112可以通过使用注入硅内的掺杂剂来设置嵌入式的应力施加半导体材料。
除了外延的源极/漏极应力施加半导体材料以外或作为其替代，其他的单轴向应力/应变技术也可以被用于引发/调节介电层的铁电性质。如图3所示，FET 100的衬底102被掺有合适的掺杂材料以形成源极和漏极区域116(以及栅极以下的源极/漏极扩展区域)。也就是说，在图3的实施例中，并未从源极/漏极半导体材料中生成应力。相反，氮化物内衬118(例如氮化硅)被成形在FET 100上。在图示的示例中，氮化物层118是压缩性氮化物层，原因在于它在衬底102的沟道区域和栅极介电层110两者上提供了单轴向的压缩应力。除了如上所述引发/调节栅极介电层110的铁电性质以外，压缩性氮化物层118还被用于提高PMOS FET器件内的载流子迁移率。
作为比较，图4示出了具有拉伸性氮化物内衬120的FET 100，该拉伸性氮化物内衬120在衬底102的沟道区域和栅极介电层110上生成单轴向的拉伸应力。除了如上所述引发/调节栅极介电层110的铁电性质以外，拉伸性氮化物层120还被用于提高NMOS FET器件内的载流子迁移率。
现主要参照图5(a)到5(d)，根据本发明的另一个实施例示出了成形具有铁电性可控介电层的MIM电容器的一系列截面图。在图5(a)中，衬底502具有依次成形在其上作为叠层的下电极层504、包括铁电性可控层的电容器介电层506和上电极层508。与FET实施例中的情况一样，铁电性可控层包括铁电性材料层或者是在向其施加外部应力后才表现出铁电性质的通常无铁电性的材料层。任意合适的导电材料均可被用于下电极层504和上电极层508，包括例如铂、铱、钌、钛、氮化钛、钽、氮化钽、氧化钇、氧化钌、铜、钨或其化合物。
类似于FET的实施例，MIM电容器中的电容器介电层506除了铁电性可控层以外还可以包括设置在铁电性可控层以及下电极层504和上电极层508之间的一个或多个缓冲层和/或一个或多个附加介电层。
在图5(b)中，下电极层504、铁电性可控层506和上电极层508被蚀刻为所需形状，然后如图5(c)所示在得到的电容器叠层上成形氮化物应力层510。氮化物应力层510可以如箭头所示被制成为有拉伸性或压缩性。结果即可因单轴向的应力/应变来引发/调节MIM电容器的铁电性质。最后，在图5(d)中，绝缘层(例如二氧化硅)512被成形在承受应力的铁电性MIM电容器上用于后续的器件加工。
尽管已经参照一个或多个优选实施例介绍了本发明，但是本领域技术人员应该理解可以进行各种修改并且可以用等价物替代其中的元素而并不背离本发明的保护范围。另外，可以根据本发明的教导做出很多修改以适合特定情况或材料而并不背离其实质的保护范围。因此，意图在于本发明并不局限于作为设计用于实现本发明的最佳模式而公开的特定实施例，而且本发明应该包括落入所附权利要求保护范围内的所有实施例。
Claims (25)
1.一种控制集成电路设备部件铁电特性的方法，所述方法包括：
在衬底上成形铁电性可控的介电层；并且
紧靠铁电性可控的介电层成形应力施加结构，从而通过应力施加结构在铁电性可控的介电层内引发基本单轴向的应变；
其中铁电性可控的介电层包括以下中的一个或多个：铁电性氧化物层以及在没有施加应力时不会表现出铁电性质的通常无铁电性的材料层。
2.如权利要求1所述的方法，其中所述铁电性可控的介电层包括以下的一种或多种材料：BaTiO3、Pb[ZrxTi1-x]O3(PZT)、SrBi2Ta2O9(SBT)、SrTiO3(STO)、Ba1-xSrxTiO3(BST)、PbTiO3、CaMnO3和BiFeO3。
3.如权利要求1所述的方法，其中所述应力施加结构包括相对于衬底不同的半导体材料。
4.如权利要求1所述的方法，其中所述应力施加结构包括成形在铁电性可控介电层上的氮化物层。
5.如权利要求4所述的方法，其中所述氮化物层是压缩性氮化物层。
6.如权利要求4所述的方法，其中所述氮化物层是拉伸性氮化物层。
7.如权利要求1所述的方法，其中所述铁电性可控介电层被包括在场效应晶体管(FET)的栅极介电层内。
8.如权利要求7所述的方法，其中所述衬底是硅衬底并且成形应力施加结构包括生长锗化硅的源极和漏极区域从而在铁电性可控介电层内引发压缩性单轴向应变。
9.如权利要求7所述的方法，其中所述衬底是硅衬底并且成形应力施加结构包括生长掺杂碳的硅源极和漏极区域从而在铁电性可控介电层内引发拉伸性单轴向应变。
10.如权利要求7所述的方法，其中成形应力施加结构包括在FET上成形压缩性氮化物层。
11.如权利要求7所述的方法，其中成形应力施加结构包括在FET上成形拉伸性氮化物层。
12.如权利要求7所述的方法，其中所述栅极介电层进一步包括一个或多个附加介电层。
13.如权利要求1所述的方法，其中所述铁电性可控介电层包括金属-绝缘体-金属(MIM)电容器的介电层。
14.一种铁电性场效应晶体管(FET)器件，包括：
设置在栅电极和衬底之间的铁电性可控栅极介电层；以及
紧靠铁电性可控介电层成形的应力施加结构，从而通过应力施加结构在铁电性可控介电层内引发基本单轴向的应变；
其中铁电性可控的栅极介电层包括以下中的一个或多个：铁电性氧化物层以及在没有施加应力时不会表现出铁电性质的通常无铁电性的材料层。
15.如权利要求14所述的器件，其中所述铁电性可控的栅极介电层包括以下的一种或多种材料：BaTiO3、Pb[ZrxTi1-x]O3(PZT)、SrBi2Ta2O9(SBT)、SrTiO3(STO)、Ba1-xSrxTiO3(BST)、PbTiO3、CaMnO3和BiFeO3。
16.如权利要求14所述的器件，其中所述衬底是硅衬底并且所述应力施加结构包括外延生长的锗化硅源极和漏极区域，其在铁电性可控介电层内引发压缩性单轴向应变。
17.如权利要求14所述的器件，其中所述衬底是硅衬底并且所述应力施加结构包括外延生长的掺杂碳的硅源极和漏极区域，其在铁电性可控介电层内引发拉伸性单轴向应变。
18.如权利要求14所述的器件，其中应力施加结构包括在FET上成形的压缩性氮化物层。
19.如权利要求14所述的器件，其中应力施加结构包括在FET上成形的拉伸性氮化物层。
20.如权利要求14所述的器件，其中所述栅极介电层进一步包括一个或多个附加介电层。
21.一种铁电性金属-绝缘体-金属(MIM)电容器，包括：
成形在衬底上的下电极层；
电容器介电层，包括成形在下电极上的铁电性可控介电层；
成形在铁电性可控介电层上的上电极层；以及
紧靠铁电性可控介电层成形的应力施加结构，从而在铁电性可控的介电层内引发基本单轴向的应变；
其中铁电性可控的栅极介电层包括以下中的一个或多个：铁电性氧化物层以及在没有施加应力时不会表现出铁电性质的通常无铁电性的材料层。
22.如权利要求21所述的器件，其中所述铁电性可控的栅极介电层包括以下的一种或多种材料：BaTiO3、Pb[ZrxTi1-x]O3(PZT)、SrBi2Ta2O9(SBT)、SrTiO3(STO)、Ba1-xSrxTiO3(BST)、PbTiO3、CaMnO3和BiFeO3。
23.如权利要求21所述的器件，其中所述应力施加结构包括在MIM电容器上成形的压缩性氮化物层。
24.如权利要求21所述的器件，其中所述应力施加结构包括在MIM电容器上成形的拉伸性氮化物层。
25.如权利要求21所述的器件，其中所述电容器介电层进一步包括一个或多个附加介电层。
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- 2011-03-15 CN CN201180016493.2A patent/CN102947917B/zh not_active Expired - Fee Related
- 2011-03-15 JP JP2013502613A patent/JP5902147B2/ja not_active Expired - Fee Related
- 2011-03-15 DE DE112011101181.4T patent/DE112011101181B4/de active Active
- 2011-03-15 GB GB1218702.7A patent/GB2492697B/en not_active Expired - Fee Related
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Also Published As
| Publication number | Publication date |
|---|---|
| DE112011101181T5 (de) | 2013-01-10 |
| WO2011123238A1 (en) | 2011-10-06 |
| CN102947917B (zh) | 2015-11-25 |
| GB2492697B (en) | 2014-03-19 |
| US20110241091A1 (en) | 2011-10-06 |
| GB2492697A (en) | 2013-01-09 |
| US20120286340A1 (en) | 2012-11-15 |
| US8890112B2 (en) | 2014-11-18 |
| US8389300B2 (en) | 2013-03-05 |
| JP2013524511A (ja) | 2013-06-17 |
| DE112011101181B4 (de) | 2020-10-08 |
| GB201218702D0 (en) | 2012-11-28 |
| JP5902147B2 (ja) | 2016-04-13 |
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