CN102844863A - 用作静电放电保护措施的晶体管组件 - Google Patents

用作静电放电保护措施的晶体管组件 Download PDF

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CN102844863A
CN102844863A CN2011800072254A CN201180007225A CN102844863A CN 102844863 A CN102844863 A CN 102844863A CN 2011800072254 A CN2011800072254 A CN 2011800072254A CN 201180007225 A CN201180007225 A CN 201180007225A CN 102844863 A CN102844863 A CN 102844863A
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弗雷德里克·罗格
沃尔夫冈·赖因普雷希特
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    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors

Abstract

本发明涉及一种布置在晶体管（25）附近的、用于进行保护防止ESD的二极管（23）。二极管包括第一传导类型的阱（5）和与第一传导类型相对的第二传导类型的掺杂区域（4）。晶体管包括第一传导类型的掺杂阱（2）和掺杂区域（1）。晶体管的阱（2）的掺杂低于二极管的阱（5）。

Description

用作静电放电保护措施的晶体管组件
本发明涉及一种具有受到保护防止静电放电的晶体管的装置。
在电子电路中，可能发生由于静电放电（ESD）引起的过压，这损坏了电路元件。因此电子电路常常配备有ESD保护装置。
US 5751042A描述了一种用于两个相互相邻的、具有用于源极和漏极的n+区域的n沟道元件的ESD保护电路。第一n沟道元件的漏极n+区域连接到供电电压的正端子，并且第二n沟道元件的源极n+区域连接到供电电压的负端子。第一n沟道元件的漏极n+区域被布置在距第二n沟道元件的源极n+区域的一定距离处，并且通过场氧化物区域隔离。增加pn结处的击穿电压的n型阱与第一n沟道元件的漏极n+区域基本上重叠，并且延伸到第二n沟道元件的源极n+区域。阱较之n+区域更深地延伸到衬底中并且具有比n+区域低的掺杂剂浓度。
作为另一可能方案，本公布指出了第一n沟道元件的漏极n+区域和第二n沟道元件的源极n+区域之间的p+型保护环的布置。这旨在减小在两个n沟道元件之间形成的寄生npn双极型晶体管的电流增益并且因此防止由静电放电触发的所谓的“快回（snap-back）”。
本发明的问题在于说明如何有效地保护晶体管元件防止由于发生静电放电引起的损坏。
该目的通过具有权利要求1的特征的晶体管组件来实现。配置来自各从属权利要求。
在该晶体管组件中，二极管被布置在晶体管附近用于进行保护防止ESD。晶体管包括第一传导类型（n型或p型）的掺杂阱以及至少一个布置在阱外部的、第一传导类型的掺杂区域。在下面的描述中以及在权利要求中，传导类型将被理解成仅意味着n型或p型，而不是指示掺杂水平（掺杂剂浓度）。二极管包括第一传导类型的掺杂阱以及至少一个布置在阱外部的、与第一传导类型相对的第二传导类型的掺杂区域，就是说，如果阱是n型的，则掺杂区域是p型的，或者如果阱是p型的，则掺杂区域是n型的。二极管的掺杂区域布置在二极管的阱和晶体管的掺杂区域之间。晶体管的阱和二极管的阱彼此电传导地连接。作为集电极的晶体管的阱、作为基极的二极管的掺杂区域以及作为发射极的晶体管的掺杂区域形成了寄生双极型晶体管，即并非由晶体管的结构有意形成的双极型晶体管。
晶体管的阱的掺杂比二极管的阱低。在晶体管的掺杂区域和二极管的阱之间存在小的距离，使得较之作为集电极的二极管的阱、作为基极的二极管的掺杂区域以及作为发射极的晶体管的掺杂区域形成的附加双极型晶体管，该寄生双极型晶体管由于阱的不同掺杂具有较小的电流增益。
如果在没有保护二极管的晶体管元件中发生静电放电，并且引起晶体管的阱和周围的半导体材料之间的不需要的电流流动，则可以在晶体管工作时施加电压的情况下使晶体管的寄生双极型晶体管生效，并且出现被称为快回的电流强度的急剧增加，这损坏了晶体管。然而，由于通过二极管形成的附加寄生双极型晶体管的较大的电流增益，在晶体管中出现的电流强度保持为受限制的，并且保护晶体管防止损坏。为了实现这一点，适当地调整晶体管的阱和二极管的阱中的掺杂剂浓度以及晶体管和二极管之间的距离。
在晶体管组件的一个实施例中，第一传导类型是n型并且第二传导类型是p型。
在另一实施例中，二极管的和晶体管的阱和掺杂区域被布置在由第二传导类型的半导体材料制成的衬底中。
在另一实施例中，具有连接导体和接触焊盘的电传导接触连接（contact connection，端子连接）被设置在衬底上方。这些连接导体中的一个被布置在晶体管的阱的接触区域上，并且这些连接导体中的另一个被布置在二极管的阱的接触区域上。
在另一实施例中，连接导体形成为指形且彼此平行布置，并且接触连接以该方式彼此以梳的方式衔接。
在另一实施例中，晶体管的阱被设置成漏极并且晶体管的掺杂区域被设置成源极。
在另一实施例中，晶体管在阱的背离掺杂区域的侧上具有与掺杂区域电传导地连接的、第一传导类型的附加掺杂区域。该附加掺杂区域同样布置在阱外部。
在另一实施例中，二极管在阱的背离掺杂区域的侧上具有与掺杂区域电传导地连接的、第二传导类型的附加掺杂区域。该附加掺杂区域同样布置在阱外部。
在另一实施例中，在晶体管的背离二极管的侧上存在作为保护二极管的附加二极管，并且晶体管和二极管的布置相对于穿过晶体管的阱的对称平面镜像对称。
在另一实施例中，二极管的阱的掺杂至少高达晶体管的阱的掺杂的两倍。
晶体管例如可以是高电压NMOS晶体管。
参照附图，晶体管组件的示例的更准确的描述如下。
图1示出了实施例的横截面。
图2示出了根据图1的实施例的俯视图。
图3示出了相关联的电路图。
图1示出了穿过晶体管组件的实施例的横截面。在半导体材料的衬底10的上侧面上形成掺杂阱和掺杂区域。晶体管25的第一掺杂区域1具有第一传导类型并且例如被设置成晶体管25的源极。掺杂阱2同样具有第一传导类型并且例如被设置成晶体管25的漏极。掺杂阱2可以配备有更高掺杂的接触区域20，通过其实现外部电端子的欧姆接触。此外，在图示实施例中设置了用于晶体管的源极的第一传导类型的附加掺杂区域3。掺杂区域1、3可以在衬底10的上侧面上彼此电传导地连接。在一个实施例中，衬底10内部的掺杂区域1、3形成了连续掺杂区域；在该实施例中，掺杂区域1、3的在图1中所示的截面还彼此分离。
用于源极和漏极的掺杂阱2和掺杂区域1、3被布置成彼此具有距离，使得在源极和漏极之间的衬底10的半导体材料中设有沟道区域，所述沟道区域可以在晶体管的操作期间通过布置在上方的栅极电极26进行控制。在栅极电极26和衬底10的半导体材料之间设置有薄的栅极电介质。在图1的横截面中，通过栅极电极26的尺寸表示，掺杂区域1、3和接触区域20可以相对于栅极电极26自对准地形成。
被设置成保护二极管的二极管23由第一传导类型的掺杂阱5和与第一传导类型相对的第二传导类型的掺杂区域4形成。掺杂区域4被布置在二极管23的阱5和晶体管25的掺杂区域1之间。此外，在图示实施例中为二极管23提供第二传导类型的附加掺杂区域6。掺杂区域4、6可以在衬底10的上侧面上和/或衬底10内部电传导地连接。特别地，第一传导类型可以是n型并且第二传导类型可以是p型。在该情况下，阱5形成二极管的阴极并且掺杂区域4、6形成二极管的阳极。掺杂阱5可以配备有较高掺杂的接触区域50，通过其实现用于外部电端子的欧姆接触。
在图1中示意性地绘出了第一接触连接7、第二接触连接8和第三接触连接9。这些接触连接7、8、9优选地通过印刷导体（printed conductors,印刷导线，带状导线）在衬底10的上侧面上形成。不同于此或者此外，也可以通过适当掺杂的区域在衬底10的半导体材料内部形成电传导连接。
在图示实施例中，第一接触连接7使二极管23的第二传导类型的两个掺杂区域4、6彼此连接。如果例如衬底10具有第二传导类型的弱掺杂，则这些连接可以同时被设置成衬底接触。第二接触连接8连接晶体管的被设置成源极的掺杂区域1、3。第三接触区域9将晶体管25的设置成漏极的阱2连接到二极管23中的第一传导类型的阱5。
阱2、5，掺杂区域1、3、4、6和衬底10的不同的传导类型使得在元件结构中形成寄生双极型晶体管。第一双极型晶体管由晶体管25的源极和漏极以及衬底10的和二极管23的相反掺杂的半导体材料形成。阱2是该第一寄生双极型晶体管的集电极并且掺杂区域1是其发射极；基极由衬底10的与源极和漏极相反掺杂的半导体材料形成，或者由二极管23中的第二传导类型的掺杂区域4、6形成。第二寄生双极型晶体管具有与第一寄生双极型晶体管相同的基极和相同的发射极，并且第二寄生双极型晶体管将二极管23中的第一传导类型的阱5当作其集电极。由于晶体管25的阱2的掺杂低于二极管23的阱5，因此第一寄生双极型晶体管具有比第二寄生双极型晶体管低的电流增益，使得在由于静电放电引发过压的情况下，电流主要流过二极管23，而流过晶体管25的电流仅具有低的电流强度。以该方式保护二极管25。
该晶体管组件可以是对称的，并且特别地，可以具有中心穿过晶体管25的阱2的对称平面S。在该情况下，可以在晶体管的阱2的背离二极管23的侧上，与二极管23对称地设置有附加二极管24，其用于进行保护防止接通晶体管25的寄生双极型晶体管。
图2示出了其中可以识别构成接触连接的连接导体的布置的俯视图。存在如下部件：电传导地连接晶体管25的第一掺杂区域1的第一连接导体11、用于晶体管25的阱2的在接触区域20上的第二连接导体12、用于晶体管25的附加掺杂区域3的第三连接导体13、用于二极管23的第一掺杂区域4的第四连接导体14、用于二极管23的阱5的在接触区域50上的第五连接导体15和用于二极管23的附加掺杂区域6的第六连接导体16、以及第一接触连接7的第一接触焊盘17、第二接触连接8的第二接触焊盘18和第三接触连接9的第三接触焊盘19。
第一接触连接7包括形成二极管23的电端子的第四连接导体14和第六连接导体16，以及特别地可被提供用于外部电端子的第一接触焊盘17。第二接触连接8包括在图示实施例中形成晶体管的电源极端子的第一连接导体11和第三连接导体13，以及特别地可被提供用于外部电端子的第二接触焊盘18。第三接触连接9包括在图示实施例中形成晶体管的电漏极端子的第二连接导体12、形成二极管的第二端子的第五连接导体15、以及特别地可被提供用于外部电端子的第三接触焊盘19。第二连接导体12和第五连接导体15借助于第三接触连接9形成晶体管25的漏极区域和同一传导类型的二极管端子之间的电传导连接。
图2中还绘出了第一寄生双极型晶体管21的和第二寄生双极型晶体管22的开关符号。如上文已解释的，寄生双极型晶体管21、22由衬底10的半导体材料中的掺杂阱2、5的和区域1、3、4、6的布置形成。寄生双极型晶体管21、22的集电极是晶体管的阱2和二极管的阱5，它们经由第三接触连接9和相关联的接触区域20、50电传导地彼此连接。寄生双极型晶体管21、22的公共发射极是晶体管25的掺杂区域1，并且公共基极是是衬底10的第二传导类型的半导体材料或二极管23的掺杂区域4的第二传导类型的半导体材料。
图3示出了晶体管组件的电路图。二极管23和晶体管25经由端子连接7、8、9彼此连接并且连接到接触焊盘17、18、19。二极管的电路图对应于其中第一传导类型是n型并且第二传导类型是p型的实施例。在电路中，在图1的横截面外部在例如衬底10中形成的附加二极管27可以设置在第一接触焊盘17和第二接触焊盘18之间。在图3的电路图中，第三接触连接9对应于寄生双极型晶体管21、22的集电极端子。寄生双极型晶体管21、22的共享的发射极端子由第二接触连接8形成。
晶体管25和二极管23优选地具有构成指形的端子，这些指形端子彼此平行地布置并且以梳的形式衔接。晶体管25和二极管23因此共同地形成具有不同的电流增益的多集电极双极型晶体管。在此，二极管的掺杂区域1、4、6和阱5可以按图1中所示的顺序接连地布置并且可以交替地具有第一传导类型和第二传导类型。在所描述的实施例中，二极管23中的第一传导类型的阱5布置在二极管23中的第二传导类型的掺杂区域4和二极管23中的第二传导类型的附加掺杂区域6之间。
二极管的阴极和晶体管的漏极端子例如可以连接到特别地可由第三接触焊盘19形成的IO端子。源极端子例如可以连接到特别地可由第二接触焊盘18形成的地端子。衬底和二极管的阳极例如可以连接到电源的作为衬底端子提供的端子。
当由于静电放电而出现过压时，两个寄生双极型晶体管接通，其中所述静电放电相对源极端子对漏极端子进行正偏压。由于晶体管的掺杂阱2，第一寄生双极型晶体管的电流增益低于由二极管形成的第二寄生双极型晶体管的电流增益。因此未达到触发晶体管内部的所谓的快回的电流强度。因此二极管保护晶体管防止由于ESD引起的破坏。因此，这还增加了晶体管组件对闩锁效应的抵抗能力。该晶体管组件的特别好的保护性质源自晶体管的和二极管的掺杂区域的密集布置与阱的不同掺杂剂浓度相结合。
在晶体管组件的适当配置中，二极管的阱的掺杂剂浓度可以高达晶体管的阱的掺杂剂浓度的两倍。然而，二极管的阱的掺杂剂浓度也可以更高。
在晶体管组件的一个配置中，晶体管是高电压NMOS晶体管。
附图标记列表
1晶体管的掺杂区域
2晶体管的阱
3晶体管的附加掺杂区域
4二极管的掺杂区域
5二极管的阱
6二极管的附加掺杂区域
7第一接触连接
8第二接触连接
9第三接触连接
10衬底
11连接导体
12连接导体
13连接导体
14连接导体
15连接导体
16连接导体
17第一接触焊盘
18第二接触焊盘
19第三接触焊盘
20接触区域
21第一双极型晶体管
22第二双极型晶体管
23二极管
24附加二极管
25晶体管
26栅极电极
27附加二极管
50接触区域
S对称平面

Claims (10)

1.一种晶体管组件，具有：
-晶体管（25），其具有第一传导类型的阱（20）以及布置在所述阱外部的第一传导类型的掺杂区域（1），以及
-二极管（23），其具有第一传导类型的附加阱（5）以及布置在所述附加阱外部的、与所述第一传导类型相对的第二传导类型的掺杂区域（4），
其中
-所述二极管的掺杂区域（4）布置在所述二极管的阱（5）和所述晶体管的掺杂区域（1）之间，并且所述晶体管的阱（2）和所述二极管的阱（5）彼此电传导地连接，以及其中
-在所述晶体管的掺杂区域（1）和所述二极管的阱（5）之间存在充分小的距离，并且所述晶体管的阱（2）具有比所述二极管的阱（5）充分低的掺杂，使得通过作为集电极的所述晶体管的阱（2）、作为基极的所述二极管的掺杂区域（4）和作为发射极的所述晶体管的掺杂区域（1）形成的双极型晶体管，与通过作为集电极的所述二极管的阱（5）、作为基极的所述二极管的掺杂区域（4）和作为发射极的所述晶体管的掺杂区域（1）形成的双极型晶体管相比，具有较低的电流增益。
2.根据权利要求1所述的晶体管组件，其中
第一传导类型是n型并且第二传导类型是p型。
3.根据权利要求1或2所述的晶体管组件，其中
阱（2、5）和掺杂区域（1、3、4、6）被布置在由第二传导类型的半导体材料制成的衬底（10）中。
4.根据权利要求3所述的晶体管组件，其中
具有连接导体（11、12、13、14、15、16）和接触焊盘（17、18、19）的电传导接触连接（7、8、9）被设置在所述衬底（10）上，并且这些连接导体中的一个（12）被布置在所述晶体管（25）的阱（2）的接触区域（20）上，并且这些连接导体中的另一个（15）被布置在所述二极管（23）的阱（5）的接触区域（50）上。
5.根据权利要求4所述的晶体管组件，其中
所述连接导体（11、12、13、14、15、16）被形成为指形并且彼此平行布置，并且接触连接（7、8、9）从而以梳的方式彼此衔接。
6.根据权利要求1至5中任一项所述的晶体管组件，其中
所述晶体管（25）的阱（2）被设置成漏极并且所述晶体管（25）的掺杂区域（1）被设置成源极。
7.根据权利要求1至6中任一项所述的晶体管组件，其中
所述晶体管（25）在阱（2）的背离掺杂区域（1）的侧上具有与掺杂区域（1）电传导地连接的、第一传导类型的附加掺杂区域（3）。
8.根据权利要求1至7中任一项所述的晶体管组件，其中
所述二极管（23）在阱（5）的背离掺杂区域（4）的侧上具有与掺杂区域（4）电传导地连接的、第二传导类型的附加掺杂区域（6）。
9.根据权利要求1至8中任一项所述的晶体管组件，其中
在所述晶体管（25）的背离所述二极管（23）的侧上存在另一二极管（24），并且所述晶体管（25）的和所述二极管（23、24）的布置相对于穿过所述晶体管（25）的阱（2）的对称平面（S）镜像对称。
10.根据权利要求1至9中任一项所述的晶体管组件，其中
所述二极管（23）的阱（5）的掺杂至少高达所述晶体管的阱（2）的掺杂的两倍。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI620302B (zh) * 2017-06-06 2018-04-01 旺宏電子股份有限公司 半導體結構及其操作方法
CN108933120A (zh) * 2017-05-23 2018-12-04 旺宏电子股份有限公司 半导体结构及其操作方法
WO2019128606A1 (zh) * 2017-12-28 2019-07-04 无锡华润上华科技有限公司 一种双向静电放电保护器件
CN111066153A (zh) * 2017-09-06 2020-04-24 苹果公司 鳍式场效晶体管技术中的半导体布局
US10833151B2 (en) 2017-06-07 2020-11-10 Macronix International Co., Ltd. Semiconductor structure and operation method thereof
CN112234056A (zh) * 2020-09-03 2021-01-15 深圳市汇德科技有限公司 一种半导体器件

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8952744B1 (en) * 2013-07-31 2015-02-10 Macronix International Co., Ltd. Semiconductor device and operating method for the same
TWI555163B (zh) * 2015-07-22 2016-10-21 新唐科技股份有限公司 半導體結構

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204020A (ja) * 1995-01-30 1996-08-09 Nec Ic Microcomput Syst Ltd 半導体装置
KR20000045486A (ko) * 1998-12-30 2000-07-15 김영환 정전기방전 보호소자가 구비된 반도체장치의 제조방법
US6169309B1 (en) * 1997-09-30 2001-01-02 Texas Instruments Incorporated High breakdown-voltage transistor with transient protection
US20060065931A1 (en) * 2004-09-27 2006-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. ESD protection for high voltage applications
CN1841744A (zh) * 2005-03-31 2006-10-04 株式会社理光 具有稳定静电放电保护能力的半导体器件
US20060255411A1 (en) * 2005-05-11 2006-11-16 Denso Corporation Semiconductor device having MOS transistor and protection diode and method for designing the same
CN101132021A (zh) * 2006-08-22 2008-02-27 东部高科股份有限公司 垂直bjt及其制造方法
US20090032837A1 (en) * 2007-07-31 2009-02-05 Tseng Tang-Kuei Asymmetric bidirectional silicon-controlled rectifier
US20090167662A1 (en) * 2007-09-25 2009-07-02 Kao Jungcheng Power mosfet integration

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0517391A1 (en) * 1991-06-05 1992-12-09 STMicroelectronics, Inc. ESD protection circuit
US5751042A (en) * 1996-02-15 1998-05-12 Winbond Electronics Corporation Internal ESD protection circuit for semiconductor devices
KR100214566B1 (ko) * 1997-04-22 1999-08-02 구본준 입력 보호회로
US20050275029A1 (en) * 2004-06-15 2005-12-15 Jeffrey Watt Fast turn-on and low-capacitance SCR ESD protection
US7336459B2 (en) * 2004-07-29 2008-02-26 United Microelectronics Corp. Electrostatic discharge protection device and circuit thereof
DE102005027368A1 (de) * 2005-06-14 2006-12-28 Atmel Germany Gmbh Halbleiterschutzstruktur für eine elektrostatische Entladung
US7659558B1 (en) * 2005-09-23 2010-02-09 Cypress Semiconductor Corporation Silicon controlled rectifier electrostatic discharge clamp for a high voltage laterally diffused MOS transistor

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204020A (ja) * 1995-01-30 1996-08-09 Nec Ic Microcomput Syst Ltd 半導体装置
US6169309B1 (en) * 1997-09-30 2001-01-02 Texas Instruments Incorporated High breakdown-voltage transistor with transient protection
KR20000045486A (ko) * 1998-12-30 2000-07-15 김영환 정전기방전 보호소자가 구비된 반도체장치의 제조방법
US20060065931A1 (en) * 2004-09-27 2006-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. ESD protection for high voltage applications
CN1841744A (zh) * 2005-03-31 2006-10-04 株式会社理光 具有稳定静电放电保护能力的半导体器件
US20060255411A1 (en) * 2005-05-11 2006-11-16 Denso Corporation Semiconductor device having MOS transistor and protection diode and method for designing the same
CN101132021A (zh) * 2006-08-22 2008-02-27 东部高科股份有限公司 垂直bjt及其制造方法
US20090032837A1 (en) * 2007-07-31 2009-02-05 Tseng Tang-Kuei Asymmetric bidirectional silicon-controlled rectifier
US20090167662A1 (en) * 2007-09-25 2009-07-02 Kao Jungcheng Power mosfet integration

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108933120A (zh) * 2017-05-23 2018-12-04 旺宏电子股份有限公司 半导体结构及其操作方法
CN108933120B (zh) * 2017-05-23 2020-06-30 旺宏电子股份有限公司 半导体结构及其操作方法
TWI620302B (zh) * 2017-06-06 2018-04-01 旺宏電子股份有限公司 半導體結構及其操作方法
US10833151B2 (en) 2017-06-07 2020-11-10 Macronix International Co., Ltd. Semiconductor structure and operation method thereof
CN111066153A (zh) * 2017-09-06 2020-04-24 苹果公司 鳍式场效晶体管技术中的半导体布局
CN111066153B (zh) * 2017-09-06 2023-12-19 苹果公司 鳍式场效晶体管技术中的半导体布局
WO2019128606A1 (zh) * 2017-12-28 2019-07-04 无锡华润上华科技有限公司 一种双向静电放电保护器件
CN109979931A (zh) * 2017-12-28 2019-07-05 无锡华润上华科技有限公司 一种双向静电放电保护器件
CN109979931B (zh) * 2017-12-28 2020-11-10 无锡华润上华科技有限公司 一种双向静电放电保护器件
CN112234056A (zh) * 2020-09-03 2021-01-15 深圳市汇德科技有限公司 一种半导体器件
CN112234056B (zh) * 2020-09-03 2024-04-09 深圳市汇德科技有限公司 一种半导体器件

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