WO2019128606A1 - 一种双向静电放电保护器件 - Google Patents

一种双向静电放电保护器件 Download PDF

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Publication number
WO2019128606A1
WO2019128606A1 PCT/CN2018/118073 CN2018118073W WO2019128606A1 WO 2019128606 A1 WO2019128606 A1 WO 2019128606A1 CN 2018118073 W CN2018118073 W CN 2018118073W WO 2019128606 A1 WO2019128606 A1 WO 2019128606A1
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doping region
electrostatic discharge
discharge protection
protection device
port
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PCT/CN2018/118073
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English (en)
French (fr)
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汪广羊
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无锡华润上华科技有限公司
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Priority to US16/766,635 priority Critical patent/US20210005598A1/en
Publication of WO2019128606A1 publication Critical patent/WO2019128606A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0257—Overvoltage protection
    • H05K1/0259—Electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements

Definitions

  • the present application relates to semiconductor design and fabrication processes, and in particular to a bidirectional electrostatic discharge protection device.
  • CMOS technology As the level of integrated circuit manufacturing technology enters the deep sub-micron era of integrated circuit line width, the feature size of CMOS technology continues to shrink, the transistor's ability to withstand high voltage and high current is continuously reduced, and deep sub-micron CMOS integrated circuits are more susceptible to electrostatic shock. The failure causes the reliability of the product to decrease.
  • Electrostatic Discharge is a common phenomenon in the process of manufacturing, manufacturing, assembling, testing and transporting integrated circuit devices or chips.
  • the large current generated in a short period of time during electrostatic discharge causes fatal damage to the integrated circuit, which is an important problem causing failure in the production of integrated circuits.
  • the electrostatic discharge phenomenon (HBM) that occurs on the human body usually occurs within a few hundred nanoseconds, and the maximum current peak may reach several amps. In other modes, the electrostatic discharge occurs for a shorter period of time and the current is larger.
  • HBM electrostatic discharge phenomenon
  • Such a large current flows through the integrated circuit in a short period of time, and the power consumption will be severely exceeded by the maximum value that it can withstand, causing serious physical damage to the integrated circuit and causing its eventual failure.
  • the present application provides a two-way electrostatic discharge protection device, the two-way electrostatic discharge protection device comprising:
  • a third doping region having a second conductivity type wherein the first doping region is a ring structure formed outside the second doping region and the third doping region;
  • a first diode a negative electrode connected to the first doping region, and a positive electrode and the second doping region being commonly connected to the first port;
  • the second diode has a negative electrode connected to the first doping region, and a positive electrode and the third doping region are commonly connected to the second port.
  • FIG. 1 is a schematic structural view of a conventional two-way electrostatic discharge protection device
  • FIG. 2 is a schematic structural diagram of a bidirectional electrostatic discharge protection device according to an embodiment of the present application
  • 3A is an equivalent circuit diagram of a bidirectional electrostatic discharge protection device with a high potential at a first port and a low potential at a second port according to an embodiment of the present application;
  • FIG. 3B is an equivalent circuit diagram of the bidirectional electrostatic discharge protection device when the first port is connected to a low potential and the second port is connected to a high potential according to an embodiment of the present application.
  • Spatial relationship terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc. This description may be used to describe the relationship of one element or feature shown in the figures to the other elements or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned “on” or “below” or “below” or “under” the element or feature is to be “on” the other element or feature. Thus, the exemplary terms “below” and “include” can include both the above and the The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein interpreted accordingly.
  • composition and/or “comprising”, when used in the specification, is used to determine the presence of the features, integers, steps, operations, components and/or components, but does not exclude one or more The presence or addition of features, integers, steps, operations, components, components, and/or groups.
  • the term “and/or” includes any and all combinations of the associated listed items.
  • Electrostatic Discharge is a common phenomenon in the process of manufacturing, manufacturing, assembling, testing and transporting integrated circuit devices or chips.
  • the large current generated in a short period of time during electrostatic discharge causes fatal damage to the integrated circuit, which is an important problem causing failure in the production of integrated circuits.
  • Ordinary ESD protection devices are mostly protected in a single direction.
  • the protection between the power line and the ground line in an integrated circuit requires only a single direction of electrostatic discharge protection between them to meet the protection requirements.
  • the design of the power supply voltage does not work at a fixed value, the voltage value will have positive or negative or high and low changes, then the ordinary electrostatic discharge protection device can not only meet the protection requirements of such integrated circuits. It may also affect the normal operation of the integrated circuit. Therefore, devices capable of two-way electrostatic discharge protection are required to meet this design requirement.
  • the present application provides a bidirectional electrostatic discharge protection device including a first doped region, a second doped region, a third doped region, and a first diode and a second diode, the first doped region has a first conductivity type, and the second doped region and the third doped region each have a second conductivity type, wherein the first doped region a ring structure formed on an outer side of the second doping region and the third doping region, a cathode of the first diode is connected to the first doping region, and the first diode is The positive electrode and the second doped region are commonly connected to the first port, the negative electrode of the second diode is connected to the first doped region, the positive electrode of the second diode and the third doped region Connect the second port together.
  • the first doped region, the second doped region, and the third doped region together form a bipolar transistor or two or more bipolar transistors connected in parallel with each other.
  • the second doped region and the third doped region are alternately arranged inside the first doped region.
  • the second doped region and the third doped region are both elongated.
  • the first doped region is heavily doped.
  • the second doped region and the third doped region are heavily doped.
  • the first diode When the first port is connected to a high potential and the second port is connected to a low potential, the first diode is turned on, and the second diode is turned off; when the first port is connected to a low potential, When the second port is connected to a high potential, the first diode is turned off, and the second diode is turned on, thereby controlling the bipolar transistor to achieve bidirectional electrostatic discharge protection to discharge static electricity.
  • the first port is an I/O terminal
  • the second port is a ground terminal.
  • the bipolar transistor formed by the first doping region, the second doping region, and the third doping region is formed differently from the first diode and the second diode respectively In the well area.
  • the first conductivity type is an N-type doping region, and the second conductivity type is a P-type.
  • the two-way electrostatic discharge protection device provided by the present application can save layout area, low trigger voltage, good protection effect, and flexible structure, and can realize protection under different voltages.
  • a bidirectional electrostatic discharge protection device includes a first doping region 201, a second doping region 202, a third doping region 203, and a first diode 204. Second diode 205.
  • the first doped region 201 is an annular structure formed on the outer side of the second doped region 202 and the third doped region 203, and the negative electrode of the first diode 204 is connected to the first a doped region 201, the anode of the first diode 204 and the second doping region 202 are commonly connected to the first port, and the cathode of the second diode 205 is connected to the first doping region 201 The anode of the second diode 205 and the third doping region 203 are commonly connected to the second port.
  • the first doping region 201, the second doping region 202, and the third doping region 203 are heavily doped regions.
  • the bipolar transistor formed by the first doping region 201, the second doping region 202, and the third doping region 203 is formed differently from the first diode 204 and the second diode 205, respectively. In the well region to avoid interference with each other.
  • the first doping region 201, the second doping region 202, and the third doping region 203 together form a bipolar transistor or two or more bipolar transistors connected in parallel with each other.
  • the first conductivity type is an N type
  • the second conductivity type is a P type
  • the first doping region 201, the second doping region 202, and the third doping region 203 form a PNP type transistor.
  • the first conductivity type is P type
  • the second conductivity type is N type
  • the first doping region 201, the second doping region 202, and the third doping region 203 forms an NPN type transistor.
  • the main doping element of the P-type doping is one or more of trivalent dopants, such as boron
  • the main doping element of the N-type doping is one or more of pentavalent dopants.
  • pentavalent dopants for example, phosphorus or arsenic.
  • the second doping region 202 and the third doping region 203 are alternately arranged inside the first doping region 201. In other embodiments, the second doping region 202 and the third doping region 203 are both elongated and alternately arranged inside the first doping region 201.
  • the first diode 204 When the first port is connected to the high potential and the second port is connected to the low potential, the first diode 204 is turned on, and the second diode 205 is turned off. When the first port is connected to the low potential and the second port is connected to the high potential, the second port is connected to the high potential. A diode 204 is turned off, and the second diode 205 is turned on, thereby controlling the implementation of the bipolar transistor formed by the first doping region 201, the second doping region 202, and the third doping region 203 Two-way electrostatic discharge protection to discharge static electricity.
  • the first diode 204 is forwardly turned on, and the second diode 205 is reversely turned off.
  • the equivalent circuit of the electrostatic discharge protection device is as shown in FIG. 3A.
  • the bipolar transistor formed by the first doping region 201, the second doping region 202, and the third doping region 203 the second doping region 202 constitutes an emitter, and the third doping region 203 constitutes The collector, the first doped region 201 constitutes a base, and the bipolar transistor is reverse biased to provide a discharge path for the forward electrostatic discharge current.
  • the equivalent circuit of the electrostatic discharge protection device is as shown in FIG. 3B. Shown.
  • the bipolar transistor formed by the first doping region 201, the second doping region 202, and the third doping region 203 the second doping region 202 constitutes a collector, and the third doping region 203 constitutes The emitter, the first doped region 201 constitutes a base, and the bipolar transistor is reverse biased to provide a reverse discharge path for electrostatic discharge current.
  • the bipolar transistor formed by the doping region 203 is reverse biased, thereby ensuring the bidirectional electrostatic discharge protection capability of the bidirectional electrostatic discharge protection device at different potentials.
  • the voltage value changes positively or negatively
  • only the same or the same set of bipolar transistors have electrostatic discharge protection capability, thereby implementing the bidirectional electrostatic discharge protection of the bidirectional electrostatic discharge protection device provided by the present application.
  • the structure is flexible, effectively reducing the device area occupied by the two-way electrostatic discharge protection device. At the same time, the on-resistance introduced is also reduced, and the two-way electrostatic discharge protection capability is further optimized.
  • the bidirectional ESD protection device is disposed between the input and output (I/O) terminals of the protected device and the ground (GND).
  • the I/O end is a first port
  • the GND end is a second port.
  • the bidirectional ESD protection device is disposed between the input and output (I/O) terminals of the protected device and the ground (GND).
  • the I/O end is a second port, and the GND end is a first port.
  • the two-way electrostatic discharge protection device provided by the present application can save layout area, low trigger voltage, good protection effect, and flexible structure, and can realize protection under different voltages.

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Abstract

本申请提供一种双向静电放电保护器件，双向静电放电保护器件包括第一掺杂区（201）、第二掺杂区（202）、第三掺杂区（203）、以及第一二极管（204）和第二二极管（205），第一掺杂区（201）具有第一导电类型，第二掺杂区（202）和第三掺杂区（203）均具有第二导电类型，其中，第一掺杂区（201）为形成于第二掺杂区（202）和第三掺杂区（203）外侧的环状结构，第一二极管（204）的负极连接第一掺杂区（201），第一二极管（204）的正极与第二掺杂区（202）共同连接第一端口，第二二极管（205）的负极连接第一掺杂区（201），第二二极管（205）的正极与第三掺杂区（203）共同连接第二端口。

Description

一种双向静电放电保护器件 技术领域
本申请涉及半导体设计与制造工艺，具体而言涉及一种双向静电放电保护器件。
背景技术
随着集成电路制造工艺水平进入集成电路线宽的深亚微米时代，CMOS工艺特征尺寸不断缩小，晶体管对于高电压和大电流的承受能力不断降低，深亚微米CMOS集成电路更容易遭受到静电冲击而失效，从而造成产品的可靠性下降。
静电放电(Electrostatic Discharge，ESD)是集成电路器件或芯片在制造、生产、组装、测试及运送等过程中产生的一种常见现象。静电放电时会在短时间内产生的大电流，对集成电路产生致命的损伤，是集成电路生产应用中造成失效的重要问题。例如，对于发生在人体上的静电放电现象(HBM)，通常发生在几百个纳秒内，最大的电流峰值可能达到几个安培，其它模式静电放电发生的时间更短，电流也更大。如此大的电流在短时间内通过集成电路，产生的功耗会严重超过其所能承受的最大值，从而对集成电路产生严重的物理损伤并导致其最终失效。
为了解决该问题，在实际应用中主要从环境和电路本身两方面来解决。环境方面，主要是减少静电的产生和及时消除静电，例如，应用不易产生静电的材料、增加环境湿度、操作人员和设备接地等。电路方面，主要是增加集成电路本身的静电放电耐受能力，例如增加额外的静电放电保护器件或者 电路来保护集成电路内部电路不被静电放电损害，这就增加了器件面积，不利于电路集成度的提高。此外，目前的静电放电保护器件存在不容易控制的问题，容易发生闩锁效应(latchup)，容易导致电路不稳定。还存在引入导通电阻大，保护内部电路效果不理想等问题。
因此，目前的静电放电保护器件的结构亟待改进。
发明内容
本申请为了克服目前存在的至少一个问题，提供了一种双向静电放电保护器件，所述双向静电放电保护器件包括：
第一掺杂区，具有第一导电类型；
第二掺杂区，具有第二导电类型；
第三掺杂区，具有第二导电类型，其中，所述第一掺杂区为形成于所述第二掺杂区和所述第三掺杂区外侧的环状结构；
第一二极管，负极连接所述第一掺杂区，正极与所述第二掺杂区共同连接第一端口；及
第二二极管，负极连接所述第一掺杂区，正极与所述第三掺杂区共同连接第二端口。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为传统的双向静电放电保护器件的结构示意图；
图2为根据本申请一实施例的双向静电放电保护器件的结构示意图；
图3A为根据本申请一实施例的双向静电放电保护器件在第一端口接高电位，第二端口接低电位时的等效电路图；
图3B为根据本申请一实施例的双向静电放电保护器件在第一端口接低电位，第二端口接高电位时的等效电路图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本申请的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的 一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
静电放电(Electrostatic Discharge，ESD)是集成电路器件或芯片在制造、生产、组装、测试及运送等过程中产生的一种常见现象。静电放电时会在短时间内产生的大电流，对集成电路产生致命的损伤，是集成电路生产应用中造成失效的重要问题。
普通的静电放电保护器件多为单一方向的保护。例如，在集成电路中电源线与地线之间的保护，只需要在它们之间加一个单一方向的静电放电保护器件就可以满足保护要求。但是，在某些集成电路中，设计其电源电压不工作在某一固定的值，电压值会有正负或高低的改变，那么普通的静电放电保护器件不仅不能满足这类集成电路的保护要求，有可能还会影响集成电路正常的工作。因此就需要能够有双向静电放电保护能力的器件来满足这一设计要求。
传统的双向静电放电保护方案有两种：第一种是采取双向可控硅(Silicon Controlled Rectifier，SCR)，其缺点是不容易控制，容易发生闩锁效应(latchup)，对电路的稳定性产生不利影响；第二种如图1所示，是将ESD器件101和 ESD器件102背靠背串联，但是串联引入的导通电阻大，对保护内部电路不理想，且占用较大的器件面积。
为了解决上述至少一个问题，本申请提出一种双向静电放电保护器件，所述双向静电放电保护器件包括第一掺杂区、第二掺杂区、第三掺杂区以及第一二极管和第二二极管，所述第一掺杂区具有第一导电类型，所述第二掺杂区和所述第三掺杂区均具有第二导电类型，其中，所述第一掺杂区为形成于所述第二掺杂区和所述第三掺杂区外侧的环状结构，所述第一二极管的负极连接所述第一掺杂区，所述第一二极管的正极与所述第二掺杂区共同连接第一端口，所述第二二极管的负极连接所述第一掺杂区，所述第二二极管的正极与所述第三掺杂区共同连接第二端口。
所述第一掺杂区、所述第二掺杂区和所述第三掺杂区共同构成一个双极型晶体管或两个以上相互并联的双极型晶体管。
所述第二掺杂区和所述第三掺杂区在所述第一掺杂区内部交替排列。
所述第二掺杂区和所述第三掺杂区均为长条状。
所述第一掺杂区为重掺杂。
所述第二掺杂区和所述第三掺杂区为重掺杂。
当所述第一端口接高电位，所述第二端口接低电位时，所述第一二极管导通，所述第二二极管截止；当所述第一端口接低电位，所述第二端口接高电位时，所述第一二极管截止，所述第二二极管导通，从而控制所述双极型晶体管实现双向静电放电保护以释放静电。
所述第一端口为I/O端，所述第二端口为接地端。
所述第一掺杂区、所述第二掺杂区和所述第三掺杂区所构成的双极型晶体管与所述第一二极管、所述第二二极管分别形成于不同的阱区中。
所述第一导电类型为N型掺杂区，所述第二导电类型为P型。
本申请提供的双向静电放电保护器件，能节省版图面积，触发电压低，保护效果好，并且结构灵活，可以实现不同电压下的保护。
下面参考图2、图3A、3B对本申请一实施例的双向静电放电保护器件的结构进行详细说明。
如图2所示，本申请一实施例所提供的双向静电放电保护器件，包括第一掺杂区201、第二掺杂区202、第三掺杂区203、以及第一二极管204和第二二极管205。其中，所述第一掺杂区201为形成于所述第二掺杂区202和所述第三掺杂区203外侧的环状结构，所述第一二极管204的负极连接所述第一掺杂区201，所述第一二极管204的正极与所述第二掺杂区202共同连接第一端口，所述第二二极管205的负极连接所述第一掺杂区201，所述第二二极管205的正极与所述第三掺杂区203共同连接第二端口。
作为示例，所述第一掺杂区201、所述第二掺杂区202和所述第三掺杂区203为重掺杂区域。所述第一掺杂区201、第二掺杂区202和第三掺杂区203所构成的双极型晶体管与所述第一二极管204、第二二极管205分别形成于不同的阱区中，以避免互相之间产生干扰。
在本实施例中，所述第一掺杂区201、所述第二掺杂区202和所述第三掺杂区203共同构成一个双极型晶体管或两个以上相互并联的双极型晶体管。所述第一导电类型为N型，所述第二导电类型为P型，所述第一掺杂区201、第二掺杂区202和所述第三掺杂区203形成PNP型晶体管。在其他实施例中，所述第一导电类型为P型，所述第二导电类型为N型，则所述第一掺杂区201、第二掺杂区202和所述第三掺杂区203形成NPN型晶体管。其中，P型掺杂的主要掺杂元素为三价掺杂剂中的一种或多种，例如硼，N型掺杂的主要掺杂元素为五价掺杂剂中的一种或多种，例如磷或砷。作为示例，所述第二掺杂区202和所述第三掺杂区203在所述第一掺杂区201内部交替排列。在其他实施例中，第二掺杂区202和第三掺杂区203均为长条状且在所述第一掺杂区201内部交替排列。
当第一端口接高电位，第二端口接低电位时，第一二极管204导通，第二二极管205截止，当第一端口接低电位，第二端口接高电位时，第一二极管204截止，第二二极管205导通，从而控制第一掺杂区201、所述第二掺 杂区202和所述第三掺杂区203所构成的双极型晶体管实现双向静电放电保护以释放静电。
具体地，当ESD事件发生时，较大的电压尖峰施加到第一端口和第二端口之间。当第一端口接高电位，第二端口接低电位时，第一二极管204正向导通，第二二极管205反向截止，该静电放电保护器件的等效电路如图3A所示。此时在由第一掺杂区201、第二掺杂区202和第三掺杂区203所形成的双极型晶体管中，第二掺杂区202构成发射极，第三掺杂区203构成集电极，第一掺杂区201构成基极，该双极型晶体管反偏，从而提供正向的静电放电电流的泄放路径。当第一端口接低电位，第二端口接高电位时，第一二极管204反向截止，第二二极管205正向导通，此时该静电放电保护器件的等效电路如图3B所示。此时在由第一掺杂区201、第二掺杂区202和第三掺杂区203所形成的双极型晶体管中，第二掺杂区202构成集电极，第三掺杂区203构成发射极，第一掺杂区201构成基极，该双极型晶体管反偏，从而提供反向的静电放电电流的泄放路径。即无论第一端口接高电位，第二端口接低电位还是第一端口接低电位，第二端口接高电位，都能够保证由第一掺杂区201、第二掺杂区202和第三掺杂区203所形成的双极型晶体管反偏，从而保证了该双向静电放电保护器件在不同电位下的双向静电放电保护能力。电压值发生正负或高低的变化时，仅借助同一个或同一组双极型晶体管，均具有静电放电保护能力，进而实现本申请提供的双向静电放电保护器件的双向静电放电保护。结构灵活，有效降低双向静电放电保护器件占用的器件面积。同时还减小了引入的导通电阻，进一步优化双向静电放电保护能力。
在其他实施例中，双向静电放电保护器件设置在受保护设备的输入输出(I/O)端与接地端(GND)之间。其中，所述I/O端为第一端口，所述GND端为第二端口。
在其他实施例中，双向静电放电保护器件设置在受保护设备的输入输出(I/O)端与接地端(GND)之间。其中，所述I/O端为第二端口，所述GND端为第一端口。
本申请提供的双向静电放电保护器件，能节省版图面积，触发电压低，保护效果好，并且结构灵活，可以实现不同电压下的保护。
本申请已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本申请限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本申请并不局限于上述实施例，根据本申请的教导还可以做出更多种的变型和修改，这些变型和修改均落在本申请所要求保护的范围以内。本申请的保护范围由附属的权利要求书及其等效范围所界定。

Claims (13)

  1. 一种双向静电放电保护器件，包括：
    第一掺杂区，具有第一导电类型；
    第二掺杂区，具有第二导电类型；
    第三掺杂区，具有第二导电类型，其中，所述第一掺杂区为形成于所述第二掺杂区和所述第三掺杂区外侧的环状结构；
    第一二极管，负极连接所述第一掺杂区，正极与所述第二掺杂区共同连接第一端口；及
    第二二极管，负极连接所述第一掺杂区，正极与所述第三掺杂区共同连接第二端口。
  2. 根据权利要求1所述的双向静电放电保护器件，其中，所述第一掺杂区、所述第二掺杂区和所述第三掺杂区共同构成一个双极型晶体管。
  3. 根据权利要求1所述的双向静电放电保护器件，其中，所述第一掺杂区、所述第二掺杂区和所述第三掺杂区共同构成两个以上相互并联的双极型晶体管。
  4. 根据权利要求1至3任一项所述的双向静电放电保护器件，其中，所述第二掺杂区和所述第三掺杂区在所述第一掺杂区内部交替排列。
  5. 根据权利要求4所述的双向静电放电保护器件，其中，所述第二掺杂区和所述第三掺杂区均为长条状。
  6. 根据权利要求1至3任一项所述的双向静电放电保护器件，其中，所述第一掺杂区为重掺杂。
  7. 根据权利要求1至3所述的双向静电放电保护器件，其中，所述第二掺杂区和所述第三掺杂区为重掺杂。
  8. 根据权利要求2或3所述的双向静电放电保护器件，其中，当所述第一端口接高电位，所述第二端口接低电位时，所述第一二极管导通，所述第二二极管截止；当所述第一端口接低电位，所述第二端口接高电位时，所述 第一二极管截止，所述第二二极管导通，从而控制所述双极型晶体管实现双向静电放电保护以释放静电。
  9. 根据权利要求1至3任一项所述的双向静电放电保护器件，其中，所述第一端口为I/O端，所述第二端口为接地端。
  10. 根据权利要求1至3任一项所述的双向静电放电保护器件，其中，所述第一端口为接地端，所述第二端口为I/O端。
  11. 根据权利要求1至3任一项所述的双向静电放电保护器件，其中，所述第一掺杂区、所述第二掺杂区和所述第三掺杂区所构成的双极型晶体管与所述第一二极管、所述第二二极管分别形成于不同的阱区中。
  12. 根据权利要求1所述的双向静电放电保护器件，其中，所述第一导电类型为N型，所述第二导电类型为P型。
  13. 根据权利要求1所述的双向静电放电保护器件，其中，所述第一导电类型为P型，所述第二导电类型为N型。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020043687A1 (en) * 2000-10-18 2002-04-18 Nobuaki Tsuji Semiconductor input protection circuit
CN101819972A (zh) * 2009-02-09 2010-09-01 万国半导体有限公司 一种用于功率器件击穿保护的栅漏箝位和静电放电保护电路
US20120211842A1 (en) * 2009-08-28 2012-08-23 Austriamicrosystems Ag Semiconductor Body Having a Terminal Cell
CN102844863A (zh) * 2010-01-26 2012-12-26 ams有限公司 用作静电放电保护措施的晶体管组件

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100223833B1 (ko) * 1996-04-03 1999-10-15 구본준 이에스디 보호회로의 구조 및 제조방법
CN1228843C (zh) * 2002-04-05 2005-11-23 华邦电子股份有限公司 双向过电压与静电放电防护装置
US6979869B2 (en) * 2003-10-01 2005-12-27 Lsi Logic Corporation Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process
US8247839B2 (en) * 2008-07-09 2012-08-21 Sofics Bvba ESD protection device with increased holding voltage during normal operation
US8653557B2 (en) * 2010-02-22 2014-02-18 Sofics Bvba High holding voltage electrostatic discharge (ESD) device
US9397085B2 (en) * 2013-12-29 2016-07-19 Texas Instruments Incorporated Bi-directional ESD protection device
CN104022111B (zh) * 2014-06-17 2017-01-11 东南大学 一种具有双向防护能力的静电放电保护结构
CN106206569B (zh) * 2016-08-12 2019-05-10 电子科技大学 一种基于埋层触发的低触发电压双向scr器件
KR102361141B1 (ko) * 2019-05-23 2022-02-09 주식회사 키파운드리 정전기 방전 보호용 반도체 소자

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020043687A1 (en) * 2000-10-18 2002-04-18 Nobuaki Tsuji Semiconductor input protection circuit
CN101819972A (zh) * 2009-02-09 2010-09-01 万国半导体有限公司 一种用于功率器件击穿保护的栅漏箝位和静电放电保护电路
US20120211842A1 (en) * 2009-08-28 2012-08-23 Austriamicrosystems Ag Semiconductor Body Having a Terminal Cell
CN102844863A (zh) * 2010-01-26 2012-12-26 ams有限公司 用作静电放电保护措施的晶体管组件

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