WO2021213024A1 - 静电保护电路 - Google Patents

静电保护电路 Download PDF

Info

Publication number
WO2021213024A1
WO2021213024A1 PCT/CN2021/079589 CN2021079589W WO2021213024A1 WO 2021213024 A1 WO2021213024 A1 WO 2021213024A1 CN 2021079589 W CN2021079589 W CN 2021079589W WO 2021213024 A1 WO2021213024 A1 WO 2021213024A1
Authority
WO
WIPO (PCT)
Prior art keywords
well
doped region
heavily doped
type heavily
circuit
Prior art date
Application number
PCT/CN2021/079589
Other languages
English (en)
French (fr)
Inventor
许杞安
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21792800.1A priority Critical patent/EP3975249B1/en
Priority to US17/386,480 priority patent/US11699697B2/en
Publication of WO2021213024A1 publication Critical patent/WO2021213024A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to an electrostatic protection circuit.
  • semiconductor manufacturing processes are getting more and more advanced, the channel length is getting shorter and shorter, the junction depth is getting shallower, the application of silicide, the application of light doping, the oxide layer is getting thinner and thinner, ESD (electrostatic The window designed for discharge (electrostatic discharge) is getting smaller and smaller, and the challenge for ESD protection design is getting bigger and bigger.
  • the breakdown voltage of the oxide layer of the MOS (Metal Oxide Semiconductor) device in the input buffer is greater than that of the MOS device used for electrostatic protection
  • the junction (junction) breakdown voltage is greater than that of the MOS device used for electrostatic protection
  • the breakdown voltage of the oxide layer has become smaller than the junction breakdown voltage, and the original ESD design window no longer exists.
  • the purpose of the embodiments of the present disclosure is to provide an electrostatic protection circuit, thereby improving the electrostatic protection capability of the charging device model of the chip at least to a certain extent.
  • an electrostatic protection circuit connected to an internal circuit, the electrostatic protection circuit including: a first circuit, a first diode connected in parallel with the first circuit, and a second Circuit and a second diode connected in parallel with the second circuit; wherein, the first circuit is connected between the power supply pad and the input terminal of the internal circuit, and the second circuit is connected between the input terminal of the internal circuit and the input terminal of the internal circuit. Between grounding pads; the first circuit and the second circuit are diode-assisted trigger thyristor circuits.
  • the first circuit includes a first PNP transistor and a first NPN transistor, the emitter of the first PNP transistor is connected to the power supply pad, and the base of the first PNP transistor is connected to the power supply pad. After the collector of the first NPN transistor is connected to the input terminal of the internal circuit through at least one third diode connected in series, the collector of the first PNP transistor is connected to the base of the first NPN transistor.
  • the first resistor is connected to the input terminal of the internal circuit, the emitter of the first NPN transistor is connected to the input terminal of the internal circuit; the cathode of the first diode is connected to the power supply pad;
  • the second circuit includes a second PNP transistor and a second NPN transistor, the emitter of the second PNP transistor is connected to the input terminal of the internal circuit, and the base of the second PNP transistor is connected to the set of the second NPN transistor. After the electrodes are connected, they are connected to the grounding pad through at least one fourth diode connected in series.
  • the collector of the second PNP transistor is connected to the base of the second NPN transistor and then connected to the ground through a second resistor. Pad connection; the anode of the second diode is connected to the ground pad.
  • the electrostatic protection circuit further includes a fifth diode connected between the power supply pad and the input pad, and a fifth diode connected between the input pad and the ground pad.
  • a fifth diode connected between the power supply pad and the input pad, and a fifth diode connected between the input pad and the ground pad.
  • the electrostatic protection circuit further includes an input resistance connected between the input pad and the input terminal of the internal circuit.
  • the ground pad and the power pad are both located on the die, the substrate of the die is provided with a first well, a second well, and a third well, and the substrate is a P-type substrate.
  • the first well, the second well, and the third well are all N-wells;
  • the first well includes a first P-type heavily doped region and a first N-type heavily doped region, and the power supply pad is connected to The first P-type heavily doped region is electrically connected;
  • the second well includes a second P-type heavily doped region and a second N-type heavily doped region, the second P-type heavily doped region and the The first N-type heavily doped region is electrically connected;
  • the third well includes a third P-type heavily doped region and a third N-type heavily doped region, and the third P-type heavily doped region is connected to the second The N-type heavily doped region is electrically connected;
  • the internal circuit input terminal is electrically connected to the third N-type heavily doped region.
  • the first P-type heavily doped region, the first well, and the substrate form a first PNP transistor; the first well, the substrate, and the third well form The first NPN transistor.
  • a first resistance is formed between the first well and the third well.
  • a first diode is formed between the third well and the first well.
  • a fourth well, a fifth well, and a sixth well are provided in the substrate, and the fourth well, the fifth well, and the sixth well are all N-wells;
  • the four-well includes a fourth P-type heavily doped region and a fourth N-type heavily doped region.
  • the internal circuit input terminal is electrically connected to the fourth P-type heavily doped region;
  • the fifth well includes a fifth P-type heavily doped region.
  • Type heavily doped region and a fifth N-type heavily doped region the fifth P-type heavily doped region and the fourth N-type heavily doped region are electrically connected;
  • the sixth well includes a sixth P-type heavily doped region A doped region and a sixth N-type heavily doped region, the sixth P-type heavily doped region is electrically connected to the sixth N-type heavily doped region;
  • the ground pad is connected to the sixth N-type heavily doped region The doped regions are electrically connected.
  • the fourth P-type heavily doped region, the fourth well, and the substrate form a second PNP transistor; the fourth well, the substrate, and the sixth well form The second NPN transistor.
  • a second resistance is formed between the fourth well and the sixth well.
  • a second diode is formed between the sixth well and the fourth well.
  • a diode is provided between the internal circuit and the power supply pad and the ground pad to assist in triggering the thyristor circuit and the diode, thereby realizing electrostatic protection of the charging device model.
  • No MOS device is used, which prevents the MOS device of the electrostatic protection circuit from breaking down before the MOS device of the electrostatic protection circuit when the MOS device of the electrostatic protection circuit undergoes electrostatic discharge, thereby improving the electrostatic protection capability of the chip.
  • Fig. 1 schematically shows a structural diagram of an electrostatic protection circuit in an embodiment of the present disclosure
  • Fig. 2 schematically shows a cross-sectional view of a first circuit in an embodiment of the present disclosure
  • Fig. 3 schematically shows a top view of a first circuit in an embodiment of the present disclosure
  • Fig. 4 schematically shows a cross-sectional view of a second circuit in an embodiment of the present disclosure
  • Fig. 5 schematically shows a top view of a second circuit in an embodiment of the present disclosure.
  • the breakdown voltage vt1 of the MOS device used for CDM electrostatic protection is greater than the breakdown voltage of the oxide layer of the MOS device of the input buffer.
  • the oxide layer of the MOS device of the input buffer will break down before the MOS device used for CDM electrostatic protection.
  • the original ESD design window no longer exists, so that it cannot provide good CDM electrostatic protection. .
  • the embodiments of the present disclosure provide an electrostatic protection circuit to realize electrostatic protection of the charging device model.
  • an embodiment of the present disclosure provides an electrostatic protection circuit, the electrostatic protection circuit is connected to an internal circuit, the electrostatic protection circuit includes: a first circuit 301, a first diode D1 connected in parallel with the first circuit 301 , The second circuit 302 and the second diode D2 connected in parallel with the second circuit 302; wherein the first circuit is connected between the power supply pad and the input terminal of the internal circuit, and the second circuit is connected between the input terminal of the internal circuit and the ground welding Between the disks; the first circuit 301 and the second circuit 302 can be a diode-assisted trigger thyristor circuit.
  • DTSCR diode assisted trigger thyristor
  • diode diode assisted trigger thyristor
  • the breakdown voltage of the layer is less than the breakdown voltage of the junction when the CDM electrostatic protection is a problem, so that the original ESD design window can be restored.
  • the input buffer includes a first MOS device Mp2 and a second MOS device Mn2.
  • the source and drain of the first MOS device Mp2 and the second MOS device Mn2 are connected in series to the power supply pad VDD and ground. Between the pads VSS, the gate of the first MOS device Mp2 and the gate of the second MOS device Mn2 are connected to the input pad Input after the internal circuit input terminal Inside is connected.
  • the first MOS device Mp2 may be PMOS
  • the second MOS device Mn2 may be NMOS.
  • the second circuit 302 for CDM protection when the circuit works normally, the normal operation of the input circuit is not affected.
  • ESD occurs, the on-voltage of the second circuit 302 for CDM protection is higher than the breakdown voltage of the Mn2 oxide layer of the second MOS device of the input buffer. Low, the second circuit 302 for CDM protection conducts and discharges the electrostatic current first, thereby realizing the electrostatic protection of the CDM.
  • the second diode D2 can provide an electrostatic discharge path in the other direction.
  • the on-voltage of the first circuit 301 for CDM protection is lower than the oxide breakdown voltage of the first MOS device Mp2 of the input buffer.
  • the first circuit 301 for CDM protection first conducts and discharges the electrostatic current, thereby realizing the electrostatic protection of the CDM.
  • the first diode D1 can provide an electrostatic discharge path in the other direction.
  • the first circuit 301 includes a first PNP transistor Q1 and a first NPN transistor Q2.
  • the emitter of the first PNP transistor Q1 is connected to the power supply pad, and the base of the first PNP transistor Q1 is connected to the collector of the first NPN transistor Q2.
  • the collector of the first PNP transistor Q1 is connected to the base of the first NPN transistor Q2 and then connected to the input terminal Inside of the internal circuit through the first resistor R1 Connected, the emitter of the first NPN transistor Q2 is connected to the input terminal Inside of the internal circuit; the cathode of the first diode D1 is connected to the power supply pad VDD.
  • the second circuit 302 includes a second PNP transistor Q3 and a second NPN transistor Q4.
  • the emitter of the second PNP transistor Q3 is connected to the input terminal Inside of the internal circuit, and the base of the second PNP transistor Q3 is connected to the collector of the second NPN transistor Q4. After connection, it is connected to the ground pad VSS through at least two fourth diodes D4 connected in series.
  • the collector of the second PNP transistor Q3 is connected to the base of the second NPN transistor Q4 and then is connected to the ground pad VSS through the second resistor R2. Connected; the anode of the second diode D2 is connected to the ground pad VSS.
  • the thyristor is equivalent to a combination of two transistors, PNP and NPN.
  • the electrostatic pulse introduced by the input terminal Inside of the internal circuit can make the two transistors of the thyristor saturated and conduct in a very short time.
  • the electrostatic pulse of the internal circuit generates a voltage drop on the second resistor R2 to turn on the NPN transistor Q4 and further turn on the PNP transistor Q3 to trigger the thyristor to turn on. After the transistor is triggered to turn on , The electrostatic pulse can be discharged from the second NPN transistor Q4 and the second PNP transistor Q3.
  • the number of at least two third diodes D3 and at least two fourth diodes D4 is based on the input voltage of the input pad Input and the breakdown voltage of the oxide layers of the first MOS device Mp2 and the second MOS device Mn2 choose.
  • the turn-on voltage of the first circuit 301 and the second circuit 302 needs to be less than the breakdown voltage of the oxide layer of the input buffer.
  • the turn-on voltage of the circuit 302 is such that the turn-on voltage is greater than the normal operating voltage of the input pad Input and is less than the oxide breakdown voltage of the second MOS device Mn2.
  • the conduction voltage of the second circuit 302 is greater than the normal operating voltage of the input pad Input, and is less than the oxide breakdown voltage of the second MOS device Mn2; the conduction voltage of the first circuit 301 is greater than the power supply voltage VDD and the input welding voltage The voltage difference of the normal working voltage of the disk Input is smaller than the breakdown voltage of the oxide layer of the first MOS device Mp2.
  • the first circuit 301 or the second circuit 302 connected to the internal circuit input terminal Inside, the power supply pad, and the ground pad are in an off state, which can ensure that the input circuit works normally during normal operation.
  • the first circuit 301 and the second circuit 302 provided by the embodiments of the present disclosure can ensure the normal operation of the input circuit during normal operation, and provide a bidirectional discharge path for CDM static electricity protection, which plays a role of CDM static electricity protection.
  • the electrostatic protection circuit further includes an input resistor Rin connected between the input pad Input and the input terminal Inside of the internal circuit.
  • the input pad Input is connected to the input terminal Inside of the internal circuit through the input resistance Rin.
  • the electrostatic protection circuit also includes a fifth diode Dp connected between the power supply pad VDD and the input pad Input, and a sixth diode Dn connected between the input pad Input and the ground pad VSS;
  • the anode of the fifth diode Dp is connected to the input pad Input, and the anode of the sixth diode Dn is connected to the ground pad VSS.
  • the fifth diode Dp and the sixth diode Dn can provide an electrostatic discharge path for the electrostatic discharge of the human body model.
  • both the ground pad and the power pad are located on the die.
  • the substrate 401 of the die is provided with a first well 410, a second well 420, and a third well 430, and the substrate 401 is P Type substrate, the first well 410, the second well 420, and the third well 430 are all N-wells; the first well 410 includes a first P-type heavily doped region 411 and a first N-type heavily doped region 412.
  • the disk VDD is electrically connected to the first P-type heavily doped region 411;
  • the second well 420 includes a second P-type heavily doped region 421 and a second N-type heavily doped region 422, the second P-type heavily doped region 421 and The first N-type heavily doped region 412 is electrically connected;
  • the third well 430 includes a third P-type heavily doped region 431 and a third N-type heavily doped region 432, the third P-type heavily doped region 431 and the second N
  • the type heavily doped region 422 is electrically connected;
  • the internal circuit input terminal Inside is electrically connected to the third N type heavily doped region 432.
  • the first P-type heavily doped region 411, the first well 410, and the substrate 401 form a first PNP transistor; the first well 410, the substrate 401, and the seventh N-type heavily doped region 433 form a first NPN transistor.
  • a first resistor R1 is formed between the first well 410 to the seventh P-type heavily doped region 434.
  • a third diode D3 is formed between the second P-type heavily doped region 421 and the second N-type heavily doped region 422; in the third well 430, the third P A third diode D3 is formed between the type heavily doped region 431 and the third N type heavily doped region 432.
  • a plurality of N-wells may also be arranged between the second well 420 and the third well 430. These N-wells have the same structure as the second well 420 and the third well 430, and a third diode D3 is formed in each N-well. , Which is equivalent to connecting multiple third diodes D3 in series between the base of the first PNP transistor Q1 and the input terminal Inside of the internal circuit.
  • ND-mode negative electrostatic discharge mode
  • the first PNP transistor Q1 and the first NPN transistor Q2 are turned on at the same time, and the electrostatic pulse of the positive electrode of the power supply is discharged to the input terminal Inside of the internal circuit via the turned on first PNP transistor Q1 and the first NPN transistor Q2.
  • a first diode D1 is formed between the third well 430 and the first well 410.
  • PD-mode positive electrostatic discharge mode
  • the first PNP transistor Q1 and the first NPN transistor Q2 are not conductive, and the electrostatic pulse of the internal circuit passes through the first and second The pole tube D1 is released to the positive pole of the power supply.
  • a fourth well 440, a fifth well 450, and a sixth well 460 are provided in the substrate, and the fourth well 440, the fifth well 450 and the sixth well 460 are all N-wells;
  • the well 440 includes a fourth P-type heavily doped region 441 and a fourth N-type heavily doped region 442.
  • the internal circuit input terminal Inside is electrically connected to the fourth P-type heavily doped region 441; the fifth well 450 includes a fifth P-type heavily doped region.
  • the heavily doped region 451 and the fifth N-type heavily doped region 452, the fifth P-type heavily doped region 451 and the fourth N-type heavily doped region 452 are electrically connected;
  • the sixth well 460 includes a sixth P-type heavily doped region The region 461 and the sixth N-type heavily doped region 462, the sixth P-type heavily doped region 461 and the sixth N-type heavily doped region 462 are electrically connected;
  • the ground pad VSS is electrically connected to the sixth N-type heavily doped region 462 connect.
  • the fourth P-type heavily doped region 441, the fourth well 440, and the substrate 401 form a second PNP transistor; the fourth well 440, the substrate 401, and the eighth N-type heavily doped region 463 form a second NPN transistor.
  • a second resistor R2 is formed between the fourth well 440 and the eighth P-type heavily doped region 464.
  • a fourth diode D4 is formed between the fifth P-type heavily doped region 451 and the fifth N-type heavily doped region 452; in the sixth well 460, the sixth P A fourth diode D4 is formed between the type heavily doped region 461 and the sixth N type heavily doped region 462.
  • a plurality of N-wells may also be arranged between the fifth well 450 and the sixth well 460. These N-wells have the same structure as the fifth well 450 and the sixth well 460, and a fourth diode D3 is formed in each N-well. , Which is equivalent to connecting multiple fourth diodes D4 in series between the base of the sixth PNP transistor Q3 and the ground pad VSS.
  • the negative electrostatic discharge mode (NS-mode) from the internal circuit input terminal Inside to the ground pad VSS.
  • the second PNP transistor Q3 and the second NPN transistor Q4 are turned on at the same time, and the internal The electrostatic pulse of the circuit is discharged to the power ground via the turned-on second PNP transistor Q3 and the second NPN transistor Q4.
  • a second diode is formed between the sixth well and the fourth well.
  • PS-mode positive discharge mode
  • the second PNP transistor Q3 and the second NPN transistor Q4 are not conductive, and the electrostatic pulse introduced by the power ground passes through the second diode D2 is released to the input terminal Inside of the internal circuit.
  • the internal circuit can discharge static electricity through the electrostatic protection circuit.
  • the internal circuit may be in four modes during electrostatic discharge, including: negative charge from the internal circuit input terminal Inside to the power supply pad VDD, the discharge path is the first PNP transistor Q1 and the first NPN transistor Q2; from the internal circuit input terminal From Inside to the power supply pad VDD, the discharge path is the first diode D1; from the internal circuit input terminal Inside to the ground pad VSS, the discharge path is the second PNP transistor Q3 and the second NPN transistor Q4. ; From the input terminal Inside of the internal circuit to the grounding pad VSS, the discharge path is the second diode D2.
  • the technical solutions of the embodiments of the present disclosure can realize electrostatic protection for these four modes under the charging device model.
  • the circuit design of the embodiments of the present disclosure can be applied to the ESD protection of the input and output circuits of the semiconductor integrated circuit, and especially can be applied to the CDM electrostatic protection of the input circuit of the advanced manufacturing process where the oxide layer of the semiconductor integrated circuit is relatively thin.
  • the circuit design method can also be applied to ESD protection of various semiconductor integrated circuits such as logic, analog and CDM of various memory chips.
  • a diode is provided between the internal circuit, the power supply pad, and the ground pad to assist in triggering the thyristor circuit and the diode to achieve electrostatic protection of the charging device model.
  • the MOS device prevents the MOS device of the electrostatic protection circuit from breaking down before the MOS device of the electrostatic protection circuit when the MOS device of the electrostatic protection circuit undergoes CDM electrostatic discharge, thereby improving the electrostatic protection capability of the chip.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本公开实施例提供了一种静电保护电路，与内部电路连接，所述静电保护电路包括：第一电路、与所述第一电路并联的第一二极管、第二电路以及与所述第二电路并联的第二二极管；其中，所述第一电路连接在电源焊盘和内部电路输入端之间，所述第二电路连接在所述内部电路输入端和接地焊盘之间；所述第一电路和所述第二电路为二极管辅助触发晶闸管电路。本公开的技术方案可以提高芯片的充电器件模型的静电保护能力。 (图1)

Description

静电保护电路
相关申请的交叉引用
本公开要求于2020年04月20日提交的申请号为202010313422.X、名称为“静电保护电路”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种静电保护电路。
背景技术
当前，半导体的制程越来越先进，沟道长度越来越短，结深(junction depth)越来越浅，硅化物的应用，轻掺杂的应用，氧化层越来越薄，ESD(electrostatic discharge，静电放电)设计的window(窗口)越来越小，ESD保护设计面临的挑战越来越大。
常规的CDM(Charged Device Model，充电器件模型)静电保护电路中，输入缓冲器中的MOS(Metal Oxide Semiconductor，金属氧化物半导体)器件的氧化层的击穿电压大于用于进行静电保护的MOS器件的结(junction)击穿电压。然而伴随着先进制程的开发，氧化层的击穿电压已经变得小于结击穿电压，原来的ESD设计window已不存在。
如何提高先进制程集成电路产品的CDM静电保护是当前亟需解决的技术问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开实施例的目的在于提供一种静电保护电路，进而至少在一定程度上提高芯片的充电器件模型的静电保护能力。
本公开的其它特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
根据本公开实施例的第一方面，提供了一种静电保护电路，与内部电路连接，所述静电保护电路包括：第一电路、与所述第一电路并联的第一二极管、第二电路以及与所述第二电路并联的第二二极管；其中，所述第一电路连接在电源焊盘和内部电路输入端之间，所述第二电路连接在所述内部电路输入端和接地焊盘之间；所述第一电 路和所述第二电路为二极管辅助触发晶闸管电路。
在一些实施例中，所述第一电路包括第一PNP晶体管和第一NPN晶体管，所述第一PNP晶体管的发射极与所述电源焊盘连接，所述第一PNP晶体管的基极与所述第一NPN晶体管的集电极连接后通过串联的至少一个第三二极管与所述内部电路输入端连接，所述第一PNP晶体管的集电极与所述第一NPN晶体管的基极连接后通过第一电阻与所述内部电路输入端连接，所述第一NPN晶体管的发射极与所述内部电路输入端连接；所述第一二极管的负极与所述电源焊盘连接；所述第二电路包括第二PNP晶体管和第二NPN晶体管，所述第二PNP晶体管的发射极与所述内部电路输入端连接，所述第二PNP晶体管的基极与所述第二NPN晶体管的集电极连接后通过串联的至少一个第四二极管与所述接地焊盘连接，所述第二PNP晶体管的集电极与所述第二NPN晶体管的基极连接后通过第二电阻与所述接地焊盘连接；所述第二二极管的正极与所述接地焊盘连接。
在一些实施例中，所述静电保护电路还包括连接于所述电源焊盘和输入焊盘之间的第五二极管和连接于所述输入焊盘和所述接地焊盘之间的第六二极管；其中，所述第五二极管的正极与所述输入焊盘连接，所述第六二极管的正极与所述接地焊盘连接。
在一些实施例中，所述静电保护电路还包括连接于所述输入焊盘和所述内部电路输入端之间的输入电阻。
在一些实施例中，所述接地焊盘和电源焊盘均位于裸片上，所述裸片的衬底中设置有第一阱、第二阱和第三阱，所述衬底为P型衬底，所述第一阱、第二阱和第三阱均为N阱；所述第一阱包含第一P型重掺杂区和第一N型重掺杂区，所述电源焊盘与所述第一P型重掺杂区电连接；所述第二阱包含第二P型重掺杂区和第二N型重掺杂区，所述第二P型重掺杂区和所述第一N型重掺杂区电连接；所述第三阱包含第三P型重掺杂区和第三N型重掺杂区，所述第三P型重掺杂区与所述第二N型重掺杂区电连接；所述内部电路输入端与所述第三N型重掺杂区电连接。
在一些实施例中，所述第一P型重掺杂区、所述第一阱、所述衬底形成第一PNP晶体管；所述第一阱、所述衬底、所述第三阱形成第一NPN晶体管。
在一些实施例中，所述第一阱至所述第三阱之间形成第一电阻。
在一些实施例中，所述第三阱与所述第一阱之间形成第一二极管。
在一些实施例中，所述衬底中设置有第四阱、第五阱和第六阱，所述第四阱、所述第五阱和所述第六阱均为N阱；所述第四阱包含第四P型重掺杂区和第四N型重 掺杂区，所述内部电路输入端与所述第四P型重掺杂区电连接；所述第五阱包含第五P型重掺杂区和第五N型重掺杂区，所述第五P型重掺杂区和所述第四N型重掺杂区电连接；所述第六阱包含第六P型重掺杂区和第六N型重掺杂区，所述第六P型重掺杂区与所述第六N型重掺杂区电连接；所述接地焊盘与所述第六N型重掺杂区电连接。
在一些实施例中，所述第四P型重掺杂区、所述第四阱、所述衬底形成第二PNP晶体管；所述第四阱、所述衬底、所述第六阱形成第二NPN晶体管。
在一些实施例中，所述第四阱至所述第六阱之间形成第二电阻。
在一些实施例中，所述第六阱与所述第四阱之间形成第二二极管。
本公开实施例提供的技术方案可以包括以下有益效果：
在本公开的一些实施例所提供的技术方案中，通过在内部电路和电源焊盘、接地焊盘之间设置二极管辅助触发晶闸管电路和二极管，实现了对充电器件模型的静电保护，由于静电保护不采用MOS器件，避免了静电保护电路的MOS器件在发生静电放电时，输入缓冲器的MOS器件的氧化层先于静电保护电路的MOS器件击穿，从而提高了芯片的静电保护能力。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。在附图中：
图1示意性示出了本公开实施例中的静电保护电路的结构图；
图2示意性示出了本公开实施例中的第一电路的截面图；
图3示意性示出了本公开实施例中的第一电路的俯视图；
图4示意性示出了本公开实施例中的第二电路的截面图；
图5示意性示出了本公开实施例中的第二电路的俯视图。
具体实施方式
现在将参考附图更全面地描述示例性实施方式。然而，示例性实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例性实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的模块翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其它相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
相关技术中，用于CDM静电保护的MOS器件的击穿电压vt1大于输入缓冲器的MOS器件的氧化层的击穿电压。当ESD发生时，输入缓冲器的MOS器件的氧化层会先于用于CDM静电保护的MOS器件先击穿，原本的ESD设计window已不存在，从而起不到很好的CDM的静电保护作用。
为解决上述问题，本公开实施例提供一种静电保护电路，以实现充电器件模型的静电保护。
如图1所示，本公开实施例提供一种静电保护电路，该静电保护电路与内部电路连接，该静电保护电路包括：第一电路301、与第一电路301并联的第一二极管D1、第二电路302以及与第二电路302并联的第二二极管D2；其中，第一电路连接在电源焊盘和内部电路输入端之间，第二电路连接在内部电路输入端和接地焊盘之间；第一电路301和第二电路302可以为二极管辅助触发晶闸管电路。
在本公开实施例的技术方案中，在内部电路输入端和VSS及VDD之间即输入缓冲器和VSS及VDD之间分别采用DTSCR(二极管辅助触发晶闸管)和二极管，可以避免先进制程当MOS氧化层的击穿电压小于结的击穿电压时的CDM静电保护的问题，这样，可以恢复原来的ESD设计window。
在本公开实施例中，输入缓冲器包括第一MOS器件Mp2和第二MOS器件Mn2， 第一MOS器件Mp2和第二MOS器件Mn2的源级和漏极串联后连接在电源焊盘VDD和接地焊盘VSS之间，第一MOS器件Mp2的栅极和第二MOS器件Mn2的栅极在内部电路输入端Inside连接后与输入焊盘Input连接。第一MOS器件Mp2可以为PMOS，第二MOS器件Mn2可以为NMOS。
具体地，电路正常工作时，输入电路正常工作不受影响，当有ESD发生时，由于CDM保护用的第二电路302的导通电压比输入缓冲器的第二MOS器件Mn2氧化层击穿电压低，CDM保护用的第二电路302先导通泄放静电电流，从而实现了CDM的静电保护。第二二极管D2能够提供另一个方向的静电泄放通路。
同理，在由第一电路301和第一二极管D1的静电保护时，由于CDM保护用的第一电路301的导通电压比输入缓冲器的第一MOS器件Mp2氧化层击穿电压低，CDM保护用的第一电路301先导通泄放静电电流，从而实现了CDM的静电保护。第一二极管D1能够提供另一个方向的静电泄放通路。
第一电路301包括第一PNP晶体管Q1和第一NPN晶体管Q2，第一PNP晶体管Q1的发射极与电源焊盘连接，第一PNP晶体管Q1的基极与第一NPN晶体管Q2的集电极连接后通过串联的至少两个第三二极管D3与内部电路输入端Inside连接，第一PNP晶体管Q1的集电极与第一NPN晶体管Q2的基极连接后通过第一电阻R1与内部电路输入端Inside连接，第一NPN晶体管Q2的发射极与内部电路输入端Inside连接；第一二极管D1的负极与电源焊盘VDD连接。
第二电路302包括第二PNP晶体管Q3和第二NPN晶体管Q4，第二PNP晶体管Q3的发射极与内部电路输入端Inside连接，第二PNP晶体管Q3的基极与第二NPN晶体管Q4的集电极连接后通过串联的至少两个第四二极管D4与接地焊盘VSS连接，第二PNP晶体管Q3的集电极与第二NPN晶体管Q4的基极连接后通过第二电阻R2与接地焊盘VSS连接；第二二极管D2的正极与接地焊盘VSS连接。
晶闸管相当于PNP和NPN两个晶体管的组合，内部电路输入端Inside引入的静电脉冲可以在极短时间内使晶闸管的两个晶体管均饱和导通。以第二电路302为例，内部电路的静电脉冲在第二电阻R2上产生压降从而使NPN晶体管Q4导通并进一步使PNP晶体管Q3导通来触发晶闸管导通，在晶体管实现触发导通后，静电脉冲可以自第二NPN晶体管Q4和第二PNP晶体管Q3释放。
这里，至少两个第三二极管D3和至少两个第四二极管D4的数量根据输入焊盘Input的输入电压和第一MOS器件Mp2和第二MOS器件Mn2的氧化层的击穿电压选 择。
在本公开实施例中，第一电路301和第二电路302的导通电压需要小于输入缓冲器的氧化层的击穿电压，通过调整串联二极管的个数，可以控制第一电路301和第二电路302的导通电压，使得该导通电压大于输入焊盘Input的正常工作电压，并且小于第二MOS器件Mn2的氧化层击穿电压。
具体地，第二电路302的导通电压大于输入焊盘Input的正常工作电压，并且小于第二MOS器件Mn2的氧化层击穿电压；第一电路301的导通电压大于电源电压VDD与输入焊盘Input的正常工作电压的电压差值，并且小于第一MOS器件Mp2的氧化层击穿电压。
这样，正常工作时，与内部电路输入端Inside、电源焊盘和接地焊盘连接的第一电路301或第二电路302处于关断状态，就可以保证正常工作时，输入电路正常工作。
综上，本公开实施例提供的第一电路301和第二电路302可以在正常工作时保证输入电路正常工作，并提供CDM静电保护的双向泄放通路，起到了CDM的静电保护作用。
在本公开实施例中，静电保护电路还包括连接于输入焊盘Input和内部电路输入端Inside之间的输入电阻Rin。输入焊盘Input通过输入电阻Rin与内部电路输入端Inside连接。
静电保护电路还包括连接于电源焊盘VDD和输入焊盘Input之间的第五二极管Dp和连接于输入焊盘Input和接地焊盘VSS之间的第六二极管Dn；其中，第五二极管Dp的正极与输入焊盘Input连接，第六二极管Dn的正极与接地焊盘VSS连接。
第五二极管Dp和第六二极管Dn可以提供人体模型静电放电的静电泄放通路。
如图2和图3所示，接地焊盘和电源焊盘均位于裸片上，裸片的衬底401中设置有第一阱410、第二阱420和第三阱430，衬底401为P型衬底，第一阱410、第二阱420和第三阱430均为N阱；第一阱410包含第一P型重掺杂区411和第一N型重掺杂区412，电源焊盘VDD与第一P型重掺杂区411电连接；第二阱420包含第二P型重掺杂区421和第二N型重掺杂区422，第二P型重掺杂区421和第一N型重掺杂区412电连接；第三阱430包含第三P型重掺杂区431和第三N型重掺杂区432，第三P型重掺杂区431与第二N型重掺杂区422电连接；内部电路输入端Inside与第三N型重掺杂区432电连接。衬底401中还有第七N型重掺杂区433和第七P型重掺杂区434，内部电路输入端Inside与第七N型重掺杂区433和第七P型重掺杂区434电 连接。
其中，第一P型重掺杂区411、第一阱410、衬底401形成第一PNP晶体管；第一阱410、衬底401、第七N型重掺杂区433形成第一NPN晶体管。第一阱410至第七P型重掺杂区434之间形成第一电阻R1。
如图2所示，第二阱420中，第二P型重掺杂区421与第二N型重掺杂区422之间形成第三二极管D3；第三阱430中，第三P型重掺杂区431与第三N型重掺杂区432之间形成第三二极管D3。
第二阱420和第三阱430之间还可以设置有多个N阱，这些N阱与第二阱420和第三阱430结构相同，每个N阱中均形成一个第三二极管D3，相当于在第一PNP晶体管Q1的基极与内部电路输入端Inside之间串联多个第三二极管D3。
如图2所示的是从内部电路输入端Inside到电源焊盘VDD负极性静电放电模式(ND-mode)。在该模式中，第一PNP晶体管Q1和第一NPN晶体管Q2同时导通，电源正极的静电脉冲经由导通的第一PNP晶体管Q1和第一NPN晶体管Q2释放至内部电路输入端Inside。
在本公开实施例中，第三阱430与第一阱410之间形成第一二极管D1。在处于从内部电路输入端Inside到电源焊盘VDD正极性静电放电模式(PD-mode)中时，第一PNP晶体管Q1和第一NPN晶体管Q2不导通，内部电路的静电脉冲经由第一二极管D1释放至电源正极。
如图4和图5所示，衬底中设置有第四阱440、第五阱450和第六阱460，第四阱440、第五阱450和第六阱460均为N阱；第四阱440包含第四P型重掺杂区441和第四N型重掺杂区442，内部电路输入端Inside与第四P型重掺杂区441电连接；第五阱450包含第五P型重掺杂区451和第五N型重掺杂区452，第五P型重掺杂区451和第四N型重掺杂区452电连接；第六阱460包含第六P型重掺杂区461和第六N型重掺杂区462，第六P型重掺杂区461与第六N型重掺杂区462电连接；接地焊盘VSS与第六N型重掺杂区462电连接。衬底401中还有第八N型重掺杂区463和第八P型重掺杂区464，第八N型重掺杂区463和第八P型重掺杂区464均与接地焊盘电连接。
第四P型重掺杂区441、第四阱440、衬底401形成第二PNP晶体管；第四阱440、衬底401、第八N型重掺杂区463形成第二NPN晶体管。第四阱440至第八P型重掺杂区464之间形成第二电阻R2。
如图4所示，第五阱450中，第五P型重掺杂区451与第五N型重掺杂区452之间形成第四二极管D4；第六阱460中，第六P型重掺杂区461与第六N型重掺杂区462之间形成第四二极管D4。
第五阱450和第六阱460之间还可以设置有多个N阱，这些N阱与第五阱450和第六阱460结构相同，每个N阱中均形成一个第四二极管D3，相当于在第六PNP晶体管Q3的基极与接地焊盘VSS之间串联多个第四二极管D4。
如图4所示的是从内部电路输入端Inside到接地焊盘VSS的负极性静电放电模式(NS-mode)在该模式中，第二PNP晶体管Q3和第二NPN晶体管Q4同时导通，内部电路的静电脉冲经由导通的第二PNP晶体管Q3和第二NPN晶体管Q4释放至电源地。
在本公开实施例中，第六阱与第四阱之间形成第二二极管。在内部电路输入端Inside到接地焊盘VSS的正极性放电模式(PS-mode)中，第二PNP晶体管Q3和第二NPN晶体管Q4不导通，电源地引入的静电脉冲经由第二二极管D2释放至内部电路输入端Inside。
当有ESD发生时，内部电路可通过静电保护电路泄放静电。内部电路在静电放电时可能处于四种模式中，包括：从内部电路输入端Inside到电源焊盘VDD打负电，泄放路径为第一PNP晶体管Q1和第一NPN晶体管Q2；从内部电路输入端Inside到电源焊盘VDD打正电，泄放路径为第一二极管D1；从内部电路输入端Inside到接地焊盘VSS打负电，泄放路径为第二PNP晶体管Q3和第二NPN晶体管Q4；从内部电路输入端Inside到接地焊盘VSS打负电，泄放路径为第二二极管D2。本公开实施例的技术方案可以实现充电器件模型下对这四种模式的静电保护。
本公开实施例的电路设计可以应用于半导体集成电路的输入和输出电路的ESD保护，尤其可以应用于半导体集成电路的氧化层比较薄的先进制程的输入电路的CDM静电保护。该电路设计方法也可应用于各类半导体集成电路如逻辑、模拟以及各类存储器芯片的CDM的ESD保护。
在本公开实施例所的静电保护电路中，通过在内部电路和电源焊盘、接地焊盘之间设置二极管辅助触发晶闸管电路和二极管，实现了对充电器件模型的静电保护，由于静电保护不采用MOS器件，避免了静电保护电路的MOS器件在发生CDM静电放电时，输入缓冲器的MOS器件的氧化层先于静电保护电路的MOS器件击穿，从而提高了芯片的静电保护能力。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (12)

  1. 一种静电保护电路，与内部电路连接，其中，所述静电保护电路包括：
    第一电路、与所述第一电路并联的第一二极管、第二电路以及与所述第二电路并联的第二二极管；其中，
    所述第一电路连接在电源焊盘和内部电路输入端之间，所述第二电路连接在所述内部电路输入端和接地焊盘之间；
    所述第一电路和所述第二电路为二极管辅助触发晶闸管电路。
  2. 根据权利要求1所述的静电保护电路，其中，
    所述第一电路包括第一PNP晶体管和第一NPN晶体管，所述第一PNP晶体管的发射极与所述电源焊盘连接，所述第一PNP晶体管的基极与所述第一NPN晶体管的集电极连接后通过串联的至少一个第三二极管与所述内部电路输入端连接，所述第一PNP晶体管的集电极与所述第一NPN晶体管的基极连接后通过第一电阻与所述内部电路输入端连接，所述第一NPN晶体管的发射极与所述内部电路输入端连接；所述第一二极管的负极与所述电源焊盘连接；
    所述第二电路包括第二PNP晶体管和第二NPN晶体管，所述第二PNP晶体管的发射极与所述内部电路输入端连接，所述第二PNP晶体管的基极与所述第二NPN晶体管的集电极连接后通过串联的至少一个第四二极管与所述接地焊盘连接，所述第二PNP晶体管的集电极与所述第二NPN晶体管的基极连接后通过第二电阻与所述接地焊盘连接；所述第二二极管的正极与所述接地焊盘连接。
  3. 根据权利要求2所述的静电保护电路，其中，所述静电保护电路还包括连接于所述电源焊盘和输入焊盘之间的第五二极管和连接于所述输入焊盘和所述接地焊盘之间的第六二极管；
    其中，所述第五二极管的正极与所述输入焊盘连接，所述第六二极管的正极与所述接地焊盘连接。
  4. 根据权利要求3所述的静电保护电路，其中，所述静电保护电路还包括连接于所述输入焊盘和所述内部电路输入端之间的输入电阻。
  5. 根据权利要求4所述的静电保护电路，其中，所述接地焊盘和电源焊盘均位于裸片上，所述裸片的衬底中设置有第一阱、第二阱和第三阱，所述衬底为P型衬底，所述第一阱、第二阱和第三阱均为N阱；
    所述第一阱包含第一P型重掺杂区和第一N型重掺杂区，所述电源焊盘与所述第一P型重掺杂区电连接；
    所述第二阱包含第二P型重掺杂区和第二N型重掺杂区，所述第二P型重掺杂区和所述第一N型重掺杂区电连接；
    所述第三阱包含第三P型重掺杂区和第三N型重掺杂区，所述第三P型重掺杂区与所述第二N型重掺杂区电连接；所述内部电路输入端与所述第三N型重掺杂区电连接。
  6. 根据权利要求5所述的静电保护电路，其中，所述第一P型重掺杂区、所述第一阱、所述衬底形成第一PNP晶体管；
    所述第一阱、所述衬底、所述第三阱形成第一NPN晶体管。
  7. 根据权利要求5所述的静电保护电路，其中，所述第一阱至所述第三阱之间形成第一电阻。
  8. 根据权利要求5所述的静电保护电路，其中，所述第三阱与所述第一阱之间形成第一二极管。
  9. 根据权利要求5所述的静电保护电路，其中，所述衬底中设置有第四阱、第五阱和第六阱，所述第四阱、所述第五阱和所述第六阱均为N阱；
    所述第四阱包含第四P型重掺杂区和第四N型重掺杂区，所述内部电路输入端与所述第四P型重掺杂区电连接；
    所述第五阱包含第五P型重掺杂区和第五N型重掺杂区，所述第五P型重掺杂区和所述第四N型重掺杂区电连接；
    所述第六阱包含第六P型重掺杂区和第六N型重掺杂区，所述第六P型重掺杂区与所述第六N型重掺杂区电连接；所述接地焊盘与所述第六N型重掺杂区电连接。
  10. 根据权利要求9所述的静电保护电路，其中，
    所述第四P型重掺杂区、所述第四阱、所述衬底形成第二PNP晶体管；
    所述第四阱、所述衬底、所述第六阱形成第二NPN晶体管。
  11. 根据权利要求9所述的静电保护电路，其中，所述第四阱至所述第六阱之间形成第二电阻。
  12. 根据权利要求9所述的静电保护电路，其中，所述第六阱与所述第四阱之间形成第二二极管。
PCT/CN2021/079589 2020-04-20 2021-03-08 静电保护电路 WO2021213024A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP21792800.1A EP3975249B1 (en) 2020-04-20 2021-03-08 Electrostatic protection circuit
US17/386,480 US11699697B2 (en) 2020-04-20 2021-07-27 Electrostatic protection circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010313422.X 2020-04-20
CN202010313422.XA CN113540070B (zh) 2020-04-20 2020-04-20 静电保护电路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/386,480 Continuation US11699697B2 (en) 2020-04-20 2021-07-27 Electrostatic protection circuit

Publications (1)

Publication Number Publication Date
WO2021213024A1 true WO2021213024A1 (zh) 2021-10-28

Family

ID=78093731

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/079589 WO2021213024A1 (zh) 2020-04-20 2021-03-08 静电保护电路

Country Status (4)

Country Link
US (1) US11699697B2 (zh)
EP (1) EP3975249B1 (zh)
CN (1) CN113540070B (zh)
WO (1) WO2021213024A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230012301A1 (en) * 2021-07-12 2023-01-12 Changxin Memory Technologies, Inc. Electro-static discharge protection circuit and semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113540070B (zh) * 2020-04-20 2023-12-12 长鑫存储技术有限公司 静电保护电路
EP4020551A4 (en) * 2020-05-12 2022-12-28 Changxin Memory Technologies, Inc. ELECTROSTATIC PROTECTION CIRCUIT

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020064007A1 (en) * 2000-12-28 2002-05-30 Chyh-Yih Chang Low substrate-noise electrostatic discharge protection circuits with bi-directional silicon diodes
US20050184344A1 (en) * 2004-02-25 2005-08-25 Ming-Dou Ker ESD protection designs with parallel LC tank for Giga-Hertz RF integrated circuits
CN101030575A (zh) * 2006-02-28 2007-09-05 松下电器产业株式会社 半导体集成电路装置
CN101385214A (zh) * 2004-03-23 2009-03-11 沙诺夫公司 使用源/体泵保护栅氧化物的方法及装置
CN103094273A (zh) * 2011-10-31 2013-05-08 旺宏电子股份有限公司 静电放电保护元件
CN103733336A (zh) * 2011-08-23 2014-04-16 美光科技公司 结合静电放电保护电路及方法
CN107482004A (zh) * 2017-07-06 2017-12-15 北京时代民芯科技有限公司 一种外延工艺下多电源电压集成电路esd保护网络
CN110071102A (zh) * 2018-01-24 2019-07-30 东芝存储器株式会社 半导体装置

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4484244A (en) * 1982-09-22 1984-11-20 Rca Corporation Protection circuit for integrated circuit devices
US5359211A (en) * 1991-07-18 1994-10-25 Harris Corporation High voltage protection using SCRs
US5182220A (en) * 1992-04-02 1993-01-26 United Microelectronics Corporation CMOS on-chip ESD protection circuit and semiconductor structure
US5430595A (en) * 1993-10-15 1995-07-04 Intel Corporation Electrostatic discharge protection circuit
US5574618A (en) * 1994-02-17 1996-11-12 Harris Corporation ESD protection using SCR clamping
US5473169A (en) * 1995-03-17 1995-12-05 United Microelectronics Corp. Complementary-SCR electrostatic discharge protection circuit
US5754380A (en) * 1995-04-06 1998-05-19 Industrial Technology Research Institute CMOS output buffer with enhanced high ESD protection capability
US5541801A (en) * 1995-05-26 1996-07-30 United Microelectronics Corporation Low-voltage gate trigger SCR (LVGTSCR) ESD protection circuit for input and output pads
KR100220385B1 (ko) * 1996-11-02 1999-09-15 윤종용 정전기 보호 소자
US5754381A (en) * 1997-02-04 1998-05-19 Industrial Technology Research Institute Output ESD protection with high-current-triggered lateral SCR
JP4256544B2 (ja) * 1998-08-25 2009-04-22 シャープ株式会社 半導体集積回路の静電気保護装置、その製造方法および静電気保護装置を用いた静電気保護回路
JP2001244418A (ja) * 2000-03-01 2001-09-07 Nec Corp 半導体集積回路装置
US7548401B2 (en) * 2001-03-16 2009-06-16 Sarnoff Corporation Electrostatic discharge protection structures for high speed technologies with mixed and ultra-low voltage supplies
US7589944B2 (en) * 2001-03-16 2009-09-15 Sofics Bvba Electrostatic discharge protection structures for high speed technologies with mixed and ultra-low voltage supplies
JP2007531284A (ja) 2004-03-23 2007-11-01 サーノフ コーポレーション ソース／バルク・ポンピングを使用してゲート酸化膜を保護するための方法および装置
US7221027B2 (en) * 2004-05-18 2007-05-22 Winbond Electronics Corporation Latchup prevention method for integrated circuits and device using the same
US20060132996A1 (en) * 2004-12-17 2006-06-22 Poulton John W Low-capacitance electro-static discharge protection
US7238969B2 (en) * 2005-06-14 2007-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor layout structure for ESD protection circuits
JP2008047876A (ja) * 2006-06-29 2008-02-28 Sarnoff Corp クランプの静電放電保護
KR20080061004A (ko) * 2006-12-27 2008-07-02 주식회사 하이닉스반도체 정전기 방전 보호 회로 및 그의 레이아웃 방법
JP5232444B2 (ja) * 2007-11-12 2013-07-10 ルネサスエレクトロニクス株式会社 半導体集積回路
US7800128B2 (en) * 2008-06-12 2010-09-21 Infineon Technologies Ag Semiconductor ESD device and method of making same
US8283698B2 (en) * 2009-04-15 2012-10-09 Sofics Bvba Electrostatic discharge protection
US8279570B2 (en) * 2010-10-20 2012-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. ESD protection for RF circuits
US8759871B2 (en) * 2011-07-06 2014-06-24 Taiwan Semiconductor Manufacturing Co., Ltd. Bidirectional dual-SCR circuit for ESD protection
US8830640B2 (en) * 2012-06-21 2014-09-09 Texas Instruments Deutschland Gmbh Electrostatic discharge protection circuit
US9130008B2 (en) * 2013-01-31 2015-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Robust ESD protection with silicon-controlled rectifier
US9640523B2 (en) * 2015-09-08 2017-05-02 Hong Kong Applied Science and Technology Research Institute Company Limited Lateral-diode, vertical-SCR hybrid structure for high-level ESD protection
CN106920792A (zh) * 2015-12-28 2017-07-04 大唐恩智浦半导体有限公司 静电防护电路及其二极管触发保持可控硅整流器
US10298215B2 (en) * 2016-04-19 2019-05-21 Globalfoundries Singapore Pte. Ltd. Integrated circuit electrostatic discharge protection
US10134722B2 (en) * 2017-04-12 2018-11-20 Hong Kong Applied Science and Technology Research Institute Company Limited Embedded PMOS-trigger silicon controlled rectifier (SCR) with suppression rings for electro-static-discharge (ESD) protection
CN108879632B (zh) * 2017-05-09 2019-12-03 奇景光电股份有限公司 静电放电保护电路
US10446537B2 (en) * 2017-06-20 2019-10-15 Texas Instruments Incorporated Electrostatic discharge devices
US10141300B1 (en) * 2017-10-19 2018-11-27 Alpha And Omega Semiconductor (Cayman) Ltd. Low capacitance transient voltage suppressor
US10892258B2 (en) * 2019-01-04 2021-01-12 Nxp B.V. ESD-robust stacked driver
CN112447676A (zh) 2019-09-03 2021-03-05 长鑫存储技术有限公司 静电保护电路
US11495955B2 (en) * 2020-02-07 2022-11-08 Arm Limited Rectifier triggering techniques
CN113540070B (zh) * 2020-04-20 2023-12-12 长鑫存储技术有限公司 静电保护电路
EP4020551A4 (en) * 2020-05-12 2022-12-28 Changxin Memory Technologies, Inc. ELECTROSTATIC PROTECTION CIRCUIT

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020064007A1 (en) * 2000-12-28 2002-05-30 Chyh-Yih Chang Low substrate-noise electrostatic discharge protection circuits with bi-directional silicon diodes
US20050184344A1 (en) * 2004-02-25 2005-08-25 Ming-Dou Ker ESD protection designs with parallel LC tank for Giga-Hertz RF integrated circuits
CN101385214A (zh) * 2004-03-23 2009-03-11 沙诺夫公司 使用源/体泵保护栅氧化物的方法及装置
CN101030575A (zh) * 2006-02-28 2007-09-05 松下电器产业株式会社 半导体集成电路装置
CN103733336A (zh) * 2011-08-23 2014-04-16 美光科技公司 结合静电放电保护电路及方法
CN103094273A (zh) * 2011-10-31 2013-05-08 旺宏电子股份有限公司 静电放电保护元件
CN107482004A (zh) * 2017-07-06 2017-12-15 北京时代民芯科技有限公司 一种外延工艺下多电源电压集成电路esd保护网络
CN110071102A (zh) * 2018-01-24 2019-07-30 东芝存储器株式会社 半导体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230012301A1 (en) * 2021-07-12 2023-01-12 Changxin Memory Technologies, Inc. Electro-static discharge protection circuit and semiconductor device
US11848322B2 (en) * 2021-07-12 2023-12-19 Changxin Memory Technologies, Inc. Electro-static discharge protection circuit and semiconductor device

Also Published As

Publication number Publication date
EP3975249B1 (en) 2023-12-20
US20210351176A1 (en) 2021-11-11
EP3975249A1 (en) 2022-03-30
CN113540070B (zh) 2023-12-12
CN113540070A (zh) 2021-10-22
EP3975249A4 (en) 2022-08-17
US11699697B2 (en) 2023-07-11

Similar Documents

Publication Publication Date Title
WO2021213024A1 (zh) 静电保护电路
TWI580001B (zh) 靜電放電保護電路、結構及其製造方法
US8039899B2 (en) Electrostatic discharge protection device
JP4401500B2 (ja) 静電放電における寄生バイポーラ効果を低減する半導体装置および方法
US5932916A (en) Electrostatic discharge protection circuit
JP3573674B2 (ja) 半導体集積回路の入出力保護装置とその保護方法
JP2010525575A (ja) 低下したトリガ電圧を有するｅｓｄ保護回路
EP1946381A2 (en) Low capacitance scr with trigger element
US8703547B2 (en) Thyristor comprising a special doped region characterized by an LDD region and a halo implant
JPH1041469A (ja) 半導体装置
US20050045952A1 (en) Pfet-based esd protection strategy for improved external latch-up robustness
CN111668209B (zh) 一种低漏电的用于低压esd防护的可控硅整流器
US7629210B2 (en) Method for fabricating an ESD protection apparatus for discharging electric charge in a depth direction
JPH05121670A (ja) 半導体入力保護装置
KR100504203B1 (ko) 반도체장치의 보호소자
US6707653B2 (en) Semiconductor controlled rectifier for use in electrostatic discharge protection circuit
WO2022267465A1 (zh) Esd保护器件、保护电路及制备方法
KR101006514B1 (ko) 정전 방전 보호 장치용 반도체 제어 정류기
US6784499B2 (en) Semiconductor device serving as a protecting element
CN112447703A (zh) 静电放电防护元件
WO2022134606A1 (zh) 静电保护结构、静电保护电路、芯片
KR20190133349A (ko) Esd 보호를 위한 반도체 장치
WO2022188326A1 (zh) 静电保护电路及半导体器件
US20220320074A1 (en) Electrostatic discharge protection circuit and semiconductor device
KR20070058165A (ko) 반도체 장치의 정전 방전 보호 소자

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21792800

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021792800

Country of ref document: EP

Effective date: 20211220

NENP Non-entry into the national phase

Ref country code: DE