WO2022188326A1 - 静电保护电路及半导体器件 - Google Patents

静电保护电路及半导体器件 Download PDF

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Publication number
WO2022188326A1
WO2022188326A1 PCT/CN2021/106499 CN2021106499W WO2022188326A1 WO 2022188326 A1 WO2022188326 A1 WO 2022188326A1 CN 2021106499 W CN2021106499 W CN 2021106499W WO 2022188326 A1 WO2022188326 A1 WO 2022188326A1
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Prior art keywords
electrostatic
electrically connected
pulse detection
pad
terminal
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PCT/CN2021/106499
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English (en)
French (fr)
Inventor
许杞安
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to JP2022547945A priority Critical patent/JP2023521277A/ja
Priority to EP21893124.4A priority patent/EP4086958A4/en
Priority to KR1020227028729A priority patent/KR20220129608A/ko
Priority to US17/453,910 priority patent/US11842995B2/en
Publication of WO2022188326A1 publication Critical patent/WO2022188326A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses

Definitions

  • the present application relates to, but is not limited to, an electrostatic protection circuit and a semiconductor device.
  • FIG. 1A is a schematic diagram of a conventional circuit structure. Please refer to FIG. 1A.
  • the internal circuit 10 is electrically connected to the first pad VDD and the second pad VSS, respectively.
  • one of the pads eg, the first pad VDD
  • the static electricity will flow through the internal circuit 10, thereby causing the internal circuit 10 to be damaged by static electricity.
  • FIG. 1B is a schematic diagram of a conventional circuit with an electrostatic protection circuit. Please refer to FIG. 1B.
  • the internal circuit 10 is electrically connected to the first pad VDD and the second pad VSS, respectively, and the electrostatic protection circuit 11 is also connected to the first pad respectively.
  • the pad VDD and the second pad VSS are electrically connected, that is, the electrostatic protection circuit 11 is connected in parallel with the internal circuit 10 .
  • static electricity is generated on one of the pads (for example, the first pad VDD)
  • the static electricity will be discharged through the electrostatic protection circuit 11 and will not flow through the internal circuit 10, so as to protect the internal circuit 10 and avoid The internal circuit 10 is damaged by static electricity.
  • the existing electrostatic protection circuit has a large error in recognizing normal power-on and electrostatic power-on, which may cause false startup, and the existing electrostatic protection circuit cannot fully discharge electrostatic charges.
  • An embodiment of the present application provides an electrostatic protection circuit, which is electrically connected to a first solder pad and a second solder pad.
  • the electrostatic protection circuit includes: an electrostatic discharge transistor, which has a control terminal, a first terminal, a second terminal, and a substrate terminal, The first end is electrically connected to the first pad, the second end is electrically connected to the second pad; the electrostatic pulse detection circuit has an upper end, a lower end, and an output end, and the upper end is electrically connected to the second pad.
  • the first bonding pad, the lower end is electrically connected to the second bonding pad, and the output end is electrically connected to the control end and the substrate end.
  • the embodiment of the present application further provides a semiconductor device, which includes an electrostatic protection circuit, the electrostatic protection circuit is electrically connected to the first bonding pad and the second bonding pad, and the electrostatic protection circuit includes:
  • An electrostatic discharge transistor has a control terminal, a first terminal, a second terminal, and a substrate terminal, the first terminal is electrically connected to the first pad, and the second terminal is electrically connected to the second pad ;
  • An electrostatic pulse detection circuit has an upper end, a lower end and an output end, the upper end is electrically connected to the first pad, the lower end is electrically connected to the second pad, and the output end is electrically connected to the control end and the substrate end.
  • 1A is a schematic diagram of an existing circuit structure
  • 1B is a schematic diagram of an existing circuit structure provided with an electrostatic protection circuit
  • FIG. 2 is a schematic diagram of the application of the electrostatic protection circuit according to the first embodiment of the present application
  • FIG. 3 is a schematic diagram of the application of the electrostatic protection circuit according to the second embodiment of the present application.
  • FIG. 4 is a schematic diagram of an application of an electrostatic protection circuit according to a third embodiment of the present application.
  • FIG. 5 is a schematic diagram of the application of the electrostatic protection circuit according to the fourth embodiment of the present application.
  • FIG. 6 is a schematic diagram of the application of the electrostatic protection circuit according to the fifth embodiment of the present application.
  • FIG. 7 is a schematic diagram of the application of the electrostatic protection circuit according to the sixth embodiment of the present application.
  • FIG. 8 is a schematic top view of a semiconductor structure for forming the electrostatic discharge transistor of the semiconductor device according to the seventh embodiment of the present application;
  • FIG. 9 is a schematic top view of the semiconductor structure forming the electrostatic discharge transistor of the semiconductor device according to the eighth embodiment of the present application.
  • FIG. 10 is a schematic top view of a semiconductor structure forming the electrostatic discharge transistor of the semiconductor device according to the ninth embodiment of the present application;
  • FIG. 11 is a schematic cross-sectional schematic diagram of the structure shown in FIG. 9 .
  • FIG. 2 is a schematic diagram of the application of the electrostatic protection circuit according to the first embodiment of the present application.
  • the internal circuit 20 is electrically connected to the first pad VDD and the second pad VSS, respectively, and the electrostatic protection circuit 21 is also electrically connected to the first pad VDD and the second pad VSS, respectively, that is, the electrostatic protection The circuit 21 is connected in parallel with the internal circuit 20 .
  • the static electricity When static electricity is generated on one of the pads (for example, the first pad VDD), the static electricity will be discharged through the electrostatic protection circuit 21 instead of flowing through the internal circuit 20, so as to protect the internal circuit 20 and avoid The internal circuit 20 is damaged by static electricity.
  • the first pad VDD is a power pad
  • the second pad VSS is a ground pad.
  • the first pad is a ground pad
  • the first pad is a ground pad.
  • Two pads are power pads, or both are power pads or both are ground pads.
  • the electrostatic protection circuit 20 of the present application includes an electrostatic discharge transistor Mesd and an electrostatic pulse detection circuit 201 .
  • the electrostatic discharge transistor Mesd has a control terminal, a first terminal, a second terminal, and a substrate terminal, the first terminal is electrically connected to the first pad VDD, and the second terminal is electrically connected to the first pad VDD. Two pads VSS.
  • the electrostatic pulse detection circuit 201 has an upper end, a lower end, and an output end. The upper end is electrically connected to the first pad VDD, the lower end is electrically connected to the second pad VSS, and the output end is electrically connected to the first pad VDD.
  • the control terminal and the substrate terminal of the electrostatic discharge transistor Mesd is configured to the electrostatic discharge transistor Mesd.
  • the electrostatic protection circuit of the present application uses the electrostatic pulse detection circuit 201 to detect pulses to distinguish between the normal power-on pulse and the electrostatic power-on pulse, so as to avoid false activation of the electrostatic protection circuit, and the electrostatic pulse detection circuit 201 is used to increase the delay time to make The electrostatic discharge transistor Mesd fully discharges electrostatic charges.
  • the output terminal of the electrostatic pulse detection circuit 201 is electrically connected to the control terminal of the electrostatic discharge transistor Mesd and the substrate terminal, that is, the control terminal of the electrostatic discharge transistor Mesd is short-circuited to the substrate terminal, which improves the The potential at the substrate end reduces the threshold voltage of the electrostatic discharge transistor Mesd and enhances the channel conduction capability.
  • the electrostatic charge can be quickly discharged through the electrostatic discharge transistor Mesd, which enhances the electrostatic charge of the electrostatic protection circuit. discharge performance.
  • the electrostatic discharge transistor Mesd is an NMOS transistor.
  • the first terminal of the NMOS transistor is electrically connected to the first pad VDD, and the second terminal of the NMOS transistor is electrically connected to the second pad VSS.
  • the first end of the NMOS transistor is the source end of the NMOS transistor, and the second end of the NMOS transistor is the drain end of the NMOS transistor; or, the first end of the NMOS transistor is the drain end of the NMOS transistor, so
  • the second terminal of the NMOS transistor is the source terminal of the NMOS transistor, which is not limited in this application.
  • the electrostatic pulse detection circuit 201 includes a capacitor C1 and a resistor R1.
  • the capacitor C1 has a first end and a second end, and the first end of the capacitor C1 serves as the upper end of the electrostatic pulse detection circuit 201 , that is, the first end of the capacitor C1 is electrically connected to the first pad VDD. connect.
  • the resistor R1 has a first end and a second end, and the first end of the resistor R1 serves as the lower end of the electrostatic pulse detection circuit 201 , that is, the first end of the resistor R1 is electrically connected to the second pad VSS. connect.
  • the second end of the resistor R1 and the second end of the capacitor C1 together serve as the output end of the electrostatic pulse detection circuit 201 , that is, the second end of the resistor R1 and the second end of the capacitor C1 together with
  • the control terminal of the electrostatic discharge transistor Mesd is electrically connected to the substrate terminal.
  • the control terminal of the ESD transistor Mesd when the first pad VDD and the second pad VSS are normally activated and working, the control terminal of the ESD transistor Mesd is at a low level, the ESD transistor Mesd is turned off, and the current flows through The internal current 20 ensures the normal operation of the internal circuit 20 .
  • static electricity is generated on the first pad VDD
  • the voltage of the first pad VDD begins to rise.
  • the control terminal of the electrostatic discharge transistor Mesd is at a high level, the electrostatic discharge transistor Mesd is turned on, and the electrostatic charge flows through the static electricity.
  • the transistor Mesd is discharged to discharge static electricity, so as to prevent the internal circuit 20 from being damaged by static electricity.
  • the present application also provides a second embodiment.
  • the difference between the second embodiment and the first embodiment is that the connection method of the capacitance and the resistance of the electrostatic pulse detection circuit 201 is different.
  • FIG. 3 is a schematic diagram of the application of the electrostatic protection circuit according to the second embodiment of the present application.
  • the electrostatic pulse detection circuit 201 includes a resistor R1 , a capacitor C1 and an inverter P1 .
  • the resistor R1 has a first end and a second end, and the first end of the resistor R1 serves as the upper end of the electrostatic pulse detection circuit 201 , that is, the first end of the resistor R1 is electrically connected to the first pad VDD. connect.
  • the capacitor C1 has a first end and a second end, and the first end of the capacitor C1 serves as the lower end of the electrostatic pulse detection circuit 201 , that is, the first end of the capacitor C1 is electrically connected to the second pad VSS. connect.
  • the inverter P1 has an input terminal and an output terminal. The second terminal of the resistor R1 and the second terminal of the capacitor C1 are electrically connected to the input terminal of the inverter P1.
  • the inverter P1 The output terminal of 1 is used as the output terminal of the electrostatic pulse detection circuit 201, that is, the output terminal of the inverter P1 is electrically connected to the control terminal and the substrate terminal of the electrostatic discharge transistor Mesd.
  • the control terminal of the ESD transistor Mesd when the first pad VDD and the second pad VSS are normally activated and working, the control terminal of the ESD transistor Mesd is at a low level, the ESD transistor Mesd is turned off, and the current flows through The internal circuit 20 ensures the normal operation of the internal circuit 20 .
  • static electricity is generated on the first pad VDD
  • the voltage of the first pad VDD begins to rise.
  • the control terminal of the static discharge transistor Mesd is at a high level, and the static discharge is discharged.
  • the transistor Mesd is turned on, and the electrostatic charge flows through the electrostatic discharge transistor Mesd to discharge the static electricity, so as to prevent the internal circuit 20 from being damaged by static electricity.
  • the RC time constant is usually 0.1-1 ⁇ m second.
  • R1 is a 50K ohm N+ diffusion resistor
  • C1 is a 20PF NMOS capacitor.
  • the present application also provides a third embodiment, which can reduce the occupied layout space and greatly reduce the leakage current while keeping the original RC time constant unchanged.
  • FIG. 4 is a schematic diagram of the application of the electrostatic protection circuit according to the third embodiment of the present application.
  • the electrostatic pulse detection circuit 201 includes a capacitor C1 and a diode group D1 .
  • the capacitor C1 has a first end and a second end, and the first end of the capacitor C1 serves as the upper end of the electrostatic pulse detection circuit 201 , that is, the first end of the capacitor C1 is electrically connected to the first pad VDD. connect.
  • the diode group D1 has a first end and a second end.
  • the first end of the diode group D1 serves as the lower end of the electrostatic pulse detection circuit 201 , that is, the first end of the diode group D1 is connected to the second end.
  • Pad VSS is electrically connected.
  • the second end of the diode group D1 and the second end of the capacitor C1 together serve as the output end of the electrostatic pulse detection circuit 201 , that is, the second end of the diode group D1 and the second end of the capacitor C1 It is electrically connected to the control terminal and the substrate terminal of the electrostatic discharge transistor Mesd in common.
  • the diode group D1 is equivalent to the resistor R1 in the first embodiment.
  • the diode group D1 occupies a very small layout space, and so on The effective resistance value is greatly improved, so that a very small capacitor C1 can be used to form an equivalent RC circuit. That is, the third embodiment of the present application can greatly reduce the occupied layout space and greatly reduce the capacitance value while keeping the RC time constant unchanged, and the electrostatic discharge transistor Mesd can fully discharge the electrostatic charge during the time when static electricity occurs. At the same time, the leakage current is also reduced, and the reliability of the semiconductor device is improved.
  • the diode group D1 is formed by connecting a plurality of diodes in series.
  • the diode group D1 is formed by connecting a diode D11 and a diode D22 in series.
  • other numbers of diodes may also be used in series to form the diode group D1 according to the voltage requirement of the control terminal of the electrostatic discharge transistor Mesd, which is not limited in the present application.
  • the control terminal of the static electricity discharge transistor Mesd is at a high level, the static electricity discharge transistor Mesd is turned on, and the static electricity is discharged.
  • the charge flows through the electrostatic discharge transistor Mesd, thereby discharging the electrostatic charge, realizing the electrostatic protection of the internal circuit 20 in PS mode, and preventing the internal circuit 20 from being damaged by static electricity.
  • the electrostatic discharge transistor Mesd is turned off, and the parasitic diode formed by the electrostatic discharge transistor Mesd discharges the electrostatic charge to realize the NS mode of the internal circuit 20.
  • the electrostatic protection can prevent the internal circuit 20 from being damaged by static electricity.
  • the present application also provides a fourth embodiment.
  • the difference between the fourth embodiment and the third embodiment is that the connection method between the capacitance of the electrostatic pulse detection circuit 201 and the diode device is different.
  • FIG. 5 is a schematic diagram of the application of the electrostatic protection circuit according to the fourth embodiment of the present application.
  • the electrostatic pulse detection circuit 201 includes a diode group D1 , a capacitor C1 and an inverter P1 .
  • the diode group D1 has a first end and a second end, and the second end of the diode group D1 serves as the upper end of the electrostatic pulse detection circuit 201 , that is, the second end of the diode group D1 is connected to the first terminal.
  • Pad VDD is electrically connected.
  • the capacitor C1 has a first end and a second end, and the first end of the capacitor C1 serves as the lower end of the electrostatic pulse detection circuit 201 , that is, the first end of the capacitor C1 is electrically connected to the second pad VSS. connect.
  • the inverter P1 has an input terminal and an output terminal. The first terminal of the diode group D1 and the second terminal of the capacitor C1 are electrically connected to the input terminal of the inverter P1.
  • the inverter P1 The output terminal of 1 is used as the output terminal of the electrostatic pulse detection circuit 201, that is, the output terminal of the inverter P1 is electrically connected to the control terminal and the substrate terminal of the electrostatic discharge
  • the diode group D1 is equivalent to the resistor R1 in the second embodiment.
  • the diode group D1 occupies a very small layout space, and the like
  • the effective resistance value is greatly improved, so that a very small capacitor C1 can be used to form an equivalent RC circuit. That is, the fourth embodiment of the present application can greatly reduce the occupied layout space and greatly reduce the capacitance value while keeping the RC time constant unchanged, and the electrostatic discharge transistor Mesd can fully discharge the electrostatic charge during the time when static electricity occurs. At the same time, the leakage current is also reduced, and the reliability of the semiconductor device is improved.
  • the diode group D1 is formed by connecting a plurality of diodes in series.
  • the diode group D1 is formed by connecting a diode D11 and a diode D22 in series.
  • other numbers of diodes may also be used in series to form the diode group D1 according to the voltage requirement of the control terminal of the electrostatic discharge transistor Mesd, which is not limited in the present application.
  • the control terminal of the static electricity discharge transistor Mesd is at a high level, the static electricity discharge transistor Mesd is turned on, and the static electricity is discharged.
  • the charge flows through the electrostatic discharge transistor Mesd, thereby discharging the electrostatic charge, realizing the electrostatic protection of the internal circuit 20 in PS mode, and preventing the internal circuit 20 from being damaged by static electricity.
  • the electrostatic discharge transistor Mesd is turned off, and the parasitic diode formed by the electrostatic discharge transistor Mesd discharges the electrostatic charge to realize the NS mode of the internal circuit 20.
  • the electrostatic protection can prevent the internal circuit 20 from being damaged by static electricity.
  • the diode group D1 can be formed by at least one diode connected in series, and in other embodiments of the present application, the diodes of the diode group are composed of transistors whose gates and drains are short-circuited constitute.
  • FIG. 6 is a schematic diagram of the application of the electrostatic protection circuit according to the fifth embodiment of the present application. The difference between the fifth embodiment and the third embodiment is that the diodes of the diode group D1 are composed of transistors whose gates and drains are short-circuited. .
  • the transistor M1 whose gate and drain are short-circuited and the transistor M2 whose gate and drain are short-circuited form a diode group D1 in series.
  • a transistor with a gate-drain shorted can operate in the saturation region, thus acting as a diode.
  • the transistor M1 and the transistor M2 working in the saturation region are connected in series, which is equivalent to a resistor with a larger resistance value, so that an equivalent RC circuit can be formed with a small capacitor, that is, this embodiment can maintain Under the condition that the RC time constant remains unchanged (that is, the electrostatic discharge transistor Mesd can fully discharge the electrostatic charge during the time of static electricity generation), compared with the first embodiment, the occupied layout space is greatly reduced, so that the overall layout area can be greatly reduced At the same time, the mode of large resistance and small capacitance is formed, which greatly reduces the leakage current.
  • the transistors forming the diode group D1 are of the same conductivity type, for example, the transistors M1 and M2 are both NMOS transistors, or the transistors M1 and M2 are both PMOS transistors. In other embodiments of the present application, the transistors forming the diode group D1 are of different conductivity types.
  • the diode group D1 is composed of one or more NMOS transistors whose gates and drains are shorted and one or more PMOS transistors whose gates and drains are shorted in series.
  • the present application also provides a sixth embodiment.
  • the difference between the sixth embodiment and the fifth embodiment is that the connection method between the capacitance and the diode group of the electrostatic pulse detection circuit 201 is different.
  • FIG. 7 is a schematic diagram of the application of the electrostatic protection circuit according to the sixth embodiment of the present application.
  • the electrostatic pulse detection circuit 201 includes a diode group D1 , a capacitor C1 and an inverter P1 .
  • the diode group D1 is composed of transistors whose gates and drains are short-circuited in series.
  • the transistor M1 whose gate and drain are short-circuited and the transistor M2 whose gate and drain are short-circuited form a diode group D1 in series.
  • the diode group D1 has a first end and a second end, and the second end of the diode group D1 serves as the upper end of the electrostatic pulse detection circuit 201 , that is, the second end of the diode group D1 is connected to the first terminal.
  • Pad VDD is electrically connected.
  • the capacitor C1 has a first end and a second end, and the first end of the capacitor C1 serves as the lower end of the electrostatic pulse detection circuit 201 , that is, the first end of the capacitor C1 is electrically connected to the second pad VSS. connect.
  • the inverter P1 has an input terminal and an output terminal. The first terminal of the diode group D1 and the second terminal of the capacitor C1 are electrically connected to the input terminal of the inverter P1.
  • the inverter P1 The output end of the ESD pulse detection circuit 201 is used as the output end of the electrostatic pulse detection circuit 201 , that is, the output end of the inverter P1 is electrically connected to the control end and the substrate end of the electrostatic discharge transistor Mesd.
  • the electrostatic protection circuit of the present application can avoid false activation of the electrostatic protection circuit, and can increase the delay time, so that the electrostatic discharge transistor Mesd can fully discharge the electrostatic charge; in addition, the electrostatic protection circuit of the present application can also greatly reduce the occupied layout space , reduce leakage current and improve the reliability of semiconductor devices.
  • the present application also provides a semiconductor device, which adopts the above-mentioned electrostatic protection circuit.
  • the semiconductor device of the present application can prevent the electrostatic protection circuit from erroneously starting, and uses the electrostatic pulse detection circuit to increase the delay time, so that the electrostatic discharge transistor can fully discharge the electrostatic charge and improve the reliability of the semiconductor device.
  • the semiconductor structure for forming the ESD transistor includes: a semiconductor substrate 700 , a well region 710 , a source region 720 , a drain region 730 , and a gate 740 .
  • the semiconductor substrate 700 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, SOI or GOI, or the like. According to the actual requirements of the device, a suitable semiconductor material can be selected as the semiconductor substrate 700, which is not limited herein. Wherein, several connection pads 709 are provided in the semiconductor substrate 700 .
  • the well region 710 is disposed in the semiconductor substrate 700 .
  • the ESD transistor is an NMOS transistor, and the well region is a P-type region.
  • the ESD transistor is a PMOS transistor, then the well region 710 It can also be an N-type region.
  • the source regions 720 and the drain regions 730 are alternately arranged in the well region 710 .
  • the well region 710 is a P-type region
  • the source region 720 and the drain region 730 are N-type regions
  • the well region 710 is an N-type region type region
  • the source region 720 and the drain region 730 are P-type regions.
  • the gate electrode 740 is disposed on the semiconductor substrate 700 between the source region 720 and the drain region 730 , and the gate electrode 740 is electrically connected to the semiconductor substrate 700 .
  • the gate electrode 740 is electrically connected to the connection pad 709 of the semiconductor substrate 700 through the connection pad 749, so as to realize the electrical connection between the gate electrode 740 and the semiconductor substrate 700, that is, the electrostatic discharge
  • the control terminal of the discharge transistor is electrically connected to the substrate terminal.
  • the semiconductor structure includes a source region 720, a drain region 730 and a gate 740, while in other embodiments of the present application, the semiconductor structure includes a plurality of source regions 720, a plurality of Drain regions 730 and gates 740 .
  • the semiconductor structure includes a first source region 721 , a second Two source regions 722 , a first drain region 731 , a first gate 741 and a second gate 742 .
  • the first drain region 731 is located between the first source region 721 and the second source region 722
  • the first gate 741 is located between the first source region 721 and the first drain region 731
  • the second gate electrode 742 is located between the first drain region 731 and the second source region 722 .
  • the first drain region 731 is used as a common drain region.
  • connection pads 749 of the first gate 741 and the second gate 742 are electrically connected to the connection pads 709 of the semiconductor substrate 700 , so that the first gate 741 and the second gate 742 are electrically connected to the semiconductor substrate 700 .
  • the substrate 700 is electrically connected, that is, the control terminal of the electrostatic discharge transistor is electrically connected to the substrate terminal.
  • 10 is a schematic top view of a semiconductor structure for forming the electrostatic discharge transistor of the semiconductor device according to the ninth embodiment of the present application. Please refer to FIG. 10.
  • the semiconductor structure includes a plurality of source regions, a plurality of A drain region and a plurality of gates, the plurality of source regions and the plurality of drain regions are alternately arranged at intervals, and a gate is disposed between two adjacent source regions and drain regions.
  • the semiconductor structure includes a first source region 721 , a second source region 722 , a first drain region 731 , a second drain region 732 , a first gate 741 and a first The second gate 742 and the third gate 743 .
  • the first source regions 721 , the first drain regions 731 , the second source regions 722 , and the second drain regions 732 are alternately arranged at intervals.
  • the first gate is disposed between the first source region 721 and the first drain region 731
  • the second gate 742 is disposed between the first drain region 731 and the second source region 722
  • the third gate 743 is disposed between the second source region 722 and the second drain region 732 .
  • FIG. 9 is a schematic cross-sectional schematic diagram of the structure shown in FIG. 9 .
  • the first gate 741 , the second gate 742 and the well region 710 of the ESD transistor are short-circuited, that is, the ESD shown in FIG.
  • the control terminal of the discharge transistor Mesd is short-circuited with the substrate terminal, and both are connected to the output terminal of the electrostatic pulse detection circuit 201 , so that the control terminal of the electrostatic discharge transistor Mesd and the substrate terminal are equipotential.
  • the ESD transistor Mesd of the present application raises the potential of the substrate terminal, so that the threshold voltage of the ESD transistor Mesd is reduced, and the channel conductance is reduced. Enhanced communication ability. When electrostatic charge is generated, the electrostatic charge can be quickly discharged through the electrostatic discharge transistor Mesd, which greatly enhances the electrostatic charge discharge capability of the electrostatic protection circuit.

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Abstract

本申请提供一种静电保护电路及半导体器件，静电保护电路与第一焊垫及第二焊垫电连接，静电保护电路包括：静电泻放晶体管，具有控制端、第一端、第二端、衬底端，第一端电连接至第一焊垫，第二端电连接至第二焊垫；静电脉冲检测电路，具有上端、下端、输出端，上端电连接至第一焊垫，下端电连接至第二焊垫，输出端电连接至控制端和衬底端。本申请优点是，避免静电保护电路的误启动，且利用静电脉冲检测电路增加延时时间，以使静电泻放晶体管充分泻放静电电荷，且静电泻放晶体管的控制端与衬底端短接，提高了衬底端的电位，静电电荷能够快速经静电泻放晶体管泻放，增强了静电保护电路的静电电荷泻放能力。

Description

静电保护电路及半导体器件
相关申请引用说明
本申请要求于2021年03月10日递交的中国专利申请号202110260635.5，申请名为“静电保护电路及半导体器件”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及但不限于一种静电保护电路及半导体器件。
背景技术
近些年随着集成电路工艺的快速发展，MOS管的线宽越来越窄，结深(junction depth)越来越浅，栅氧层的厚度也越来越薄，这些都加速了电路设计对静电保护(ESD，Electro–Static Discharge)的需求。当线宽为1μm时，ESD事件对电路的影响很小，当进入0.18μm、0.13μm时代，尤其是90纳米以下时代，ESD成为了刻不容缓的问题。
图1A是现有的电路结构示意图，请参阅图1A，内部电路10分别与第一焊垫VDD及第二焊垫VSS电连接，当在其中一个焊垫(例如第一焊垫VDD)上产生静电时，静电会流经内部电路10，从而导致内部电路10被静电损伤。
为了避免内部电路被静电损伤，通常采用包含有钳位晶体管(Clamp Transistor)的钳位电路(Clamp Circuit)作为ESD保护电路的保护方案。图1B是现有的设置有静电保护电路的电路结构示意图，请参阅图1B，内部电路10分别与第一焊垫VDD及第二焊垫VSS电连接，静电保护电路11也分别与第一焊垫VDD及第二焊垫VSS电连接，即所述静电保护电路11与所述内部电路10并联。当在其中一个焊垫(例如第一焊垫VDD)上产生静电时，静电会经静电保护电路11泻放，而不会流经内部电路10，从而起到对内部电路10的保护作用，避免内部电路10受到静电损伤。
但是，现有的静电保护电路在识别正常上电与静电上电时存在较大误差，可能会造成误启动，且现有的静电保护电路无法充分泻放静电电荷。
发明内容
本申请实施例提供一种静电保护电路，与第一焊垫及第二焊垫电连接，静电保护电路包括：静电泻放晶体管，具有控制端、第一端、第二端、衬底端， 所述第一端电连接至所述第一焊垫，所述第二端电连接至所述第二焊垫；静电脉冲检测电路，具有上端、下端、输出端，所述上端电连接至所述第一焊垫，所述下端电连接至所述第二焊垫，所述输出端电连接至所述控制端和所述衬底端。
本申请实施例还提供一种半导体器件，其包括静电保护电路，所述静电保护电路与第一焊垫及第二焊垫电连接，所述静电保护电路包括：
静电泻放晶体管，具有控制端、第一端、第二端、衬底端，所述第一端电连接至所述第一焊垫，所述第二端电连接至所述第二焊垫；
静电脉冲检测电路，具有上端、下端、输出端，所述上端电连接至所述第一焊垫，所述下端电连接至所述第二焊垫，所述输出端电连接至所述控制端和所述衬底端。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A是现有的电路结构示意图；
图1B是现有的设置有静电保护电路的电路结构示意图；
图2是本申请第一实施例静电保护电路应用示意图；
图3是本申请第二实施例静电保护电路应用示意图；
图4是本申请第三实施例静电保护电路应用示意图；
图5是本申请第四实施例静电保护电路应用示意图；
图6是本申请第五实施例静电保护电路应用示意图；
图7是本申请第六实施例静电保护电路应用示意图；
图8是本申请第七实施例半导体器件的形成所述静电泻放晶体管的半导体结构的俯视示意图；
图9是本申请第八实施例半导体器件的形成所述静电泻放晶体管的半导体结构的俯视示意图；
图10是本申请第九实施例半导体器件的形成所述静电泻放晶体管的半导 体结构的俯视示意图；
图11是图9所示结构的截面原理示意图。
具体实施方式
为了使本申请的目的、技术手段及其效果更加清楚明确，以下将结合附图对本申请作进一步地阐述。应当理解，此处所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例，并不用于限定本申请。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图2是本申请第一实施例静电保护电路应用示意图。请参阅图2，内部电路20分别与第一焊垫VDD及第二焊垫VSS电连接，静电保护电路21也分别与第一焊垫VDD及第二焊垫VSS电连接，即所述静电保护电路21与所述内部电路20并联。当在其中一个焊垫(例如第一焊垫VDD)上产生静电时，静电会经静电保护电路21泻放，而不会流经内部电路20，从而起到对内部电路20的保护作用，避免内部电路20受到静电损伤。
其中，在本实施例中，第一焊垫VDD为电源焊垫，所述第二焊垫VSS为接地焊垫，在本申请其他实施例中，第一焊垫为接地焊垫，所述第二焊垫为电源焊垫，或者两者均为电源焊垫或均为接地焊垫。
本申请静电保护电路20包括静电泻放晶体管Mesd及静电脉冲检测电路201。所述静电泻放晶体管Mesd具有控制端、第一端、第二端、衬底端，所述第一端电连接至所述第一焊垫VDD，所述第二端电连接至所述第二焊垫VSS。所述静电脉冲检测电路201具有上端、下端、输出端，所述上端电连接至所述第一焊垫VDD，所述下端电连接至所述第二焊垫VSS，所述输出端电连接至所述静电泻放晶体管Mesd的控制端和衬底端。
本申请静电保护电路利用静电脉冲检测电路201检测脉冲，以区分电源正常上电脉冲及静电上电脉冲，从而避免静电保护电路的误启动，且利用静电脉冲检测电路201增加延时时间，以使静电泻放晶体管Mesd充分泻放静电电荷。另外，所述静电脉冲检测电路201的输出端电连接至所述静电泻放晶体管Mesd的控制端和所述衬底端，即将静电泻放晶体管Mesd的控制端与衬底端短接，提高了衬底端的电位，使得静电泻放晶体管Mesd的阈值电压降低，沟道导通 能力增强，则在产生静电时，静电电荷能够快速经静电泻放晶体管Mesd泻放，增强了静电保护电路的静电电荷泻放的性能。
在本实施例中，所述静电泻放晶体管Mesd为NMOS晶体管。所述NMOS晶体管的第一端电连接至所述第一焊垫VDD，所述NMOS晶体管的第二端电连接至所述第二焊垫VSS。其中，所述NMOS晶体管的第一端为NMOS晶体管的源极端，所述NMOS晶体管的第二端为NMOS晶体管的漏极端；或者，所述NMOS晶体管的第一端为NMOS晶体管的漏极端，所述NMOS晶体管的第二端为NMOS晶体管的源极端，本申请对此不限定。
在本实施例中，所述静电脉冲检测电路201包括电容C1及电阻R1。所述电容C1具有第一端及第二端，所述电容C1的第一端作为所述静电脉冲检测电路201的上端，即所述电容C1的第一端与所述第一焊垫VDD电连接。所述电阻R1具有第一端及第二端，所述电阻R1的第一端作为所述静电脉冲检测电路201的下端，即所述电阻R1的第一端与所述第二焊垫VSS电连接。所述电阻R1的第二端及所述电容C1的第二端共同作为所述静电脉冲检测电路201的输出端，即所述电阻R1的第二端及所述电容C1的第二端共同与所述静电泻放晶体管Mesd的控制端和衬底端电连接。
在第一实施例中，当第一焊垫VDD及第二焊垫VSS正常启动和正常工作时，静电泻放晶体管Mesd的控制端处于低电平，则静电泻放晶体管Mesd关闭，电流流经内部电流20，保证内部电路20的正常运行。当第一焊垫VDD产生静电时，第一焊垫VDD的电压开始攀升，此时，静电泻放晶体管Mesd的控制端处于高电平，则静电泻放晶体管Mesd导通，静电电荷流经静电泻放晶体管Mesd，进行静电泻放，避免内部电路20受到静电损伤。
本申请还提供一第二实施例，所述第二实施例与第一实施例的区别在于，所述静电脉冲检测电路201的电容与电阻的连接方法不同。具体地说，请参阅图3，其为本申请第二实施例静电保护电路应用示意图，在该实施例中，所述静电脉冲检测电路201包括电阻R1、电容C1及反相器P1。
所述电阻R1具有第一端及第二端，所述电阻R1的第一端作为所述静电脉冲检测电路201的上端，即所述电阻R1的第一端与所述第一焊垫VDD电连接。所述电容C1具有第一端及第二端，所述电容C1的第一端作为所述静 电脉冲检测电路201的下端，即所述电容C1的第一端与所述第二焊垫VSS电连接。所述反相器P1具有输入端及输出端，所述电阻R1的第二端及所述电容C1的第二端与所述反相器P1的输入端电连接，所述反相器P 1的输出端作为所述静电脉冲检测电路201的输出端，即所述反相器P 1的输出端与所述静电泻放晶体管Mesd的控制端和衬底端电连接。
在第二实施例中，当第一焊垫VDD及第二焊垫VSS正常启动和正常工作时，静电泻放晶体管Mesd的控制端处于低电平，则静电泻放晶体管Mesd关闭，电流流经内部电路20，保证内部电路20的正常运行。当第一焊垫VDD产生静电时，第一焊垫VDD的电压开始攀升，当电压升高到反相器P1能够工作时，静电泻放晶体管Mesd的控制端处于高电平，则静电泻放晶体管Mesd导通，静电电荷流经静电泻放晶体管Mesd，进行静电泻放，避免内部电路20受到静电损伤。
在第一实施例及第二实施例中，为区分出是静电还是电源启动的瞬态状态，且保证在静电发生的时间内Mesd能充分泄放静电电荷，RC时间常数通常为0.1-1微秒。例如，R1为50K欧姆的N+扩散电阻，C1为20PF的NMOS电容。但是，申请人发现，这样的RC时间常数设计会占用比较大的版图空间，同时也会导致较大的漏电电流。
为了解决上述问题，本申请还提供一第三实施例，其能够在保持原有RC时间常数不变的情况下，减小占用的版图空间，并大大降低漏电流。
图4是本申请第三实施例静电保护电路应用示意图。请参阅图4，在第三实施例中，所述静电脉冲检测电路201包括电容C1及二极管组D1。所述电容C1具有第一端及第二端，所述电容C1的第一端作为所述静电脉冲检测电路201的上端，即所述电容C1的第一端与所述第一焊垫VDD电连接。所述二极管组D1具有第一端及第二端，所述二极管组D1的第一端作为所述静电脉冲检测电路201的下端，即所述二极管组D1的第一端与所述第二焊垫VSS电连接。所述二极管组D1的第二端及所述电容C1的第二端共同作为所述静电脉冲检测电路201的输出端，即所述二极管组D1的第二端及所述电容C1的第二端共同与所述静电泻放晶体管Mesd的控制端和衬底端电连接。
在第三实施例中，所述二极管组D1相当于第一实施例中的电阻R1，但是， 与第一实施例的电阻R1相比，所述二极管组D1占用版图空间非常小，且其等效电阻值大大提高，从而可以使用非常小的电容C1就能够形成等效RC电路。即本申请第三实施例能够在保持RC时间常数不变的情况下，大大减小占用的版图空间，且大大降低电容值，在静电发生的时间内静电泻放晶体管Mesd能够充分泄放静电电荷，同时，也减小了漏电电流，提高半导体器件的可靠性。
其中，所述二极管组D1由若干个二极管串联而成，例如，在本实施例中，所述二极管组D1由二极管D11及二极管D22串联而成。在本申请其他实施例中，也可根据所述静电泻放晶体管Mesd的控制端对电压的要求而采用其他数量的二极管串联形成所述二极管组D1，本申请对此不进行限制。
在第三实施例中，当第一焊垫VDD产生静电，即在PS模式(PS mode)静电发生的时，静电泻放晶体管Mesd控制端为高电平，静电泻放晶体管Mesd导通，静电电荷流经静电泻放晶体管Mesd，从而泄放静电电荷，实现内部电路20的PS mode的静电保护，避免内部电路20受到静电损伤。当第二焊垫VSS产生静电，即NS模式(NS mode)静电发生时，静电泻放晶体管Mesd关闭，经静电泻放晶体管Mesd所形成的寄生二极管泄放静电电荷，实现内部电路20的NS mode的静电保护，避免内部电路20受到静电损伤。
本申请还提供一第四实施例，所述第四实施例与第三实施例的区别在于，所述静电脉冲检测电路201的电容与二极管器件的连接方法不同。具体地说，请参阅图5，其为本申请第四实施例静电保护电路应用示意图，在该实施例中，所述静电脉冲检测电路201包括二极管组D1、电容C1及反相器P1。
所述二极管组D1具有第一端及第二端，所述二极管组D1的第二端作为所述静电脉冲检测电路201的上端，即所述二极管组D1的第二端与所述第一焊垫VDD电连接。所述电容C1具有第一端及第二端，所述电容C1的第一端作为所述静电脉冲检测电路201的下端，即所述电容C1的第一端与所述第二焊垫VSS电连接。所述反相器P1具有输入端及输出端，所述二极管组D1的第一端及所述电容C1的第二端与所述反相器P1的输入端电连接，所述反相器P1的输出端作为所述静电脉冲检测电路201的输出端，即所述反相器P 1的输出端与所述静电泻放晶体管Mesd的控制端和衬底端电连接。
在第四实施例中，所述二极管组D1相当于第二实施例中的电阻R1，但是， 与第二实施例的电阻R1相比，所述二极管组D1占用版图空间非常小，且其等效电阻值大大提高，从而可以使用非常小的电容C1就能够形成等效RC电路。即本申请第四实施例能够在保持RC时间常数不变的情况下，大大减小占用的版图空间，且大大降低电容值，在静电发生的时间内静电泻放晶体管Mesd能够充分泄放静电电荷，同时，也减小了漏电电流，提高半导体器件的可靠性。
其中，所述二极管组D1由若干个二极管串联而成，例如，在本实施例中，所述二极管组D1由二极管D11及二极管D22串联而成。在本申请其他实施例中，也可根据所述静电泻放晶体管Mesd的控制端对电压的要求而采用其他数量的二极管串联形成所述二极管组D1，本申请对此不进行限制。
在第四实施例中，当第一焊垫VDD产生静电，即在PS模式(PS mode)静电发生的时，静电泻放晶体管Mesd控制端为高电平，静电泻放晶体管Mesd导通，静电电荷流经静电泻放晶体管Mesd，从而泄放静电电荷，实现内部电路20的PS mode的静电保护，避免内部电路20受到静电损伤。当第二焊垫VSS产生静电，即NS模式(NS mode)静电发生时，静电泻放晶体管Mesd关闭，经静电泻放晶体管Mesd所形成的寄生二极管泄放静电电荷，实现内部电路20的NS mode的静电保护，避免内部电路20受到静电损伤。
在第三实施例及第四实施例中，所述二极管组D1可由至少一个二极管串联而成，而在本申请其他实施例中，所述二极管组的二极管由栅极与漏极短接的晶体管构成。请参阅图6，其为本申请第五实施例静电保护电路应用示意图，第五实施例与第三实施例的区别在于，所述二极管组D1的二极管由栅极与漏极短接的晶体管构成。具体地说，在第五实施例中，栅极与漏极短接的晶体管M1及栅极与漏极短接的晶体管M2串联构成二极管组D1。栅极与漏极短接的晶体管能够工作在饱和区，因此，其相当于一个二极管。
而在本申请其他实施例中，也可根据所述静电泻放晶体管Mesd的控制端对电压的要求而采用其他数量的栅极与漏极短接的晶体管串联形成所述二极管组D1，本申请对此不进行限制。
在第五实施例中，工作于饱和区域的晶体管M1及晶体管M2串联，等效于一个阻值较大的电阻，从而可用小的电容就能够形成等效RC电路，即本实施例能够在保持RC时间常数不变(即在静电发生的时间内静电泻放晶体管 Mesd能够充分泄放静电电荷)的情况下，相较于第一实施例，占用版图空间大大减小，使得总体布局面积可大大缩小，同时，形成大电阻小电容的模式，大大降低了漏电流。
在第五实施例中，形成所述二极管组D1的晶体管的导电类型相同，例如所述晶体管M1及晶体管M2均为NMOS晶体管，或者所述晶体管M1及晶体管M2均为PMOS晶体管。在本申请其他实施例中，形成所述二极管组D1的晶体管导电类型不同。例如，所述二极管组D1由一个或多个栅极与漏极短接的NMOS晶体管及一个或多个栅极与漏极短接的PMOS晶体管串联而成。
本申请还提供一第六实施例，所述第六实施例与第五实施例的区别在于，所述静电脉冲检测电路201的电容与二极管组的连接方法不同。具体地说，请参阅图7，其为本申请第六实施例静电保护电路应用示意图，在该实施例中，所述静电脉冲检测电路201包括二极管组D1、电容C1及反相器P1。所述二极管组D1由栅极与漏极短接的晶体管串联构成。具体地说，在第六实施例中，栅极与漏极短接的晶体管M1及栅极与漏极短接的晶体管M2串联构成二极管组D1。
所述二极管组D1具有第一端及第二端，所述二极管组D1的第二端作为所述静电脉冲检测电路201的上端，即所述二极管组D1的第二端与所述第一焊垫VDD电连接。所述电容C1具有第一端及第二端，所述电容C1的第一端作为所述静电脉冲检测电路201的下端，即所述电容C1的第一端与所述第二焊垫VSS电连接。所述反相器P1具有输入端及输出端，所述二极管组D1的第一端及所述电容C1的第二端与所述反相器P1的输入端电连接，所述反相器P1的输出端作为所述静电脉冲检测电路201的输出端，即所述反相器P1的输出端与所述静电泻放晶体管Mesd的控制端和衬底端电连接。本申请静电保护电路能够避免静电保护电路的误启动，且能够增加延时时间，以使静电泻放晶体管Mesd充分泻放静电电荷；另外，本申请静电保护电路还能够大大减小占用的版图空间，降低漏电流，提高半导体器件的可靠性。
本申请还提供一种半导体器件，其采用上述的静电保护电路。本申请半导体器件能够避免静电保护电路误启动，且利用静电脉冲检测电路增加延时时间，以使静电泻放晶体管充分泻放静电电荷，提高半导体器件的可靠性。
图8是本申请第七实施例半导体器件的形成所述静电泻放晶体管的半导体结构的俯视示意图。请参阅图8，形成所述静电泻放晶体管的半导体结构包括：半导体衬底700、阱区710、源极区720、漏极区730、栅极740。
所述半导体衬底700可以为单晶硅衬底、Ge衬底、SiGe衬底、SOI或GOI等。可根据器件的实际需求，可以选择合适的半导体材料作为所述半导体衬底700，在此不作限定。其中，在所述半导体衬底700中设置有若干个连接垫709。
所述阱区710设置于所述半导体衬底700内。在本实施例中，所述静电泻放晶体管为NMOS晶体管，则所述阱区为P型区，在本申请其他实施例中，所述静电泻放晶体管为PMOS晶体管，则所述阱区710也可为N型区。
源极区720与漏极区730交替间隔排布设置在所述阱区710内。在本实施例中，由于所述阱区710为P型区，则所述源极区720与漏极区730为N型区，而在本申请其他实施例中，所述阱区710为N型区，则所述源极区720与漏极区730为P型区。
所述栅极740设置在所述半导体衬底700上，且位于所述源极区720与漏极区730之间，所述栅极740与所述半导体衬底700电连接。具体地说，所述栅极740通过连接垫749与所述半导体衬底700的连接垫709电连接，以实现所述栅极740与所述半导体衬底700的电连接，即所述静电泻放晶体管的控制端与衬底端电连接。
在本实施例中，所述半导体结构包括一个源极区720、一个漏极区730及一个栅极740，而在本申请其他实施例中，所述半导体结构包括多个源极区720、多个漏极区730及多个栅极740。
图9是本申请第八实施例半导体器件的形成所述静电泻放晶体管的半导体结构的俯视示意图，请参阅图9，在本实施例中，所述半导体结构包括第一源极区721、第二源极区722、第一漏极区731、第一栅极741及第二栅极742。所述第一漏极731区位于所述第一源极区721与第二源极区722之间，所述第一栅极741位于所述第一源极区721与第一漏极区731之间，所述第二栅极742位于第一漏极区731与第二源极区722之间。在该实施例中，所述第一漏极区731作为共用漏极区使用。所述第一栅极741及所述第二栅极742的连接垫749与半导体衬底700的连接垫709电连接，以使得所述第一栅极741及所述第二 栅极742与半导体衬底700电连接，即所述静电泻放晶体管的控制端与衬底端电连接。图10是本申请第九实施例半导体器件的形成所述静电泻放晶体管的半导体结构的俯视示意图，请参阅图10，在本实施例中，所述半导体结构包括多个源极区、多个漏极区及多个栅极，所述多个源极区与多个漏极区交替间隔排布，相邻的两个源极区及漏极区之间设置有一所述栅极。
具体地说，在本实施例中，所述半导体结构包括第一源极区721、第二源极区722、第一漏极区731、第二漏极区732、第一栅极741及第二栅极742、第三栅极743。第一源极区721、第一漏极区731、第二源极区722、第二漏极区732交替间隔排布。第一栅极设置在第一源极区721与第一漏极区731之间，第二栅极742设置在第一漏极区731与第二源极区722之间，第三栅极743设置在第二源极区722与第二漏极区732之间。以理解的是，在本申请其他实施例中，也可依据上述排布规则设置多个源极区、多个漏极区及多个栅极，此处不再赘述。下面以图9所示结构为例，说明本申请静电保护电路能够增强静电电荷泻放能力的原理。请参阅图11，其为图9所示结构的截面原理示意图，静电泻放晶体管的第一栅极741、第二栅极742及阱区710三者短接，即图2所示的静电泻放晶体管Mesd的控制端与衬底端短接，并均连接至静电脉冲检测电路201的输出端，则静电泻放晶体管Mesd的控制端与衬底端等电位。与常规的控制端及衬底端未短接的静电泻放晶体管相比，本申请静电泻放晶体管Mesd抬高了衬底端的电位，使得静电泻放晶体管Mesd的阈值电压减小，沟道导通能力增强。当有静电电荷产生时，静电电荷能够快速经静电泻放晶体管Mesd泻放，大大增强了静电保护电路的静电电荷泻放能力。
以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (16)

  1. 一种静电保护电路，与第一焊垫及第二焊垫电连接，包括：
    静电泻放晶体管，具有控制端、第一端、第二端、衬底端，所述第一端电连接至所述第一焊垫，所述第二端电连接至所述第二焊垫；
    静电脉冲检测电路，具有上端、下端、输出端，所述上端电连接至所述第一焊垫，所述下端电连接至所述第二焊垫，所述输出端电连接至所述控制端和所述衬底端。
  2. 根据权利要求1所述的静电保护电路，其中，所述静电泻放晶体管为NMOS晶体管。
  3. 根据权利要求1所述的静电保护电路，其中，所述静电脉冲检测电路包括：
    电容，具有第一端及第二端，所述电容的第一端作为所述静电脉冲检测电路的上端；
    电阻，具有第一端及第二端，所述电阻的第一端作为所述静电脉冲检测电路的下端，所述电阻的第二端及所述电容的第二端共同作为所述静电脉冲检测电路的输出端。
  4. 根据权利要求1所述的静电保护电路，其中，所述静电脉冲检测电路包括：
    电阻，具有第一端及第二端，所述电阻的第一端作为所述静电脉冲检测电路的上端；
    电容，具有第一端及第二端，所述电容的第一端作为所述静电脉冲检测电路的下端；
    反相器，具有输入端及输出端，所述电阻的第二端及所述电容的第二端与所述反相器的输入端电连接，所述反相器的输出端作为所述静电脉冲检测电路的输出端。
  5. 根据权利要求1所述的静电保护电路，其中，所述静电脉冲检测电路包括：
    电容，具有第一端及第二端，所述电容的第一端作为所述静电脉冲检测电路的上端；
    二极管组，具有第一端及第二端，所述二极管组的第一端作为所述静电脉冲检测电路的下端，所述二极管组的第二端及所述电容的第二端共同作为所述静电脉冲检测电路的输出端。
  6. 根据权利要求1所述的静电保护电路，其中，所述静电脉冲检测电路包括：
    二极管组，具有第一端及第二端，所述二极管组的第一端作为所述静电脉冲检测电路的上端；
    电容，具有第一端及第二端，所述电容的第一端作为所述静电脉冲检测电路的下端；
    反相器，具有输入端及输出端，所述二极管组的第一端及所述电容的第二端与所述反相器的输入端电连接，所述反相器的输出端作为所述静电脉冲检测电路的输出端。
  7. 根据权利要求5所述的静电保护电路，其中，所述二极管组由若干个二极管串联而成。
  8. 根据权利要求7所述的静电保护电路，其中，所述二极管由栅极与漏极短接的晶体管构成。
  9. 根据权利要求8所述的静电保护电路，其中，所述晶体管为NMOS晶体管或PMOS晶体管。
  10. 根据权利要求9所述的静电保护电路，其中，所述二极管组由至少一栅极与漏极短接的NMOS晶体管及至少一栅极与漏极短接的PMOS晶体管串联而成。
  11. 根据权利要求1所述的静电保护电路，其中，所述第一焊垫连接电源，所述第二焊垫接地。
  12. 一种半导体器件，包括静电保护电路，所述静电保护电路与第一焊垫及第二焊垫电连接，所述静电保护电路包括：
    静电泻放晶体管，具有控制端、第一端、第二端、衬底端，所述第一端电连接至所述第一焊垫，所述第二端电连接至所述第二焊垫；
    静电脉冲检测电路，具有上端、下端、输出端，所述上端电连接至所述第一焊垫，所述下端电连接至所述第二焊垫，所述输出端电连接至所述控制端和所述衬底端。
  13. 根据权利要求12所述的半导体器件，其中，形成所述静电泻放晶体管的半导体结构包括：
    半导体衬底；
    阱区，设置于所述半导体衬底内；
    交替间隔排布的源极区与漏极区，设置在所述阱区内；
    栅极，设置在所述半导体衬底上，且位于所述源极区与漏极区之间，所述栅极与所述半导体衬底电连接。
  14. 根据权利要求13所述的半导体器件，其中，所述阱区为P型区，所述源极区及所述漏极区为N型区。
  15. 根据权利要求13所述的半导体器件，所述半导体结构还包括第一源极区、第二源极区、第一漏极区、第一栅极及第二栅极，所述第一漏极区位于所述第一源极区与第二源极区之间，所述第一栅极位于所述第一源极区与第一漏极区之间，所述第二栅极位于第一漏极区与第二源极区之间。
  16. 根据权利要求13所述的半导体器件，所述半导体结构还包括多个源极区、多个漏极区及多个栅极，所述多个源极区与多个漏极区交替间隔排布，相邻的两个源极区及漏极区之间设置有一所述栅极。
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