WO2022134606A1 - 静电保护结构、静电保护电路、芯片 - Google Patents

静电保护结构、静电保护电路、芯片 Download PDF

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Publication number
WO2022134606A1
WO2022134606A1 PCT/CN2021/111532 CN2021111532W WO2022134606A1 WO 2022134606 A1 WO2022134606 A1 WO 2022134606A1 CN 2021111532 W CN2021111532 W CN 2021111532W WO 2022134606 A1 WO2022134606 A1 WO 2022134606A1
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Prior art keywords
electrostatic protection
type
terminal
type well
signal terminal
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PCT/CN2021/111532
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English (en)
French (fr)
Inventor
许杞安
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长鑫存储技术有限公司
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Priority to US17/451,670 priority Critical patent/US20230040542A1/en
Publication of WO2022134606A1 publication Critical patent/WO2022134606A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular, to an electrostatic protection structure, an electrostatic protection circuit, and a chip.
  • the chip generally needs to be provided with an electrostatic protection circuit ESD (Electro-Static discharge).
  • ESD Electro-Static discharge
  • the electrostatic protection circuit is used to discharge the static electricity in the chip to prevent the core circuit in the chip from being damaged by static electricity.
  • electrostatic protection structures include components such as MOS transistors, diodes, and thyristors.
  • the trigger voltage of the electrostatic protection structure in the related art is relatively high, that is, the electrostatic protection structure in the related art cannot be triggered in time at a lower electrostatic voltage to discharge static electricity.
  • an electrostatic protection structure includes: a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doping portion, and a first P-type doping part, a second N-type doped part, and a second P-type doped part.
  • the semiconductor substrate includes a first integration region; a first N-type well is located in the first integration region; a first P-type well is located in the first integration region and is arranged adjacent to the first N-type well; a first The N-type doping part is located in the first N-type well; the first P-type doping part is located in the first N-type well, and the first P-type doping part is located in the first N-type doping part
  • the impurity portion is close to one side of the first P-type well; the second N-type impurity portion is located in the first P-type well; the second P-type impurity portion is located away from the second N-type impurity portion. one side of the first N-type well; wherein, the first N-type doped portion is electrically connected to the second P-type doped portion.
  • an electrostatic protection circuit includes at least one electrostatic protection unit, the electrostatic protection unit includes: a thyristor, a first diode, and a second diode.
  • the thyristor includes: a PNP-type triode and an NPN-type triode, the emitter of the PNP-type triode forms the anode of the thyristor, the base is connected to the first node, and the collector is connected to the second node; the collector of the NPN-type triode is connected to the first node , the base is connected to the first node and the second node, and the emitter forms the cathode of the thyristor; the anode of the first diode is connected to the anode of the thyristor, and the cathode of the first diode is connected to the thyristor. the first node; the anode of the second diode is connected to the first node, and the
  • a chip including the above-mentioned electrostatic protection structure.
  • a chip including the above-mentioned electrostatic protection circuit.
  • FIG. 1 is a schematic structural diagram of an exemplary embodiment of an electrostatic protection circuit of the disclosure
  • FIG. 2 is a schematic structural diagram of another exemplary embodiment of an electrostatic protection circuit of the present disclosure
  • FIG. 3 is a schematic structural diagram of another exemplary embodiment of the disclosed electrostatic protection structure
  • FIG. 4 is a schematic structural diagram of an exemplary embodiment of the disclosed electrostatic protection structure
  • FIG. 5 is a schematic structural diagram of another exemplary embodiment of an electrostatic protection circuit of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another exemplary embodiment of the disclosed electrostatic protection structure.
  • FIG. 7 is a schematic structural diagram of another exemplary embodiment of an electrostatic protection circuit of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another exemplary embodiment of the disclosed electrostatic protection structure.
  • FIG. 9 is a schematic structural diagram of another exemplary embodiment of an electrostatic protection circuit of the present disclosure.
  • FIG. 10 is a top view of the electrostatic protection structure in FIG. 8;
  • FIG. 11 is a top view of another exemplary embodiment of the disclosed electrostatic protection structure.
  • FIG. 12 is a schematic structural diagram of another exemplary embodiment of the disclosed electrostatic protection structure.
  • FIG. 13 is a schematic structural diagram of an exemplary embodiment of the disclosed chip.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 is a schematic structural diagram of an exemplary embodiment of the electrostatic protection circuit of the present disclosure.
  • the electrostatic protection circuit may include at least one electrostatic protection unit.
  • the electrostatic protection unit may include: a thyristor, a first diode D1, and a second diode D2.
  • the thyristor may include: a PNP-type triode Q1, an NPN-type triode Q2, the emitter of the PNP-type triode Q1 forms the anode 1 of the thyristor, the base is connected to the first node N1, and the collector is connected to the second node N2; The collector is connected to the first node N1, the base is connected to the first node N1 and the second node N2, the emitter forms the cathode 2 of the thyristor; the anode of the first diode D1 is connected to the thyristor Anode 1, the cathode of the first diode D1 is connected to the first node N1; the anode of the second diode D2 is connected to the first node N1, and the cathode of the second diode D2 is connected to the first node N1 The cathode 2 of the thyristor.
  • the anode 1 may be connected to the first signal terminal, and the cathode may be connected to the second signal terminal.
  • the first diode D1 and the second diode D2 can be turned on first, because the first diode D1 There is a voltage drop itself, and a potential difference will be generated between the anode 1 and the first node N1. Under the action of the potential difference between the anode 1 and the first node N1, the PNP transistor Q1 is turned on.
  • the NPN transistor Q2 is turned on.
  • the conductive NPN transistor Q2 and the PNP transistor Q1 form a positive feedback circuit, so that the electrostatic protection circuit can quickly discharge the static electricity on the first signal terminal to the second signal terminal.
  • the thyristor can be triggered, and the thyristor can quickly pass a large current, thereby rapidly releasing static electricity. Because the turn-on voltage required to turn the diode on first is lower, it has a lower trigger voltage.
  • the anode of the thyristor in the electrostatic protection circuit forms the anode of the electrostatic protection unit
  • the cathode of the thyristor in the electrostatic protection circuit forms the cathode of the electrostatic protection unit.
  • the electrostatic protection circuit may include a plurality of the electrostatic protection units, the multiple electrostatic protection units may be connected in series, and in two adjacent electrostatic protection units, the anode of one electrostatic protection unit and the other electrostatic protection unit Cathode connection of the unit. Multiple electrostatic protection units connected in series can increase the maintenance voltage of the electrostatic protection circuit. When the maintenance voltage of the electrostatic protection circuit is greater than the power supply voltage of the protected circuit, the electrostatic protection circuit will not be latched.
  • FIG. 2 it is a schematic structural diagram of another exemplary embodiment of an electrostatic protection circuit of the present disclosure.
  • the electrostatic protection circuit includes two electrostatic protection units 01 and 02 , and the cathode of the electrostatic protection unit 01 can be connected to the anode of the electrostatic protection unit 02 .
  • the anode of the electrostatic protection unit 01 can be used to form the anode 1 of the electrostatic protection circuit
  • the cathode of the electrostatic protection unit 02 can be used to form the cathode 2 of the electrostatic protection circuit
  • the anode 1 of the electrostatic protection circuit can be connected to the first signal terminal
  • the cathode 2 can be connected to the second signal terminal.
  • the electrostatic protection circuit can be used to discharge static electricity from the first signal terminal to the second signal terminal.
  • the electrostatic protection circuit may include: a first electrostatic protection unit group 001, a second electrostatic protection unit group 002, a first signal terminal V1, a second signal terminal V2, a third signal terminal V3, and the first electrostatic protection unit group 001 It may include: a first electrostatic protection unit 0011 and a second electrostatic protection unit 0012 .
  • the anode of the first electrostatic protection unit 0011 is connected to the first signal terminal V1; the anode of the second electrostatic protection unit 0012 is connected to the cathode of the first electrostatic protection unit 0011, and the cathode of the second electrostatic protection unit 0012 is connected to the second signal terminal V2;
  • the second electrostatic protection unit group 002 may include: a third electrostatic protection unit 0023 and a fourth electrostatic protection unit 0024 .
  • the anode of the third electrostatic protection unit 0023 is connected to the first signal terminal V1; the anode of the fourth electrostatic protection unit 0024 is connected to the cathode of the third electrostatic protection unit 0023, and the cathode of the fourth electrostatic protection unit 0024 is connected to the third signal terminal V3;
  • the first electrostatic protection unit, the second electrostatic protection unit, the third electrostatic protection unit, and the fourth electrostatic protection unit may have the same structure as the aforementioned electrostatic protection unit.
  • the electrostatic protection circuit shown in FIG. 3 can discharge the static electricity of the first signal terminal V1 to the second signal terminal V2 and/or the third signal terminal V3.
  • the electrostatic protection circuit can be applied to a chip, and the chip can include a signal transmission terminal, a power terminal, and a ground terminal.
  • the first signal terminal of the electrostatic protection circuit may be connected to the power supply terminal, the second signal terminal may be connected to the signal transmission terminal, and the third signal terminal may be connected to the ground terminal; or, the first signal terminal of the electrostatic protection circuit may be connected to the signal transmission terminal.
  • Signal transmission terminal, the second signal terminal is connected to the ground terminal, and the third signal terminal is connected to the power terminal; or, the first signal terminal of the electrostatic protection circuit can be connected to the ground terminal, and the second signal terminal is connected to the signal transmission terminal terminal, and the third signal terminal is connected to the power terminal.
  • the signal transmission end may be a signal output end or a signal input end.
  • the exemplary embodiment further provides an electrostatic protection structure, as shown in FIG. 4 , which is a schematic structural diagram of an exemplary embodiment of the electrostatic protection structure of the present disclosure.
  • the electrostatic protection structure may include: a semiconductor substrate 3, a first N-type well 4, a first P-type well 5, a first N-type doping portion 6, a first P-type doping portion 7, and a second N-type doping portion part 8 and the second P-type doped part 9 .
  • the semiconductor substrate 3 may include a first integration region; the first N-type well 4 may be located in the first integration region; the first P-type well 5 may be located in the first integration region, and is connected with the first N-type well 4 are arranged adjacently; the first N-type doping part 6 may be located in the first N-type well 4; the first P-type doping part 7 may be located in the first N-type well 4, and the first The P-type doping portion 7 is located on the side of the first N-type doping portion 6 close to the first P-type well 5 ; the second N-type doping portion 8 may be located in the first P-type well 5 ; The second P-type doping portion 9 may be located in the first P-type well 5 , and the second P-type doping portion 9 may be located in the second N-type doping portion 8 away from the first N-type well 4 one side; wherein, the first N-type doping portion 6 is electrically connected to the second P-type doping portion 9 .
  • the first P-type doping portion 7 and the first N-type doping portion 6 may be arranged at intervals, and the second P-type doping portion 9 and the second N-type doping portion 8 may be arranged at intervals.
  • the doping concentration of the doped well eg, the first P-type well, the first N-type well
  • the semiconductor substrate may be a P-type semiconductor substrate.
  • the electrostatic protection structure can form the electrostatic protection circuit shown in FIG. 1 .
  • the first P-type doping portion 7 can form the emitter of the PNP-type transistor Q1, the first N-type well 4 can form the base of the PNP-type transistor Q1, and the first P-type well 5 can form the collector of the PNP-type transistor Q1 electrode.
  • the second N-type doping portion 8 can form the emitter of the NPN-type transistor Q2, the first P-type well 5 can form the base of the NPN-type transistor Q2, and the first N-type well 4 can form the collector of the NPN-type transistor Q2.
  • the first N-type well 4 and the first P-type doping portion 7 may form a first diode D1, and the first P-type well 5 and the second N-type doping portion 8 may form a second diode D2.
  • the first N-type well 4 itself may also have a resistance R1
  • the first P-type well 5 itself may also have a resistance R2 .
  • FIG. 5 which is a schematic structural diagram of another exemplary embodiment of the electrostatic protection circuit of the present disclosure, considering the resistances of the first N-type well 4 and the first P-type well 5 , the The electrostatic protection circuit corresponding to the electrostatic protection structure can also be represented as shown in FIG. 5 .
  • the electrostatic protection circuit shown in FIG. 5 has the same working principle and technical effect as the electrostatic protection structure shown in FIG. 1 .
  • FIG. 6 it is a schematic structural diagram of another exemplary embodiment of the electrostatic protection structure of the present disclosure.
  • the semiconductor substrate may further include a second integration region, the first integration region and the second integration region are spaced apart, and the electrostatic protection structure may further include: a second N-type well 10 and a second P-type well 11.
  • a third N-type doped portion 12 a third P-type doped portion 13 , a fourth N-type doped portion 14 , and a fourth P-type doped portion 15 .
  • the second N-type well 10 is located in the second integration region;
  • the second P-type well 11 is located in the second integration region, and is disposed adjacent to the second N-type well 10 .
  • the third N-type doping portion 12 is located in the second N-type well 10 ; the third P-type doping portion 13 is located in the second N-type well 10 , and the third P-type doping portion 13 is located in The third N-type doping portion 12 is close to one side of the second P-type well 11 ; the fourth N-type doping portion 14 is located in the second P-type well 11 ; the fourth P-type doping portion 15 is located in the second P-type well 11, and the fourth P-type doping portion 15 is located on the side of the fourth N-type doping portion 14 away from the second N-type well 10; wherein the third The N-type doping portion 12 is electrically connected to the fourth P-type doping portion 15 , and the second N-type doping portion 8 is electrically connected to the third P-type doping portion 13 .
  • the doping concentration of the doped well may be smaller than the doping concentration of the doped portion.
  • the fourth N-type doping portion 14 and the fourth P-type doping portion 15 are arranged at intervals, and the third N-type doping portion 12 and the third P-type doping portion 13 are arranged at intervals.
  • the electrostatic protection structure can form the electrostatic protection circuit shown in FIG. 2 .
  • the first P-type well 5, the first N-type well 4, the first N-type doping part 6, the first P-type doping part 7, the second N-type doping part 8, the first N-type doping part 8, the The two P-type doping parts 9 can form the electrostatic protection unit 01 in FIG. 2 .
  • the second N-type well 10 , the second P-type well 11 , the third N-type doping portion 12 , the third P-type doping portion 13 , the fourth N-type doping portion 14 , and the fourth P-type doping portion 15 may be The electrostatic protection unit 02 in FIG. 2 is formed.
  • the manner in which the electrostatic protection structure shown in FIG. 6 forms the electrostatic protection circuit has been described in detail in the above content, and will not be repeated here.
  • the second N-type well 10 itself may also have a resistance R3
  • the second P-type well 11 itself may also have a resistance R4 .
  • FIG. 7 which is a schematic structural diagram of another exemplary embodiment of the electrostatic protection circuit of the present disclosure, considering the resistances of the second N-type well 10 and the second P-type well 11 , as shown in FIG. 6
  • the electrostatic protection circuit corresponding to the electrostatic protection structure can also be represented as shown in FIG. 7 .
  • the electrostatic protection circuit shown in FIG. 7 has the same working principle and technical effect as the electrostatic protection structure shown in FIG. 2 .
  • FIG. 8 it is a schematic structural diagram of another exemplary embodiment of the electrostatic protection structure of the present disclosure.
  • the electrostatic protection structure may further include: a third P-type well 16, a fifth P-type doping portion 17, a fifth N-type doping portion 18, a sixth P-type doping portion 19, a fourth P-type well 20, The seventh P-type doping portion 21 , the sixth N-type doping portion 22 , and the eighth P-type doping portion 23 .
  • the third P-type well 16 is located in the first integration region, and is located on the side of the first N-type well 4 away from the first P-type well 5 , and the third P-type well 16 is connected to the first P-type well 5 .
  • the N-type wells 4 are arranged adjacently; the fifth P-type doping portion 17 is located in the first N-type well 4 , and the fifth P-type doping portion 17 is located away from the first N-type doping portion 6
  • the side of the first N-type doping part 17 away from the first N-type doping part 6; the sixth P-type doping part 19 is located in the third P-type well 16, and the sixth P-type doping part 19 It is located on the side of the fifth N-type doping portion 18 away from the first N-type well 4 ; wherein the first N-type doping portion 6 is electrically connected to the sixth P-type doping portion 19 .
  • the fourth P-type well 20 is located in the second integration region, and the fourth P-type well 20 is located on the side of the second N-type well 10 away from the second P-type well 11 .
  • the well 20 is disposed adjacent to the second N-type well 10; the seventh P-type doping portion 21 is located in the second N-type well 10, and the seventh P-type doping portion 21 is located in the second N-type well 10.
  • the third N-type doping portion 12 is on one side away from the third P-type doping portion 13 ; the sixth N-type doping portion 22 is located in the fourth P-type well 20 , and the sixth N-type doping portion 22
  • the part 22 is located on the side of the seventh P-type doping part 21 away from the third N-type doping part 12; the eighth P-type doping part 23 is located in the fourth P-type well 20, and the The eighth P-type doping portion 23 is located on the side of the sixth N-type doping portion 22 away from the second N-type well 10 ; wherein the third N-type doping portion 12 and the eighth P-type doping portion 23
  • the type doped portion 23 is electrically connected, and the fifth N-type doped portion 18 is electrically connected to the seventh P-type doped portion 21 .
  • the doping concentration of the doped well may be smaller than the doping concentration of the doped portion.
  • the fifth P-type doping portion 17 is spaced apart from the first N-type doping portion 6
  • the fifth N-type doping portion 18 and the sixth P-type doping portion 19 are spaced apart
  • the seventh P-type doping portion 21 is spaced from the first N-type doping portion 18 .
  • the three N-type doping portions 12 are arranged at intervals
  • the sixth N-type doping portion 22 and the eighth P-type doping portion 23 are arranged at intervals.
  • the fifth P-type doping portion 17 and the first N-type well 4 form a diode D5
  • the fifth P-type doping portion 17 forms the emitter of the PNP-type triode Q5
  • the first N-type well 4 forms the base of the PNP transistor Q5
  • the third P-well 16 forms the collector of the PNP transistor Q5.
  • the fifth N-type doped portion 18 and the third P-type well 16 form the diode D6
  • the fifth N-type doped portion 18 forms the emitter of the NPN-type transistor Q6
  • the third P-type well 16 forms the NPN-type transistor Q6.
  • the base, the first N-well 4 forms the collector of the NPN transistor Q6.
  • the seventh P-type doped portion 21 and the second N-type well 10 form a diode D7
  • the seventh P-type doped portion 21 forms the emitter of the PNP-type transistor Q7
  • the second N-type well forms the base of the PNP-type transistor Q7
  • the third P-type well 20 forms the collector of the PNP-type transistor Q7.
  • the sixth N-type doped portion 22 and the third P-type well 20 form a diode D8, the sixth N-type doped portion 22 forms the emitter of the NPN-type transistor Q8, and the third P-type well 20 forms the base of the NPN-type transistor Q8 , the second N-type well 10 forms the collector of the NPN-type transistor Q8.
  • the electrostatic protection structure may further include a first signal terminal V1, a second signal terminal V2, and a third signal terminal V3.
  • the first P-type doping part 7 and the fifth P-type doping part 17 can be used for connecting the first signal terminal V1 of the electrostatic protection structure
  • the fourth N-type doping part 14 can be used for connecting the second signal of the electrostatic protection structure
  • the terminal V2, the sixth N-type doping portion 22 can be used for connecting to the third signal terminal V3 of the electrostatic protection structure.
  • the electrostatic protection structure not only has smaller trigger voltage, faster trigger speed, and higher maintenance voltage, but also has smaller area and lower capacitance.
  • the diodes connected in series can reduce the leakage of the chip during normal operation. current.
  • the electrostatic protection structure can be applied to a chip, and the chip can include a signal transmission terminal, a power terminal, and a ground terminal.
  • the first signal terminal of the electrostatic protection structure may be connected to the power supply terminal, the second signal terminal may be connected to the signal transmission terminal, and the third signal terminal may be connected to the ground terminal; or, the first signal terminal of the electrostatic protection structure may be connected to the signal transmission terminal.
  • Signal transmission terminal, the second signal terminal is connected to the ground terminal, and the third signal terminal is connected to the power terminal; or, the first signal terminal of the electrostatic protection structure can be connected to the ground terminal, and the second signal terminal is connected to the signal transmission terminal terminal, and the third signal terminal is connected to the power terminal.
  • the signal transmission end may be a signal output end or a signal input end.
  • the first N-type well 4 itself may also have a resistance R5
  • the third P-type well 16 itself may also have a resistance R6
  • the second N-type well 10 itself may also have a resistance R7
  • the third P-type well 10 itself may also have a resistance R7.
  • the well 20 itself may also have a resistor R8.
  • FIG. 9 which is a schematic structural diagram of another exemplary embodiment of the electrostatic protection circuit of the present disclosure
  • the resistance of the doping well itself is doped, and the electrostatic protection circuit corresponding to the electrostatic protection structure shown in FIG. 8 can also be expressed as as shown in Figure 9.
  • the electrostatic protection circuit shown in FIG. 9 has the same working principle and technical effect as the electrostatic protection structure shown in FIG. 3 .
  • the first N-type well 4 may be formed in the annular P-type well 24 , part of the P-type well 24 may form the first P-type well 5 , and part of the P-type well 24 may form the third P-type well 16 .
  • the second N-type well 10 may be formed in the annular P-type well 25 , part of the P-type well 25 may form the second P-type well 11 , and part of the P-type well 25 may form the fourth P-type well 20 .
  • FIG. 11 it is a top view of another exemplary embodiment of the electrostatic protection structure of the present disclosure.
  • the first P-type doping portion 7 and the fifth P-type doping portion 17 may form a ring-shaped doping portion surrounding the first N-type doping portion 6 with other P-type doping portions.
  • the ring-shaped doping portion can increase the effective area of the bases of the transistors Q1 and Q5, and at the same time increase the diffusion coefficients of the first P-type doping portion 7 and the fifth P-type doping portion 17 serving as the emitters, thereby amplifying the current through the triode The influence of the coefficient increases the maintenance voltage of the electrostatic protection structure.
  • the electrostatic protection structure may further include: a first N-type deep well 26, the first N-type deep well 26 is formed in the semiconductor substrate 3, the first N-type deep well 26 has a groove structure, the The first N-type well 4 , the first P-type well 5 and the third P-type well 16 are located in the grooves formed by the first N-type deep well 26 .
  • the electrostatic protection structure may further include: a second N-type deep well 27, the second N-type deep well 27 is formed in the semiconductor substrate, the second N-type deep well 27 is a groove structure, and the second N-type deep well 27 is a groove structure.
  • the two N-type wells 10 , the second P-type well 11 and the fourth P-type well 20 are located in the grooves formed by the second N-type deep well 27 .
  • the first N-type deep well 26 can shield the components in the first N-type well 4 , the first P-type well 5 , and the third P-type well 16 from noise, and at the same time can prevent the components from lining the P-type semiconductor substrate. Bottom leakage.
  • the second N-type deep well 27 can shield the components in the second N-type well 10 , the second P-type well 11 , and the fourth P-type well 20 from noise, and at the same time can prevent the components Leakage to the P-type semiconductor substrate.
  • the first N-type deep well 26 may be located in the first integration region
  • the second N-type deep well 27 may be located in the second integration region.
  • the electrostatic protection structure further includes: a ninth P-type doping part 28 , the ninth P-type doping part 28 may be located in the semiconductor substrate, and the The ninth P-type doping portion 28 may be located outside the first integration region and the second integration region; wherein, the ninth P-type doping portion 28 may be connected to the ground terminal VSS.
  • the ninth P-type doping portion 28 may be used to ground the semiconductor substrate 3 .
  • the ground terminal VSS can be understood as the ground terminal of the chip where the electrostatic protection structure is located.
  • the present exemplary embodiment also provides a chip including the above electrostatic protection structure.
  • the chip includes a power supply terminal, a ground terminal, and a signal transmission terminal
  • the chip includes a plurality of the electrostatic protection structures
  • the multiple electrostatic protection structures include: a first electrostatic protection structure, a second electrostatic protection structure, and a second electrostatic protection structure.
  • the electrostatic protection structure and the third electrostatic protection structure are examples of electrostatic protection structure.
  • the first signal terminal of the first electrostatic protection structure is connected to the power supply terminal, the second signal terminal is connected to the signal transmission terminal, and the third signal terminal is connected to the ground terminal; the first signal terminal of the second electrostatic protection structure is connected to the signal transmission terminal The second signal terminal is connected to the ground terminal, and the third signal terminal is connected to the power terminal; the first signal terminal of the third electrostatic protection structure is connected to the ground terminal, the second signal terminal is connected to the signal transmission terminal, and the third signal terminal is connected to the power terminal.
  • FIG. 13 it is a schematic structural diagram of an exemplary embodiment of the disclosed chip.
  • the chip may include a core processing circuit 29, a power supply terminal VDD, a ground terminal VSS, a signal input terminal INPUT, and a signal output terminal OUTPUT.
  • the chip may include five electrostatic protection structures shown in FIG. 12 or FIG. 8 .
  • the first signal terminal of the electrostatic protection structure 31 is connected to the power supply terminal VDD
  • the second signal terminal V2 is connected to the signal input terminal INPUT
  • the third signal terminal V3 is connected to the ground terminal VSS
  • the first signal terminal of the electrostatic protection structure 32 is connected to the signal input terminal.
  • the second signal terminal V2 is connected to the ground terminal VSS, the third signal terminal V3 is connected to the power terminal VDD;
  • the first signal terminal of the electrostatic protection structure 33 is connected to the signal output terminal OUTPUT, the second signal terminal V2 is connected to the ground terminal VSS, and the third signal terminal
  • the terminal V3 is connected to the power terminal VDD;
  • the first signal terminal of the electrostatic protection structure 34 is connected to the ground terminal VSS, the second signal terminal V2 is connected to the signal output terminal OUTPUT, and the third signal terminal V3 is connected to the power supply terminal VDD;
  • the first signal of the electrostatic protection structure 35 The terminal is connected to the ground terminal VSS, the second signal terminal V2 is connected to the signal input terminal INPUT, and the third signal terminal V3 is connected to the power terminal VDD.
  • the first signal terminal of the electrostatic protection structure 36 is connected to the power terminal VDD, the second signal terminal V2 is connected to the output terminal OUTPUT, and the third signal terminal V3 is connected to the ground terminal VSS.
  • the chip may be any chip such as a memory chip. It should be understood that, in addition to the signal output end and the signal output end, the chip may also include other signal transmission ends.
  • the present exemplary embodiment also provides a chip including the above-mentioned electrostatic protection circuit.
  • the chip may include a power supply terminal, a ground terminal, and a signal transmission terminal, the chip includes a plurality of the electrostatic protection circuits, and the multiple electrostatic protection circuits include: a first electrostatic protection circuit, a second electrostatic protection circuit, and a second electrostatic protection circuit. The second electrostatic protection circuit, the third electrostatic protection circuit.
  • the first signal terminal of the first electrostatic protection circuit is connected to the power supply terminal, the second signal terminal is connected to the signal transmission terminal, and the third signal terminal is connected to the ground terminal; the first signal terminal of the second electrostatic protection circuit is connected to the Signal transmission terminal, the second signal terminal is connected to the ground terminal, and the third signal terminal is connected to the power terminal; the first signal terminal of the third electrostatic protection circuit is connected to the ground terminal, and the second signal terminal is connected to the signal transmission terminal , the third signal terminal is connected to the power terminal.
  • the chip may include six electrostatic protection circuits shown in FIG. 3 , wherein the connection mode of the six electrostatic protection circuits in the chip may be the same as the connection mode of the electrostatic protection structure in FIG. 13 , which will not be repeated here.

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Abstract

一种静电保护结构、静电保护电路、芯片，静电保护结构包括半导体衬底（3）、第一N型阱（4）、第一P型阱（5）、第一N型掺杂部（6）、第一P型掺杂部（7）、第二N型掺杂部（8）、第二P型掺杂部（9）。半导体衬底（3）包括第一集成区；第一N型阱（4）位于第一集成区；第一P型阱（5）位于第一集成区，且与第一N型阱（4）相邻设置；第一N型掺杂部（6）位于第一N型阱（4）内；第一P型掺杂部（7）位于第一N型阱（4）内，且第一P型掺杂部位（7）于第一N型掺杂部（6）靠近第一P型阱（5）的一侧；第二N型掺杂部（8）位于第一P型阱（5）内；第二P型掺杂部（9）位于第二N型掺杂部（8）远离第一N型阱（4）的一侧；其中，第一N型掺杂部（6）与第二P型掺杂部（9）电连接。静电保护结构具有较小的触发电压。

Description

静电保护结构、静电保护电路、芯片
相关申请的交叉引用
本申请要求于2020年12月23日递交的、名称为《静电保护结构、静电保护电路、芯片》的中国专利申请第202011538427.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及半导体技术领域，尤其涉及一种静电保护结构、静电保护电路、芯片。
背景技术
芯片中一般需要设置有静电保护电路ESD(Electro-Static discharge)，静电保护电路用于释放芯片中的静电以避免芯片中的核心电路在静电作用下损坏。
相关技术中，常用的静电保护结构有MOS管、二极管、晶闸管等元器件。然而，相关技术中的静电保护结构触发电压较高，即相关技术中的静电保护结构不能在较低的静电电压下及时触发以释放静电。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种静电保护结构，该静电保护结构包括：半导体衬底、第一N型阱、第一P型阱、第一N型掺杂部、第一P型掺杂部、第二N型掺杂部、第二P型掺杂部。半导体衬底包括第一集成区；第一N型阱位于所述第一集成区；第一P型阱位于所述第一集成区，且与所述第一N型阱相邻设置；第一N型掺杂部位于所述第一N型阱内；第一P型掺杂部位于所述第一N型阱内，且所述第一P型掺杂部位于所述第一N型掺杂部靠近所述第一P型阱的一侧；第二N型掺杂部位于所述第一P型阱内；第二P型掺杂部位于所述第二N型掺杂部远离所述第一N型阱的一侧；其中，所述第一N型掺杂部与所述第二P型掺杂部电连接。
根据本公开的一个方面，提供一种静电保护电路，该静电保护电路包括至少一个静电保护单元，所述静电保护单元包括：晶闸管、第一二极管、第二二极管。晶闸管包括：PNP型三极管、NPN型三极管，PNP型三极管的发射极形成所述晶闸管的阳极，基极连接第一节点，集电极连接第二节点；NPN型三极管的集电极连接所述第一节点，基极连接所述第一节点和第二节点，发射极形成所述晶闸管的阴极；所述第一二极管的阳极连接所述晶闸管的阳极，所述第一二极管的阴极连接所述第一节点；所述第二二极管的阳极连接所述第一节点，所述第二二极管的阴极连接所述晶闸管的阴极。
根据本公开的一个方面，提供一种芯片，该芯片包括上述的静电保护结构。
根据本公开的一个方面，提供一种芯片，该芯片包括上述的静电保护电路。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开静电保护电路一种示例性实施例中的结构示意图；
图2为本公开静电保护电路另一种示例性实施例的结构示意图；
图3为本公开静电保护结构另一种示例性实施例的结构示意图；
图4为本公开静电保护结构一种示例性实施例的结构示意图；
图5为本公开静电保护电路另一种示例性实施例的结构示意图；
图6为本公开静电保护结构另一种示例性实施例的结构示意图；
图7为本公开静电保护电路另一种示例性实施例的结构示意图；
图8为本公开静电保护结构另一种示例性实施例的结构示意图；
图9为本公开静电保护电路另一种示例性实施例的结构示意图；
图10为图8中静电保护结构的俯视图；
图11为本公开静电保护结构另一种示例性实施例的俯视图；
图12为本公开静电保护结构另一种示例性实施例的结构示意图；
图13为本公开芯片一种示例性实施例的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和 “具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本示例性实施例提供一种静电保护电路，如图1所示，为本公开静电保护电路一种示例性实施例中的结构示意图。该静电保护电路可以包括至少一个静电保护单元，如图1所示，所述静电保护单元可以包括：晶闸管、第一二极管D1、第二二极管D2。晶闸管可以包括：PNP型三极管Q1、NPN型三极管Q2，PNP型三极管Q1的发射极形成所述晶闸管的阳极1，基极连接第一节点N1，集电极连接第二节点N2；NPN型三极管Q2的集电极连接所述第一节点N1，基极连接所述第一节点N1和第二节点N2，发射极形成所述晶闸管的阴极2；所述第一二极管D1的阳极连接所述晶闸管的阳极1，所述第一二极管D1的阴极连接所述第一节点N1；所述第二二极管D2的阳极连接所述第一节点N1，所述第二二极管D2的阴极连接所述晶闸管的阴极2。
在本示例性实施例提供的静电保护电路中，阳极1可以连接第一信号端，阴极可以连接第二信号端。当第一信号端上存在静电，且第一信号端和第二信号端的电位差大于阈值时，第一二极管D1和第二二极管D2可以首先导通，由于第一二极管D1自身存在压降，阳极1和第一节点N1之间会产生电位差，在阳极1和第一节点N1之间的电位差作用下，PNP型三极管Q1导通。同时，由于第二二极管D2自身存在压降，第一节点N1和阴极2之间会产生电位差，在第一节点N1和阴极2之间的电位差作用下，NPN型三极管Q2导通。导通的NPN型三极管Q2和PNP型三极管Q1形成正反馈电路，从而该静电保护电路可以将第一信号端上的静电快速的释放到第二信号端。该静电保护电路中的二极管先导通之后，可以触发晶闸管，由晶闸管快速通过大电流，从而快速释放静电。因为让二极管先导通需要的导通电压较低，所以具有较小的触发电压。
本示例性实施例中，所述静电保护电路中晶闸管的阳极形成该静电保护单元的阳极，所述静电保护电路中晶闸管的阴极形成该静电保护单元的阴极。所述静电保护电路可以包括多个所述静电保护单元，多个所述静电保护单元可以串联连接，且在相邻的两所述静电保护单元中，一个静电保护单元的阳极和另一静电保护单元的阴极连接。串联的多个静电保护单元可以增加静电保护电路的维持电压，当静电保护电路的维持电压大于被保护电路电源电压时，静电保护电路就不会发生闩锁。
如图2所示，为本公开静电保护电路另一种示例性实施例的结构示意图。该静电保护电路包括两个静电保护单元01、02，静电保护单元01的阴极可以连接静电保护单元02的阳极。静电保护单元01的阳极可以用于形成静电保护电路的阳极1，静电保护单元02的阴极可以用于形成静电保护电路的阴极2，静电保护电路的阳极1可以连接第一信号端，静电保护电路的阴极2可以连接第二信号端。该静电保护电路可以用于将第一信号端的静电释放到第二信号端。
如图3所示，为本公开静电保护结构另一种示例性实施例的结构示意图。所述静 电保护电路可以包括：第一静电保护单元组001、第二静电保护单元组002，以及第一信号端V1、第二信号端V2、第三信号端V3，第一静电保护单元组001可以包括：第一静电保护单元0011和第二静电保护单元0012。第一静电保护单元0011的阳极连接第一信号端V1；第二静电保护单元0012的阳极连接所述第一静电保护单元0011的阴极，第二静电保护单元0012的阴极连接第二信号端V2；第二静电保护单元组002可以包括：第三静电保护单元0023、第四静电保护单元0024。第三静电保护单元0023的阳极连接第一信号端V1；第四静电保护单元0024的阳极连接所述第三静电保护单元0023的阴极，第四静电保护单元0024的阴极连接第三信号端V3；其中，所述第一静电保护单元、第二静电保护单元、第三静电保护单元、第四静电保护单元可以与上述的静电保护单元具有相同的结构。图3所示的静电保护电路可以将第一信号端V1的静电向第二信号端V2和/或第三信号端V3释放。其中，该静电保护电路可以应用于一芯片，该芯片可以包括信号传输端、电源端、接地端。静电保护电路的第一信号端可以连接所述电源端，第二信号端连接所述信号传输端，第三信号端连接所述接地端；或，静电保护电路的第一信号端可以连接所述信号传输端，第二信号端连接所述接地端，第三信号端连接所述电源端；或，静电保护电路的第一信号端可以连接所述接地端，第二信号端连接所述信号传输端，第三信号端连接所述电源端。其中，信号传输端可以为信号输出端或信号输入端。
本示例性实施例还提供一种静电保护结构，如图4所示，为本公开静电保护结构一种示例性实施例的结构示意图。该静电保护结构可以包括：半导体衬底3、第一N型阱4、第一P型阱5、第一N型掺杂部6、第一P型掺杂部7、第二N型掺杂部8、第二P型掺杂部9。半导体衬底3可以包括第一集成区；第一N型阱4可以位于所述第一集成区；第一P型阱5可以位于所述第一集成区，且与所述第一N型阱4相邻设置；第一N型掺杂部6可以位于所述第一N型阱4内；第一P型掺杂部7可以位于所述第一N型阱4内，且所述第一P型掺杂部7位于所述第一N型掺杂部6靠近所述第一P型阱5的一侧；第二N型掺杂部8可以位于所述第一P型阱5内；第二P型掺杂部9可以位于所述第一P型阱5内，且第二P型掺杂部9可以位于所述第二N型掺杂部8远离所述第一N型阱4的一侧；其中，第一N型掺杂部6与所述第二P型掺杂部9电连接。第一P型掺杂部7和第一N型掺杂部6可以间隔设置，第二P型掺杂部9和第二N型掺杂部8可以间隔设置。掺杂阱(例如，第一P型阱、第一N型阱)的掺杂浓度可以小于掺杂部(例如，第一N型掺杂部、第一P型掺杂部)的掺杂浓度。所述半导体衬底可以为P型半导体衬底。
如图4所示，该静电保护结构可以形成图1所示的静电保护电路。其中，第一P型掺杂部7可以形成PNP型三极管Q1的发射极，第一N型阱4可以形成PNP型三极管Q1的基极，第一P型阱5可以形成PNP型三极管Q1的集电极。第二N型掺杂部8可以形成NPN型三极管Q2的发射极，第一P型阱5可以形成NPN型三极管Q2的 基极，第一N型阱4可以形成NPN型三极管Q2的集电极。第一N型阱4和第一P型掺杂部7可以形成第一二极管D1，第一P型阱5和第二N型掺杂部8可以形成第二二极管D2。
此外，如图4所示，第一N型阱4自身还可以存在电阻R1，第一P型阱5自身还可以存在电阻R2。相应的，如图5所示，为本公开静电保护电路另一种示例性实施例的结构示意图，考虑到第一N型阱4、第一P型阱5自身的电阻，图4所示的该静电保护结构对应的静电保护电路还可以表示为如图5所示。图5所示的静电保护电路与图1所示的静电保护结构具有相同的工作原理和技术效果。
本示例性实施例中，如图6所示，为本公开静电保护结构另一种示例性实施例的结构示意图。所述半导体衬底还可以包括第二集成区，所述第一集成区和所述第二集成区间隔设置，所述静电保护结构还可以包括：第二N型阱10、第二P型阱11、第三N型掺杂部12、第三P型掺杂部13、第四N型掺杂部14、第四P型掺杂部15。第二N型阱10位于所述第二集成区；第二P型阱11位于所述第二集成区，且与所述第二N型阱10相邻设置。第三N型掺杂部12位于所述第二N型阱10内；第三P型掺杂部13位于所述第二N型阱10内，且所述第三P型掺杂部13位于所述第三N型掺杂部12靠近所述第二P型阱11的一侧；第四N型掺杂部14位于所述第二P型阱11内；第四P型掺杂部15位于所述第二P型阱11内，且第四P型掺杂部15位于所述第四N型掺杂部14远离所述第二N型阱10的一侧；其中，所述第三N型掺杂部12与所述第四P型掺杂部15电连接，所述第二N型掺杂部8与所述第三P型掺杂部13电连接。其中，掺杂阱的掺杂浓度可以小于掺杂部的掺杂浓度。第四N型掺杂部14和第四P型掺杂部15间隔设置，第三N型掺杂部12和第三P型掺杂部13间隔设置。
如图6所示，该静电保护结构可以形成图2所示的静电保护电路。其中，第一集成区中的第一P型阱5、第一N型阱4、第一N型掺杂部6、第一P型掺杂部7、第二N型掺杂部8、第二P型掺杂部9可以形成图2中的静电保护单元01。第二N型阱10、第二P型阱11、第三N型掺杂部12、第三P型掺杂部13、第四N型掺杂部14、第四P型掺杂部15可以形成图2中的静电保护单元02。其中，图6所示静电保护结构形成静电保护电路的方式已在上述内容进行了详细说明，此处不再赘述。
此外，如图6所示，第二N型阱10自身还可以存在电阻R3，第二P型阱11自身还可以存在电阻R4。相应的，如图7所示，为本公开静电保护电路另一种示例性实施例的结构示意图，考虑到第二N型阱10、第二P型阱11自身的电阻，图6所示的该静电保护结构对应的静电保护电路还可以表示为如图7所示。图7所示的静电保护电路与图2所示的静电保护结构具有相同的工作原理和技术效果。
本示例性实施例中，如图8所示，为本公开静电保护结构另一种示例性实施例的结构示意图。所述静电保护结构还可以包括：第三P型阱16、第五P型掺杂部17、第五N型掺杂部18、第六P型掺杂部19、第四P型阱20、第七P型掺杂部21、第六N 型掺杂部22、第八P型掺杂部23。第三P型阱16位于所述第一集成区，且位于所述第一N型阱4远离所述第一P型阱5的一侧，所述第三P型阱16与所述第一N型阱4相邻设置；第五P型掺杂部17位于所述第一N型阱4内，且所述第五P型掺杂部17位于所述第一N型掺杂部6远离所述第一P型掺杂部7的一侧；第五N型掺杂部18位于所述第三P型阱16内，且所述第五N型掺杂部18位于所述第五P型掺杂部17远离所述第一N型掺杂部6的一侧；第六P型掺杂部19位于所述第三P型阱16内，且所述第六P型掺杂部19位于所述第五N型掺杂部18远离所述第一N型阱4的一侧；其中，所述第一N型掺杂部6与所述第六P型掺杂部19电连接。第四P型阱20位于所述第二集成区，且所述第四P型阱20位于所述第二N型阱10远离所述第二P型阱11的一侧，所述第四P型阱20与所述第二N型阱10相邻设置；第七P型掺杂部21位于所述第二N型阱10内，且所述第七P型掺杂部21位于所述第三N型掺杂部12远离所述第三P型掺杂部13的一侧；第六N型掺杂部22位于所述第四P型阱20内，且所述第六N型掺杂部22位于所述第七P型掺杂部21远离所述第三N型掺杂部12的一侧；第八P型掺杂部23位于所述第四P型阱20内，且所述第八P型掺杂部23位于所述第六N型掺杂部22远离所述第二N型阱10的一侧；其中，所述第三N型掺杂部12与所述第八P型掺杂部23电连接，第五N型掺杂部18与第七P型掺杂部21电连接。其中，掺杂阱的掺杂浓度可以小于掺杂部的掺杂浓度。第五P型掺杂部17与第一N型掺杂部6间隔设置，第五N型掺杂部18和第六P型掺杂部19间隔设置，第七P型掺杂部21与第三N型掺杂部12间隔设置，第六N型掺杂部22和第八P型掺杂部23间隔设置。
如图8所示，第五P型掺杂部17与第一N型阱4形成二极管D5，第五P型掺杂部17形成了PNP型三级管Q5的发射极，第一N型阱4形成了PNP型三极管Q5的基极，第三P型阱16形成了PNP型三极管Q5的集电极。第五N型掺杂部18和第三P型阱16形成二极管D6，第五N型掺杂部18形成了NPN型三极管Q6的发射极，第三P型阱16形成了NPN型三极管Q6的基极，第一N型阱4形成了NPN型三极管Q6的集电极。第七P型掺杂部21与第二N型阱10形成二极管D7，第七P型掺杂部21形成PNP型三极管Q7的发射极，第二N型阱形成PNP型三极管Q7的基极，第三P型阱20形成PNP型三极管Q7的集电极。第六N型掺杂部22和第三P型阱20形成二极管D8，第六N型掺杂部22形成NPN型三极管Q8的发射极，第三P型阱20形成NPN型三极管Q8的基极，第二N型阱10形成NPN型三极管Q8的集电极。所述静电保护结构还可以包括第一信号端V1、第二信号端V2、第三信号端V3。第一P型掺杂部7和第五P型掺杂部17可以用于连接静电保护结构的第一信号端V1，第四N型掺杂部14可以用于连接静电保护结构的第二信号端V2，第六N型掺杂部22可以用于连接静电保护结构的第三信号端V3。该静电保护结构不仅具有较小的触发电压、较快的触发速度、较高的维持电压，其还具有较小的面积、较低的电容，此外，串联 的二极管可以降低芯片正常工作时候的漏电流。
该静电保护结构可以应用于一芯片，该芯片可以包括信号传输端、电源端、接地端。静电保护结构的第一信号端可以连接所述电源端，第二信号端连接所述信号传输端，第三信号端连接所述接地端；或，静电保护结构的第一信号端可以连接所述信号传输端，第二信号端连接所述接地端，第三信号端连接所述电源端；或，静电保护结构的第一信号端可以连接所述接地端，第二信号端连接所述信号传输端，第三信号端连接所述电源端。其中，信号传输端可以为信号输出端或信号输入端。
此外，如图8所示，第一N型阱4自身还可以存在电阻R5，第三P型阱16自身还可以存在电阻R6，第二N型阱10自身还可以存在电阻R7，第三P型阱20自身还可以存在电阻R8。相应的，如图9所示，为本公开静电保护电路另一种示例性实施例的结构示意图，掺杂阱自身的电阻，图8所示的该静电保护结构对应的静电保护电路还可以表示为如图9所示。图9所示的静电保护电路与图3所示的静电保护结构具有相同的工作原理和技术效果。
如图10所示，为图8中静电保护结构的俯视图。第一N型阱4可以形成于环形P型阱24内，部分P型阱24可以形成第一P型阱5，部分P型阱24可以形成第三P型阱16。第二N型阱10可以形成于环形P型阱25内，部分P型阱25可以形成第二P型阱11，部分P型阱25可以形成第四P型阱20。
如图11所示，为本公开静电保护结构另一种示例性实施例的俯视图。第一P型掺杂部7和第五P型掺杂部17可以与其他P型掺杂部形成围绕第一N型掺杂部6的环形掺杂部。该环形掺杂部能够增加三极管Q1和Q5基极的有效面积，同时增加了作为发射极的第一P型掺杂部7和第五P型掺杂部17的扩散系数，从而通过三极管电流放大系数的影响，抬高静电保护结构的维持电压。
本示例性实施例中，如图12所示，为本公开静电保护结构另一种示例性实施例的结构示意图。所述静电保护结构还可以包括：第一N型深阱26，第一N型深阱26形成于所述半导体衬底3内，所述第一N型深阱26呈凹槽结构，所述第一N型阱4、第一P型阱5、第三P型阱16位于所述第一N型深阱26形成的凹槽内。所述静电保护结构还可以包括：第二N型深阱27，第二N型深阱27形成于所述半导体衬底内，所述第二N型深阱27呈凹槽结构，所述第二N型阱10、第二P型阱11、第四P型阱20位于所述第二N型深阱27形成的凹槽内。第一N型深阱26可以对第一N型阱4、第一P型阱5、第三P型阱16中的元器件起到噪音屏蔽作用，同时能够防止该元器件向P型半导体衬底漏电。同样的，第二N型深阱27可以对所述第二N型阱10、第二P型阱11、第四P型阱20中的元器件起到噪音屏蔽作用，同时能够防止该元器件向P型半导体衬底漏电。其中，第一N型深阱26可以位于第一集成区，第二N型深阱27可以位于第二集成区。
本示例性实施例中，如图12所示，所述静电保护结构还包括：第九P型掺杂部 28，第九P型掺杂部28可以位于所述半导体衬底内，且所述第九P型掺杂部28可以位于所述第一集成区、第二集成区以外；其中，所述第九P型掺杂部28可以连接接地端VSS。第九P型掺杂部28可以用于将半导体衬底3接地。其中，接地端VSS可以理解为静电保护结构所在芯片的接地端。
本示例性实施例还提供一种芯片，该芯片包括上述的静电保护结构。本示例性实施例中，所述芯片包括电源端、接地端、信号传输端，所述芯片包括多个所述静电保护结构，多个所述静电保护结构包括：第一静电保护结构、第二静电保护结构、第三静电保护结构。第一静电保护结构的第一信号端连接所述电源端，第二信号端连接所述信号传输端，第三信号端连接所述接地端；第二静电保护结构的第一信号端连接信号传输端，第二信号端连接接地端，第三信号端连接电源端；第三静电保护结构的第一信号端连接接地端，第二信号端连接信号传输端，第三信号端连接电源端。
如图13所示，为本公开芯片一种示例性实施例的结构示意图。该芯片可以包括核心处理电路29、电源端VDD、接地端VSS、信号输入端INPUT、信号输出端OUTPUT。该芯片可以包括五个图12或图8所示静电保护结构。其中，静电保护结构31的第一信号端连接电源端VDD，第二信号端V2连接信号输入端INPUT，第三信号端V3连接接地端VSS；静电保护结构32的第一信号端连接信号输入端INPUT，第二信号端V2连接接地端VSS，第三信号端V3连接电源端VDD；静电保护结构33的第一信号端连接信号输出端OUTPUT，第二信号端V2连接接地端VSS，第三信号端V3连接电源端VDD；静电保护结构34的第一信号端连接接地端VSS，第二信号端V2连接信号输出端OUTPUT，第三信号端V3连接电源端VDD；静电保护结构35的第一信号端连接接地端VSS，第二信号端V2连接信号输入端INPUT，第三信号端V3连接电源端VDD。静电保护结构36的第一信号端连接电源端VDD，第二信号端V2连接输出端OUTPUT，第三信号端V3连接接地端VSS。其中，该芯片可以为存储芯片等任意芯片。应该理解的是，该芯片除了包括信号输出端和信号输出端以外，还可以包括其他信号传输端。
本示例性实施例还提供一种芯片，该芯片包括上述的静电保护电路。本示例性实施例中，所述芯片可以包括电源端、接地端、信号传输端，所述芯片包括多个所述静电保护电路，多个所述静电保护电路包括：第一静电保护电路、第二静电保护电路、第三静电保护电路。第一静电保护电路的第一信号端连接所述电源端，第二信号端连接所述信号传输端，第三信号端连接所述接地端；第二静电保护电路的第一信号端连接所述信号传输端，第二信号端连接所述接地端，第三信号端连接所述电源端；第三静电保护电路的第一信号端连接所述接地端，第二信号端连接所述信号传输端，第三信号端连接所述电源端。具体的，该芯片可以包括6个图3所示的静电保护电路，其中，6个静电保护电路在芯片中的连接方式可以与图13中静电保护结构的连接方式相同，此处不再赘述。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (16)

  1. 一种静电保护结构，包括：
    半导体衬底，包括第一集成区；
    第一N型阱，位于所述第一集成区；
    第一P型阱，位于所述第一集成区，且与所述第一N型阱相邻设置；
    第一N型掺杂部，位于所述第一N型阱内；
    第一P型掺杂部，位于所述第一N型阱内，且所述第一P型掺杂部位于所述第一N型掺杂部靠近所述第一P型阱的一侧；
    第二N型掺杂部，位于所述第一P型阱内；
    第二P型掺杂部，位于所述第一P型阱内，且位于所述第二N型掺杂部远离所述第一N型阱的一侧；
    其中，所述第一N型掺杂部与所述第二P型掺杂部电连接。
  2. 根据权利要求1所述的静电保护结构，其中，所述半导体衬底还包括第二集成区，所述第一集成区和所述第二集成区间隔设置，所述静电保护结构还包括：
    第二N型阱，位于所述第二集成区；
    第二P型阱，位于所述第二集成区，且与所述第二N型阱相邻设置；
    第三N型掺杂部，位于所述第二N型阱内；
    第三P型掺杂部，位于所述第二N型阱内，且所述第三P型掺杂部位于所述第三N型掺杂部靠近所述第二P型阱的一侧；
    第四N型掺杂部，位于所述第二P型阱内；
    第四P型掺杂部，位于所述第二P型阱内，且位于所述第四N型掺杂部远离所述第二N型阱的一侧；
    其中，所述第三N型掺杂部与所述第四P型掺杂部电连接，所述第二N型掺杂部与所述第三P型掺杂部电连接。
  3. 根据权利要求2所述的静电保护结构，其中，所述静电保护结构还包括：
    第三P型阱，位于所述第一集成区，且位于所述第一N型阱远离所述第一P型阱的一侧，所述第三P型阱与所述第一N型阱相邻设置；
    第五P型掺杂部，位于所述第一N型阱内，且所述第五P型掺杂部位于所述第一N型掺杂部远离所述第一P型掺杂部的一侧；
    第五N型掺杂部，位于所述第三P型阱内；
    第六P型掺杂部，位于所述第三P型阱内，且所述第六P型掺杂部位于所述第五N型掺杂部远离所述第一N型阱的一侧；
    其中，所述第一N型掺杂部与所述第六P型掺杂部电连接。
  4. 根据权利要求3所述的静电保护结构，其中，所述静电保护结构还包括：
    第四P型阱，位于所述第二集成区，且所述第四P型阱位于所述第二N型阱远离 所述第二P型阱的一侧，所述第四P型阱与所述第二N型阱相邻设置；
    第七P型掺杂部，位于所述第二N型阱内，且所述第七P型掺杂部位于所述第三N型掺杂部远离所述第三P型掺杂部的一侧；
    第六N型掺杂部，位于所述第四P型阱内；
    第八P型掺杂部，位于所述第四P型阱内，且所述第八P型掺杂部位于所述第六N型掺杂部远离所述第二N型阱的一侧；
    其中，所述第三N型掺杂部与所述第八P型掺杂部电连接，第五N型掺杂部与第七P型掺杂部电连接。
  5. 根据权利要求4所述的静电保护结构，其中，所述半导体衬底为P型半导体衬底。
  6. 根据权利要求5所述的静电保护结构，其中，所述静电保护结构还包括：
    第一N型深阱，形成于所述半导体衬底内，所述第一N型深阱呈凹槽结构，所述第一N型阱、第一P型阱、第三P型阱位于所述第一N型深阱形成的凹槽内。
  7. 根据权利要求5所述的静电保护结构，其中，所述静电保护结构还包括：
    第二N型深阱，形成于所述半导体衬底内，所述第二N型深阱呈凹槽结构，所述第二N型阱、第二P型阱、第四P型阱位于所述第二N型深阱形成的凹槽内。
  8. 根据权利要求5所述的静电保护结构，其中，所述静电保护结构还包括：
    第九P型掺杂部，位于所述半导体衬底内，且所述第九P型掺杂部位于所述第一集成区、第二集成区以外；
    其中，所述第九P型掺杂部连接接地端。
  9. 根据权利要求4-7任一项所述的静电保护结构，其中，所述静电保护结构还可以包括第一信号端、第二信号端、第三信号端，所述第一P型掺杂部和所述第五P型掺杂部用于连接所述静电保护结构的第一信号端，所述第四N型掺杂部用于连接所述静电保护结构的第二信号端，所述第六N型掺杂部用于连接所述静电保护结构的第三信号端。
  10. 一种静电保护电路，其中，包括至少一个静电保护单元，所述静电保护单元包括：
    晶闸管，包括：
    PNP型三极管，发射极形成所述晶闸管的阳极，基极连接第一节点，集电极连接第二节点；
    NPN型三极管，集电极连接所述第一节点，基极连接所述第一节点和第二节点，发射极形成所述晶闸管的阴极；
    第一二极管，所述第一二极管的阳极连接所述晶闸管的阳极，所述第一二极管的阴极连接所述第一节点；
    第二二极管，所述第二二极管的阳极连接所述第一节点，所述第二二极管的阴极 连接所述晶闸管的阴极。
  11. 根据权利要求10所述的静电保护电路，其中，所述静电保护电路中晶闸管的阳极形成该静电保护单元的阳极，所述静电保护电路中晶闸管的阴极形成该静电保护单元的阴极；
    所述静电保护电路包括多个所述静电保护单元，多个所述静电保护单元串联连接，且在相邻的两所述静电保护单元中，一个静电保护单元的阳极和另一静电保护单元的阴极连接。
  12. 根据权利要求11所述的静电保护电路，其中，所述静电保护电路包括：
    第一信号端、第二信号端、第三信号端；
    第一静电保护单元组，包括：
    第一静电保护单元，阳极连接所述第一信号端；
    第二静电保护单元，阳极连接所述第一静电保护单元的阴极，阴极连接所述第二信号端；
    第二静电保护单元组，包括：
    第三静电保护单元，阳极连接所述第一信号端；
    第四静电保护单元，阳极连接所述第三静电保护单元的阴极，阴极连接所述第三信号端；
    其中，所述第一静电保护单元、第二静电保护单元、第三静电保护单元、第四静电保护单元形成多个所述静电保护单元。
  13. 一种芯片，其中，包括权利要求1-9任一项所述的静电保护结构。
  14. 根据权利要求13所述的芯片，其中，所述芯片包括电源端、接地端、信号传输端，所述芯片包括多个所述静电保护结构，当所述静电保护结构包括第一信号端、第二信号端、第三信号端时，多个所述静电保护结构包括：
    第一静电保护结构，第一信号端连接所述电源端，第二信号端连接所述信号传输端，第三信号端连接所述接地端；
    第二静电保护结构，第一信号端连接所述信号传输端，第二信号端连接所述接地端，第三信号端连接所述电源端；
    第三静电保护结构，第一信号端连接所述接地端，第二信号端连接所述信号传输端，第三信号端连接所述电源端。
  15. 一种芯片，其中，包括权利要求10-12任一项所述的静电保护电路。
  16. 根据权利要求15所述的芯片，其中，所述芯片包括电源端、接地端、信号传输端，所述芯片包括多个所述静电保护电路，当所述静电保护电路包括第一信号端、第二信号端、第三信号端时，多个所述静电保护电路包括：
    第一静电保护电路，第一信号端连接所述电源端，第二信号端连接所述信号传输端，第三信号端连接所述接地端；
    第二静电保护电路，第一信号端连接所述信号传输端，第二信号端连接所述接地端，第三信号端连接所述电源端；
    第三静电保护电路，第一信号端连接所述接地端，第二信号端连接所述信号传输端，第三信号端连接所述电源端。
PCT/CN2021/111532 2020-12-23 2021-08-09 静电保护结构、静电保护电路、芯片 WO2022134606A1 (zh)

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