CN102812546B - 制造双面装备有芯片的晶片的方法 - Google Patents

制造双面装备有芯片的晶片的方法 Download PDF

Info

Publication number
CN102812546B
CN102812546B CN201080065914.6A CN201080065914A CN102812546B CN 102812546 B CN102812546 B CN 102812546B CN 201080065914 A CN201080065914 A CN 201080065914A CN 102812546 B CN102812546 B CN 102812546B
Authority
CN
China
Prior art keywords
wafer
layer
intermediate layer
adhesion
adhesive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201080065914.6A
Other languages
English (en)
Chinese (zh)
Other versions
CN102812546A (zh
Inventor
J.布格拉夫
M.温普林格
H.韦斯鲍尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EV Group E Thallner GmbH
Original Assignee
EV Group E Thallner GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EV Group E Thallner GmbH filed Critical EV Group E Thallner GmbH
Publication of CN102812546A publication Critical patent/CN102812546A/zh
Application granted granted Critical
Publication of CN102812546B publication Critical patent/CN102812546B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • H10P10/12Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H10P72/7418Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. a chip mounting substrate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7436Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to support a device or a wafer when forming electrical connections thereto
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • H10P72/7442Separation by peeling
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • H10P72/7442Separation by peeling
    • H10P72/7444Separation by peeling using a peeling wedge, a knife or a bar
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63Vias, e.g. via plugs
    • H10W70/635Through-vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/0198Manufacture or treatment batch processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07202Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
    • H10W72/07207Temporary substrates, e.g. removable substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • H10W74/014Manufacture or treatment using batch processing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/22Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/297Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
CN201080065914.6A 2010-03-31 2010-03-31 制造双面装备有芯片的晶片的方法 Active CN102812546B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2010/002055 WO2011120537A1 (de) 2010-03-31 2010-03-31 Verfahren zur herstellung eines doppelseitig mit chips bestückten wafers

Publications (2)

Publication Number Publication Date
CN102812546A CN102812546A (zh) 2012-12-05
CN102812546B true CN102812546B (zh) 2015-08-26

Family

ID=42286741

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201080065914.6A Active CN102812546B (zh) 2010-03-31 2010-03-31 制造双面装备有芯片的晶片的方法

Country Status (8)

Country Link
US (1) US9224630B2 (https=)
EP (1) EP2553719B1 (https=)
JP (1) JP5763169B2 (https=)
KR (3) KR20130040779A (https=)
CN (1) CN102812546B (https=)
SG (1) SG183820A1 (https=)
TW (1) TWI518758B (https=)
WO (1) WO2011120537A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9827757B2 (en) 2011-07-07 2017-11-28 Brewer Science Inc. Methods of transferring device wafers or layers between carrier substrates and other surfaces
BR112016023471B1 (pt) * 2014-04-09 2022-05-03 Lionel O. Barthold Sistema de transformação de potência de cc em cc de múltiplos módulos e sistema para regulação de transferência de potência
WO2020178080A1 (en) * 2019-03-05 2020-09-10 Evatec Ag Method for processing fragile substrates employing temporary bonding of the substrates to carriers
WO2021164855A1 (de) 2020-02-18 2021-08-26 Ev Group E. Thallner Gmbh Verfahren und vorrichtung zur übertragung von bauteilen
CN118891713A (zh) 2022-03-25 2024-11-01 Ev 集团 E·索尔纳有限责任公司 用于分离载体基板的方法和基板系统
KR102788502B1 (ko) * 2023-07-27 2025-04-01 한국기계연구원 효과적인 디본딩이 가능한 웨이퍼 모듈, 및 이의 본딩 및 디본딩 방법
WO2025228530A1 (de) 2024-05-02 2025-11-06 Ev Group E. Thallner Gmbh Verfahren zum temporären verbinden eines produktsubstrats und eines trägersubstrats, trägersubstrat, produktsubstrat und schichtsystem sowie deren anordnung und eine vorrichtung zum durchführen eines solchen verfahrens

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1491439A (zh) * 2001-11-22 2004-04-21 ���ṫ˾ 多芯片电路模块及其制造方法
CN1528009A (zh) * 2001-04-13 2004-09-08 ����ԭ����ίԱ�� 可拆除基片或可拆除结构及其生产方法
US20090218560A1 (en) * 2008-01-24 2009-09-03 Brewer Science Inc. Method for reversibly mounting a device wafer to a carrier substrate

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6198784A (ja) * 1984-10-20 1986-05-17 Kimurashin Kk ロール状又は積層状の両面接着テープ
JPH04283283A (ja) 1991-03-08 1992-10-08 Nippon Synthetic Chem Ind Co Ltd:The 開封自在テープ
JP3686454B2 (ja) 1995-05-10 2005-08-24 日東電工株式会社 接着型使捨てカイロ用粘着シート及びそのカイロ
WO1997039481A1 (en) 1996-04-12 1997-10-23 Northeastern University An integrated complex-transition metal oxide device and a method of fabricating such a device
JPH11105924A (ja) 1997-10-06 1999-04-20 Nitto Denko Corp 電子部品搬送用テ−プ
JPH11238375A (ja) * 1998-02-20 1999-08-31 Sony Corp 電子機器の放熱装置とディスクドライブ装置
JP2000326995A (ja) 1999-05-17 2000-11-28 Ogawa Sangyo Kk 滅菌袋
JP2002097041A (ja) 2000-07-17 2002-04-02 Sekisui Chem Co Ltd 合わせガラス用中間膜及び合わせガラス
JP2003218063A (ja) * 2002-01-24 2003-07-31 Canon Inc ウエハ貼着用粘着シート及び該シートを利用する加工方法
US6794273B2 (en) 2002-05-24 2004-09-21 Fujitsu Limited Semiconductor device and manufacturing method thereof
JP4565804B2 (ja) 2002-06-03 2010-10-20 スリーエム イノベイティブ プロパティズ カンパニー 被研削基材を含む積層体、その製造方法並びに積層体を用いた極薄基材の製造方法及びそのための装置
JP4364535B2 (ja) * 2003-03-27 2009-11-18 シャープ株式会社 半導体装置の製造方法
JP4405246B2 (ja) 2003-11-27 2010-01-27 スリーエム イノベイティブ プロパティズ カンパニー 半導体チップの製造方法
US7232740B1 (en) 2005-05-16 2007-06-19 The United States Of America As Represented By The National Security Agency Method for bumping a thin wafer
US8592286B2 (en) 2005-10-05 2013-11-26 Stats Chippac Ltd. Ultra-thin wafer system and method of manufacture thereof
DE102006000687B4 (de) 2006-01-03 2010-09-09 Thallner, Erich, Dipl.-Ing. Kombination aus einem Träger und einem Wafer, Vorrichtung zum Trennen der Kombination und Verfahren zur Handhabung eines Trägers und eines Wafers
US20080003780A1 (en) * 2006-06-30 2008-01-03 Haixiao Sun Detachable stiffener for ultra-thin die
US20080044984A1 (en) * 2006-08-16 2008-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of avoiding wafer breakage during manufacture of backside illuminated image sensors
US7838391B2 (en) * 2007-05-07 2010-11-23 Stats Chippac, Ltd. Ultra thin bumped wafer with under-film
JP2009043962A (ja) * 2007-08-09 2009-02-26 Sony Corp 半導体装置の製造方法
EP2104138A1 (de) 2008-03-18 2009-09-23 EV Group E. Thallner GmbH Verfahren zum Bonden von Chips auf Wafer
JP4572243B2 (ja) * 2008-03-27 2010-11-04 信越化学工業株式会社 熱伝導性積層体およびその製造方法
JP2010010644A (ja) * 2008-05-27 2010-01-14 Toshiba Corp 半導体装置の製造方法
JP2010092931A (ja) * 2008-10-03 2010-04-22 Toshiba Corp 半導体装置の製造方法及び半導体装置の製造装置
US8267143B2 (en) 2009-04-16 2012-09-18 Suss Microtec Lithography, Gmbh Apparatus for mechanically debonding temporary bonded semiconductor wafers
US8689437B2 (en) * 2009-06-24 2014-04-08 International Business Machines Corporation Method for forming integrated circuit assembly
EP2299486B1 (de) * 2009-09-18 2015-02-18 EV Group E. Thallner GmbH Verfahren zum Bonden von Chips auf Wafer
US8008121B2 (en) * 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US9136144B2 (en) * 2009-11-13 2015-09-15 Stats Chippac, Ltd. Method of forming protective material between semiconductor die stacked on semiconductor wafer to reduce defects during singulation
US8017439B2 (en) * 2010-01-26 2011-09-13 Texas Instruments Incorporated Dual carrier for joining IC die or wafers to TSV wafers
TWI419302B (zh) * 2010-02-11 2013-12-11 日月光半導體製造股份有限公司 封裝製程
US8252682B2 (en) * 2010-02-12 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for thinning a wafer
JP4976522B2 (ja) * 2010-04-16 2012-07-18 日東電工株式会社 熱硬化型ダイボンドフィルム、ダイシング・ダイボンドフィルム、及び、半導体装置の製造方法
US8852391B2 (en) * 2010-06-21 2014-10-07 Brewer Science Inc. Method and apparatus for removing a reversibly mounted device wafer from a carrier substrate
US8492197B2 (en) * 2010-08-17 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
JP2012069919A (ja) * 2010-08-25 2012-04-05 Toshiba Corp 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1528009A (zh) * 2001-04-13 2004-09-08 ����ԭ����ίԱ�� 可拆除基片或可拆除结构及其生产方法
CN1491439A (zh) * 2001-11-22 2004-04-21 ���ṫ˾ 多芯片电路模块及其制造方法
US20090218560A1 (en) * 2008-01-24 2009-09-03 Brewer Science Inc. Method for reversibly mounting a device wafer to a carrier substrate

Also Published As

Publication number Publication date
EP2553719A1 (de) 2013-02-06
US20130011997A1 (en) 2013-01-10
EP2553719B1 (de) 2019-12-04
WO2011120537A1 (de) 2011-10-06
JP2013524493A (ja) 2013-06-17
KR20130040779A (ko) 2013-04-24
US9224630B2 (en) 2015-12-29
TW201145370A (en) 2011-12-16
SG183820A1 (en) 2012-10-30
TWI518758B (zh) 2016-01-21
JP5763169B2 (ja) 2015-08-12
CN102812546A (zh) 2012-12-05
KR20170042817A (ko) 2017-04-19
KR101856429B1 (ko) 2018-05-09
KR20160075845A (ko) 2016-06-29

Similar Documents

Publication Publication Date Title
CN102812546B (zh) 制造双面装备有芯片的晶片的方法
US10103048B2 (en) Dual-layer bonding material process for temporary bonding of microelectronic substrates to carrier substrates
US9159595B2 (en) Thin wafer carrier
US8846499B2 (en) Composite carrier structure
TW447025B (en) Process for precision alignment of chips for mounting on a substrate
CN116391252A (zh) 具有互连结构的键合结构
EP2162907B1 (fr) Dispositif comportant des composants encastrés dans des cavités d'une plaquette d'accueil et procédé correspondant
US8383460B1 (en) Method for fabricating through substrate vias in semiconductor substrate
US9595446B2 (en) Methods of processing substrates
EP3333882B1 (en) Method for bonding thin semiconductor chips to a substrate
JP6360123B2 (ja) ワークピースの加工手順およびシステム
JP5334411B2 (ja) 貼り合わせ基板および貼り合せ基板を用いた半導体装置の製造方法
KR102403580B1 (ko) 쉬운 조립을 위한 초소형 또는 초박형 개별 컴포넌트의 구성
KR101503326B1 (ko) 디바이스 웨이퍼와 캐리어 웨이퍼의 디본딩 방법 및 장치
CN108886015A (zh) 用于接合两个衬底的方法与装置
TW201133772A (en) Method for bonding of chips on wafers
KR20150001253A (ko) 디바이스 웨이퍼와 캐리어 웨이퍼의 디본딩 방법 및 본딩/디본딩 장치
US20090251879A1 (en) Die thinning processes and structures
US20050000636A1 (en) Method for temporarily fixing two planar workpieces
CN107910288B (zh) 基于太鼓晶圆的晶圆级封装结构及方法
CN118448328A (zh) 一种功能晶圆临时键合与解键合方法及临时键合载体
CN107644843B (zh) 晶圆堆叠制作方法
KR102819751B1 (ko) 용융 본딩 및 본딩 분리를 위한 저밀도 실리콘 산화물에 대한 방법 및 구조물
Ishida et al. Temporary bonding/de-bonding and permanent wafer bonding solutions for 3D integration
Chanchani An Overview-temporary wafer bonding/debonding for 2.5 d and 3d technologies

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant