CN107910288B - 基于太鼓晶圆的晶圆级封装结构及方法 - Google Patents

基于太鼓晶圆的晶圆级封装结构及方法 Download PDF

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CN107910288B
CN107910288B CN201711045692.1A CN201711045692A CN107910288B CN 107910288 B CN107910288 B CN 107910288B CN 201711045692 A CN201711045692 A CN 201711045692A CN 107910288 B CN107910288 B CN 107910288B
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wafer
taiko
support
thinning
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郑凤霞
刘路路
王腾
马书英
于大全
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Huatian Technology Kunshan Electronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device

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Abstract

本发明公开了一种基于太鼓晶圆的晶圆级封装结构及方法,通过在使用太鼓减薄工艺减薄后的太鼓晶圆的中心部分键合一支撑晶圆,实现了对太鼓晶圆中心部分的加厚,使其可继续进行晶圆级的封装工艺。该方法也避免了使用特别的太鼓晶圆支撑环去除设备,使得太鼓晶圆的晶圆级封装在标准的封装产线中即可实现。

Description

基于太鼓晶圆的晶圆级封装结构及方法
技术领域
本发明涉及半导体封装技术领域,尤其涉及一种基于太鼓晶圆的晶圆级封装结构及方法。
背景技术
太鼓(Taiko)减薄工艺是由日本DISCO公司开发的一种晶圆减薄工艺,经太鼓减薄工艺的晶圆在此称为太鼓晶圆。太鼓(Taiko)减薄工艺只对晶圆(硅片)的中间部分进行减薄,将边缘部分保留为支撑环,利用晶圆减薄的中间部分形成集成电路的器件,利用较厚的支撑环来保持整个晶圆的机械强度,防止晶圆发生卷曲,有利于后续工艺中对晶圆的搬运、转移和加工。但是,由于支撑环的存在,太鼓晶圆的晶圆级封装无法在标准的封装产线中完成,也就是说太鼓晶圆在后续晶圆级封装工艺前,通常需要将支撑环去除,这步去环工艺通常需要在特别的去环设备上进行,参见专利文献CN105428220A,也就是说需要引入了额外的工艺和设备,增加生产成本。
另外,在一些产品的制造中,需要在衬底背面将同一封装内的多个器件在背面连接。出于性能的考虑,该连接层离晶圆正面的距离需要被制作得很小。因此,在此类产品的制造中,使用太鼓减薄工艺将晶圆减薄并在减薄区制作背面连接层后,如果继续使用晶圆级封装工艺对其进行封装,晶圆被减薄的中心部分过薄,该区域无法承受某些工艺制程,导致太鼓晶圆应用受限。
发明内容
为了解决上述技术问题,本发明提出一种基于太鼓晶圆的晶圆级封装结构及方法,实现了对太鼓晶圆中心部分的加厚的同时,使其可继续进行晶圆级的封装工艺,且避免了使用特别的太鼓晶圆支撑环去除设备,使得太鼓晶圆的晶圆级封装在标准的封装产线中即可实现。
本发明的技术方案是这样实现的:
一种基于太鼓晶圆的晶圆级封装方法,包括如下步骤:
a)提供一太鼓晶圆,该太鼓晶圆包括背面中部被减薄到需要厚度而形成的中间减薄区和背面边缘未被减薄而形成的支撑环;
b)制作一支撑晶圆,所述支撑晶圆的尺寸小于所述太鼓晶圆的支撑环的开口尺寸,所述支撑晶圆的厚度大于所述太鼓晶圆的支撑环的开口深度,在该支撑晶圆的一表面涂布粘结剂;
c)将步骤b中的支撑晶圆键合固定于所述太鼓晶圆的支撑环内的中间减薄区上,使支撑晶圆与太鼓晶圆通过粘结剂连接起来;
d)将步骤c后支撑晶圆进行研磨至目标厚度,并将研磨后的支撑晶圆和太鼓晶圆组成的整体进行切割,形成单颗晶圆级封装结构。
进一步的,在步骤c后,在太鼓晶圆的支撑环与支撑晶圆之间的环形间隙中填满填充材料。
进一步的,在步骤a后,通过干法刻蚀去除太鼓晶圆因研磨减薄产生的内应力。
进一步的,在步骤a后,在太鼓晶圆的中间减薄区内制作导电连接层。
一种基于太鼓晶圆的晶圆级封装结构,由基于太鼓晶圆的晶圆封装结构切割形成,包括依次设置的芯片、粘结层和支撑体,所述基于太鼓晶圆的晶圆封装结构包括太鼓晶圆和支撑晶圆,所述太鼓晶圆包括背面中部被减薄到需要厚度而形成的中间减薄区和背面边缘未被减薄而形成的支撑环,所述中间减薄区由若干芯片组成,各芯片之间具有切割道;所述支撑晶圆通过粘结层贴装于所述太鼓晶圆的支撑环内的中间减薄区上;所述支撑晶圆的外侧与所述支撑环之间具有环形间隙,所述环形间隙内填有填充材料,所述支撑体由所述支撑晶圆切割分立形成。
进一步的,所述芯片的厚度为20μm~200μm。
进一步的,所述芯片的背面设有导电连接层。
进一步的,所述导电连接层与所述芯片背面之间还设有钝化层。
本发明的有益效果是:本发明提供一种基于太鼓晶圆的晶晶圆级封装结构及方法,该晶圆封装结构通过在使用太鼓减薄工艺减薄后的太鼓晶圆的中心部分键合一支撑晶圆,实现了对太鼓晶圆中心部分的加厚,使其可继续进行晶圆级的封装工艺。该晶圆级封装方法避免了使用特别的太鼓晶圆支撑环去除设备,使得太鼓晶圆的晶圆级封装在标准的封装产线中即可实现。
附图说明
图1是本发明实施例方法流程图;
图2是本发明实施例方法中太鼓晶圆结构示意图;
图3是本发明实施例方法中支撑晶圆结构示意图;
图4是本发明实施例方法中将支撑晶圆键合于太鼓晶圆的支撑环后的结构示意图;
图5是本发明实施例方法中在支撑晶圆与太鼓晶圆的支撑环之间的环状间隙内填满填充材料后的结构示意图;
图6是本发明实施例方法中将整个太鼓晶圆进行研磨至目标厚度的结构示意图;
图7是本发明晶圆级封装结构的示意图。
具体实施方式
为使本发明能够更加易懂,下面结合附图对本发明的具体实施方式做详细的说明。为方便说明,实施例附图的结构中各组成部分未按正常比例缩放,故不代表实施例中各结构的实际相对大小。
如图1所示,是本发明实施例方法流程图,如图2至图6所示,是本发明实施例方法中各步骤后的晶圆结构示意图。本发明基于太鼓晶圆的晶圆级封装方法包括如下步骤:
步骤一,参见图2,使用太鼓减薄工艺方法对晶圆背面中部进行减薄,形成太鼓晶圆1,该太鼓晶圆的中间部分减薄到需要的厚度,形成中间减薄区101,该太鼓晶圆的边缘部分不被减薄而形成一支撑环102;通过干法刻蚀去除图2中晶圆因研磨减薄产生的内应力;如应用需要,还可在太鼓晶圆的背面通过溅射等方法制作形成导电连接层。
步骤二,参见图3,另制作一支撑晶圆2,该支撑晶圆的尺寸小于太鼓晶圆的支撑环的开口尺寸;该支撑晶圆的厚度大于太鼓晶圆的支撑环的开口深度。这样,支撑晶圆的尺寸小于太鼓晶圆的尺寸,如果太鼓晶圆的尺寸是标准尺寸,那么支撑晶圆的尺寸就要小于标准尺寸,支撑晶圆的尺寸减小具体可通过机械切割、激光切割、腐蚀或其他方法实现。然后,在该支撑晶圆的一表面通过旋涂、喷涂、压膜等工艺涂布一层粘结剂,参见图3。
步骤三,参见图4,将步骤二中的涂布过粘结剂的支撑晶圆和步骤一中研磨减薄后的太鼓晶圆通过键合制程进行固定,即将支撑晶圆键合固定于太鼓晶圆的支撑环内的中间减薄区上,使支撑晶圆2与太鼓晶圆1通过粘结层3(粘结剂固化后形成)连接起来,以便于进行后续晶圆级封装制程的作业。该工艺步骤中,需要采用晶圆对准机构将支撑晶圆对准贴装到太鼓晶圆的支撑环内,其中,使用的晶圆对准机构中的隔离片(spacer)要求伸入晶圆间的距离较长,也需要较高的机械强度,以支撑尺寸已减小的支撑晶圆。
步骤四、参见图5,在步骤三后,在太鼓晶圆的支撑环与支撑晶圆之间的环形间隙中填满填充材料4。这样,在后续的晶圆运输和研磨等步骤中可降低裂片风险,填满填充材料的方法可采用在太鼓晶圆和支撑晶圆间的环形间隙中用点胶或印刷工艺填满高分子材料。也可以通过提高前一步中的压合力,使太鼓晶圆和支撑晶圆之间的粘结剂(通常为胶水)外溢,从而填满支撑晶圆与太鼓晶圆之间的环形间隙。
步骤五、参见图6,对支撑晶圆进行研磨至目标厚度,并将研磨后的支撑晶圆和太鼓晶圆组成的整体进行切割,形成单颗晶圆级封装结构,即形成单颗封装体。
参见图6,一种基于太鼓晶圆的晶圆封装结构,该基于太鼓晶圆的晶圆封装结构包括太鼓晶圆和支撑晶圆,太鼓晶圆包括背面中部被减薄到需要厚度而形成的中间减薄区和背面边缘未被减薄而形成的支撑环,中间减薄区由若干芯片11组成,各芯片单元之间具有切割道,各芯片的背面设有导电连接层,芯片的厚度为20μm~200μm;支撑晶圆通过粘结层3贴装于太鼓晶圆的支撑环内的中间减薄区上;支撑晶圆的外侧与所述支撑环之间具有环形间隙,环形间隙内填有填充材料。沿各芯片之间的切割道对基于太鼓晶圆的晶圆封装结构进行切割,即可形成基于太鼓晶圆的晶圆级封装结构,即该晶圆级封装结构包括芯片11、导电连接层(未示出)、粘结层3和分立支撑晶圆后的支撑体21,参见图7。在其他实施例中,导电连接层与芯片背面之间还设有钝化层。综上,本发明提供一种基于太鼓晶圆的晶圆级封装结构及方法,通过在使用太鼓减薄工艺减薄后的太鼓晶圆的中心部分键合一支撑晶圆,实现了对太鼓晶圆中心部分的加厚,使其可继续进行晶圆级的封装工艺。该方法也避免了使用特别的太鼓晶圆支撑环去除设备,使得太鼓晶圆的晶圆级封装在标准的封装产线中即可实现。
以上实施例是参照附图,对本发明的优选实施例进行详细说明。本领域的技术人员通过对上述实施例进行各种形式上的修改或变更,但不背离本发明的实质的情况下,都落在本发明的保护范围之内。

Claims (6)

1.一种基于太鼓晶圆的晶圆级封装方法,其特征在于,包括如下步骤:
a)提供一太鼓晶圆,该太鼓晶圆包括背面中部被减薄到需要厚度而形成的中间减薄区和背面边缘未被减薄而形成的支撑环;并还通过干法刻蚀去除太鼓晶圆因研磨减薄产生的内应力;
b)制作一支撑晶圆,所述支撑晶圆的尺寸小于所述太鼓晶圆的支撑环的开口尺寸,所述支撑晶圆的厚度大于所述太鼓晶圆的支撑环的开口深度,在该支撑晶圆的一表面涂布粘结剂;
c)采用晶圆对准机构将步骤b中的支撑晶圆对准并键合固定于所述太鼓晶圆的支撑环内的中间减薄区上,使支撑晶圆与太鼓晶圆通过粘结剂连接起来;然后在太鼓晶圆的支撑环与支撑晶圆之间的环形间隙中填满填充材料;
d)将步骤c后支撑晶圆进行研磨至目标厚度,并将研磨后的支撑晶圆和太鼓晶圆组成的整体进行切割,形成单颗晶圆级封装结构。
2.根据权利要求1所述的基于太鼓晶圆的晶圆级封装方法,其特征在于:在步骤a后,在太鼓晶圆的中间减薄区内制作导电连接层。
3.一种基于太鼓晶圆的晶圆级封装结构,其特征在于,由基于太鼓晶圆的晶圆封装结构切割形成,包括依次设置的芯片、粘结层和支撑体,所述基于太鼓晶圆的晶圆封装结构包括太鼓晶圆和支撑晶圆,所述太鼓晶圆包括背面中部被减薄到需要厚度而形成的中间减薄区和背面边缘未被减薄而形成的支撑环,所述中间减薄区由若干芯片组成,各芯片之间具有切割道;所述支撑晶圆通过粘结层贴装于所述太鼓晶圆的支撑环内的中间减薄区上;所述支撑晶圆的外侧与所述支撑环之间具有环形间隙,所述环形间隙内填有填充材料,所述支撑体由所述支撑晶圆切割分立形成。
4.根据权利要求3所述的基于太鼓晶圆的晶圆级封装结构,其特征在于,所述芯片的厚度为20μm~200μm。
5.根据权利要求3所述的基于太鼓晶圆的晶圆级封装结构,其特征在于,所述芯片的背面设有导电连接层。
6.根据权利要求5所述的太鼓晶圆的晶圆级封装结构,其特征在于,所述导电连接层与所述芯片背面之间还设有钝化层。
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