CN109411359B - 用于处理半导体装置结构的方法和设备 - Google Patents

用于处理半导体装置结构的方法和设备 Download PDF

Info

Publication number
CN109411359B
CN109411359B CN201810933189.8A CN201810933189A CN109411359B CN 109411359 B CN109411359 B CN 109411359B CN 201810933189 A CN201810933189 A CN 201810933189A CN 109411359 B CN109411359 B CN 109411359B
Authority
CN
China
Prior art keywords
wafer
device wafer
sacrificial material
carrier
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810933189.8A
Other languages
English (en)
Other versions
CN109411359A (zh
Inventor
A·M·贝利斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN109411359A publication Critical patent/CN109411359A/zh
Application granted granted Critical
Publication of CN109411359B publication Critical patent/CN109411359B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381Details of chemical or physical process used for separating the auxiliary support from a device or wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Geometry (AREA)

Abstract

本申请涉及一种用于处理半导体装置结构的方法和设备。一种处理装置晶片的方法包括:将牺牲材料涂覆到载体晶片的表面;将所述装置晶片的表面粘附到所述载体晶片的相对表面;通过仅移除所述牺牲材料厚度的一部分来平面化所述牺牲材料的暴露表面;以及平面化所述装置晶片的相对表面。还公开一种晶片组合件。

Description

用于处理半导体装置结构的方法和设备
优先权要求
本申请要求申请日2017年8月18日申请的第No.15/680,461号美国专利申请案“用于处理半导体装置结构的方法和设备(Method and Apparatus for ProcessingSemiconductor Device Structures)”的权益。
技术领域
本公开大体上涉及制造半导体装置的方法。更具体地说,所公开的实施例涉及用于处理半导体装置结构的方法和设备,其可增强例如晶片的块状半导体衬底的平面化且减小此类过程的成本。
背景技术
常规晶片载体系统将工艺晶片(其还可描述为装置晶片)粘合到载体以进行背侧处理,包含对工艺晶片进行大量薄化,此后将工艺晶片与载体分开。然而,为了充分平面化以及薄化粘合到载体的装置晶片,载体自身在粘合到装置晶片时以及在装置晶片薄化过程期间应呈现足够的平面度,以便充当参考面且防止经薄化装置晶片平面度的不可接受的偏差。
虽然已知呈半导体和玻璃材料两个形式的载体,但当前优选在呈载体晶片形式的半导体(一般是硅)载体粘合到装置晶片之后以及在装置晶片薄化之前平面化所述半导体载体。此优选很大程度上归因于能够使用可随后用于薄化和平面化装置晶片的同一设备来平面化半导体载体晶片。相比之下,归因于玻璃载体的不同材料特性,必须使用不同设备且尤其是用于接触玻璃的工具元件来平面化玻璃载体。
然而,使用半导体或玻璃材料的载体晶片的显著缺点是载体晶片在其平面化期间所需的薄化。通常为至少约20μm到不超过约30μm的此类薄化将载体的再次使用限制于相对少的次数,此后,经薄化载体晶片的结构刚度在处理期间不足以支撑装置晶片。这时,所述载体晶片必须被舍弃且用另一载体晶片替换。因此,现代现有技术半导体厂中处理的大量装置晶片每年会产生用于载体晶片的至少数十万美元的成本。
发明内容
本公开的实施例可表征为一种处理装置晶片的方法,所述方法包括:将牺牲材料涂覆于载体晶片的表面;将所述装置晶片的表面粘附到所述载体晶片的相对表面;通过仅移除所述牺牲材料的厚度的一部分来平面化所述牺牲材料的暴露表面;以及平面化所述装置晶片的相对表面。
本公开的另一实施例可表征为一种处理装置晶片的方法,其包括在不移除载体晶片材料的情况下平面化粘合到装置晶片的载体晶片的暴露表面,以及从装置晶片的暴露表面处减小装置晶片的厚度,且在减小厚度之后平面化所述装置晶片的暴露表面。
本公开的另一实施例可表征为一种晶片组合件,其包括:载体晶片,其在其表面上具有大体上均匀的牺牲材料涂层;以及装置晶片,其粘合到所述载体晶片的未涂布的相对表面。
本公开的又一实施例可表征为一种晶片组合件,其包括:载体晶片,其具有未涂布任何材料的暴露表面;以及厚度低于约100μm的装置晶片,其粘合到所述载体晶片的相对表面,所述装置晶片在其与所述载体晶片相对的暴露表面上呈现低于约8μm的总厚度变化。
附图说明
尽管本公开利用确切地指出且清楚地主张特定实施例的权利要求进行总结,但本公开范围内的实施例的各种特征和优势可在结合附图阅读时从以下描述更轻松地确定,在附图中:
图1是根据本公开的实施例的处置半导体装置晶片的过程中的第一阶段的侧面横截面侧视图;
图2是处置半导体装置晶片的过程中的第二阶段的侧面横截面图;
图3是处置半导体装置晶片的过程中的第三阶段的侧面横截面图;
图4是处置半导体装置结构的过程中的第四阶段的侧面横截面图;
图5是处置半导体装置结构的过程中的第五阶段的侧面横截面图;
图6是处置半导体装置结构的过程中的第六阶段的侧面横截面图;以及
图7是处置半导体装置结构的过程中的第七阶段的侧面横截面图。
具体实施方式
本公开中呈现的图解并非意指任何特定晶片、晶片组合件、处置半导体装置结构、系统或其组件的过程中的动作的实际视图,而是仅为用于描述说明性实施例的理想化表示。因此,各图未必按比例绘制。
本公开的实施例大体上涉及用于处理半导体装置晶片的方法和设备,其可增强此类晶片在薄化之后的平面度以及降低薄化过程的成本。更具体地说,本公开的实施例涉及涂覆到载体晶片的表面的牺牲材料的使用,所述表面与待粘合到装置晶片以在粘合到所述装置晶片之后在研磨薄化和平面化过程期间支撑所述装置晶片的表面相对。在装置晶片粘合到载体晶片之后移除牺牲材料的厚度的一部分以平面化载体晶片上临时的牺牲材料。接着薄化和平面化装置晶片,从载体晶片移除牺牲材料,且装置晶片与载体晶片脱粘。
如本文所使用,术语“装置晶片”意指且包含块状衬底,其包括一或多种半导体材料且易于通过从晶片移除半导体材料进行薄化以实现较小厚度。此类衬底可配置为常规圆形晶片、其它块状衬底或此类晶片或块状衬底的片段。装置晶片可包括半导体裸片位点阵列,其可单分为个别裸片或较大晶片片段。在根据本公开的实施例进行处理之前,装置晶片的作用表面上可制造有集成电路,且在其上可放置有且任选地包封有额外裸片或裸片叠层。预期本公开的实施例尤其适合于结合常规圆形硅晶片实施,但本公开不限于此。
如本文所使用,术语“载体晶片”意指且包含玻璃或其它合适材料的半导体衬底,其呈现足够的刚度和与待粘合的装置晶片兼容的热膨胀系数(CTE),且支撑所述装置晶片以进行薄化和平面化。尽管并非必需,但预期载体晶片将在大小和形状上大体上对应于装置晶片的大小和形状。
如本文所使用,术语“牺牲材料”意指且包含可易于涂覆到载体晶片的表面且将在应力的施加下粘附到所述表面上以便通过设备移除其一部分的材料,所述设备例如用于薄化和平面化粘合到其上的晶片研磨和/或化学机械平面化工具。此类材料还呈现足够的硬度和结构完整性以便在施加的此类应力下以及以后维持表面构形的完整性、足够的限定和平面度。正性和负性光致抗蚀剂、旋涂式电介质(SOD)材料、抗反射涂层(ARC)材料和其它材料,例如氧化硅和氮化硅,是合适的牺牲材料的非限制性实例。光致抗蚀剂和SOD材料可通过常规旋涂技术进行涂覆。ARC材料以及其它氧化物和氮化物可通过化学气相沉积涂覆,包含低压化学气相沉积(LPCVD)和等离子体增强式化学气相沉积(PECVD)。牺牲材料可涂覆到例如约15μm到约30μm的厚度。如本文所使用,术语“涂覆”意指且包含物理涂覆牺牲材料以及当场形成牺牲材料。
参考图1,半导体或玻璃材料的载体晶片100的侧面横截面立面包含已涂覆到载体晶片的表面104的牺牲材料102。
参考图2,可倒置载体晶片100,将粘合材料204涂覆到表面106,且通过粘合材料204将装置晶片200的表面202(例如作用表面)粘合到表面106以形成工序内晶片组合件300,其中装置晶片200的表面206待薄化和平面化。粘合材料204可包括例如经调配以临时粘附到载体晶片100且将所述载体晶片固定到装置晶片200的聚合物材料。所述材料可大体上无空隙和污染,呈现平面度公差且提供翘曲控制,呈现应力吸收特性,耐受例如从约20℃到约320℃的过程温度,且呈现针对半导体制造中、且尤其是背侧处理中所用的广泛范围的液体和反应剂的化学抗性。粘合材料204的选择可考虑晶片材料和类型、装置类型和灵敏度、支撑载体类型、粘合条件、工艺条件、脱粘条件以及残余物和清理问题。
粘合材料204可包含低温蜡、烃寡聚物和聚合物、改性丙烯酸酯、改性环氧树脂、改性硅酮和高温热固性塑料或热固性塑料。粘合材料204可通过例如旋涂涂覆为液体或可流动凝胶、涂覆为胶带或涂覆为预制膜。更具体地说,粘合材料204可包含热固性或热塑性聚合物材料,优选地经调配以耐受例如用在材料沉积中的那些较高处理温度,同时不准许载体晶片100与固定到其上的装置晶片200之间的相对横向或竖直移动。作为具体的非限制性实例,粘合材料204可包含固化或部分固化的热固性材料或用于形成热固性材料的前体(例如硅酮胶粘剂401LC,可购自美国信越有机硅公司(Shin-Etsu Silicones of America,Inc.),俄亥俄州阿克伦达玛路1150号(1150Damar Drive,Akron,OH),邮编44305;胶粘剂BSI.T14049A、胶粘剂BSI.D16052K,各自可购自布鲁尔科学(Brewer Science),密苏里州罗拉布鲁尔路2401号(2401Brewer Drive,Rolla,MO),邮编65401;或前体材料或其部分固化的变体)。粘合材料204的厚度可以是例如介于约0.5微米与约5微米之间以提供尽可能薄的粘合线,同时维持装置晶片200到载体晶片100的足够粘附性。作为具体的非限制性实例,粘合材料204的厚度可以是例如介于约2微米与约3微米之间(例如约2.5微米)。合乎需要的是,粘合材料204的厚度在装置晶片200粘合到其上之前和之后跨越载体结构100的表面106大体上均匀。
如图3中所展示,晶片组合件300被倒置,且牺牲材料102的暴露表面108通过用背面研磨设备402的研磨头400移除牺牲材料102的厚度的仅一部分来进行平面化。仅移除牺牲材料的部分厚度,例如约20μm的总厚度中的约12μm到约15μm,或例如约30μm总厚度中的约22μm到约25μm,使得牺牲材料102的剩余部分102′能够补偿表面104的构形中的非平面性。此类补偿提供充分平的表面以在不接触载体晶片100的表面104和从晶片移除材料的情况下用作装置晶片100的后续薄化和平面化的参考面。值得注意的是,比起用于薄化和平面化装置晶片200的过程,牺牲材料102的使用连同未涂布载体晶片100的平面化一起实现更便宜、粗略的研磨过程。牺牲材料102的平面化可充当装置晶片的后续厚度减小和平面化的更精确参考,从而有益于背侧处理以及可能发生的装置晶片200的其它处理和处置,这可产生更一致的可预测结果,从而增大成出率和减小跨越装置晶片的厚度变化。这实现裸片厚度的更少变化、在取放操作期间裸片上的更小应力,确保装置晶片200上的导电穿孔的成功暴露和完成,且总体上减小过程变化。
如图4中所展示,晶片组合件300同样被倒置,且装置晶片200的暴露主表面(例如非作用表面或背侧)206使用与用于平面化载体晶片100上的牺牲材料102相同的设备进行薄化和平面化。举例来说,装置晶片200可从约700μm到约800μm的初始厚度薄化到经薄化装置晶片200′的小于100μm(参看图5)、介于(例如)约50μm与约70μm之间的最终厚度,但装置晶片200可薄化到低于约50μm。所得的薄化装置晶片200′的总厚度变化(TTV)从约12μm到约15μm减小到低于约10μm,例如介于约7μm到约8μm之间或更低或例如约3μm。如本文所引用,TTV可表征为,垂直于经薄化装置晶片的平面化表面,所述表面构形的最低点与最高点之间的差。
如图5中所展示,经薄化晶片组合件300′被倒置,且可接着任选地从载体晶片100的表面104移除牺牲材料102的剩余部分102′。在进一步处理经薄化装置晶片200′之前是否需要移除牺牲材料102的剩余部分102′可考虑用于在进一步处理经薄化装置晶片200′之后从所述经薄化装置晶片移除载体晶片100的技术,如下文所描述。如果需要,那么合适的移除技术取决于用于牺牲材料102的材料,且包含但不限于湿法(溶剂剥离)蚀刻和干法(反应离子)蚀刻。
如图6中所展示,再次倒置经薄化晶片组合件300′,使得可在经平面化背侧206′上实现经薄化装置晶片200′的常规背侧处理。此类背侧处理可包含例如:重布层(RDL)的形成,所述重布层包括连接到通过装置晶片200的薄化而暴露的穿透衬底通孔(TSV)的导电迹线;钝化层以及任选的焊接掩模层的形成;以及导电元件的形成,所述导电元件呈导电柱、列、凸块或短柱或焊料凸块形式,延伸贯穿钝化层以及任选的焊接掩模层的开口。
如图7中所展示,在完成背侧处理之后,再次倒置晶片组合件300′,且将经薄化装置晶片200′固定到支撑结构500,使得经薄化装置晶片200′可准备好用于载体晶片100的后续移除。举例来说,晶片组合件300′可临时支撑在支撑结构500上,支撑结构500位于经薄化装置晶片200′的与载体晶片100相对的一侧。支撑结构500可配置为例如膜框架、引线框架、胶带或与最初固定到装置晶片200的载体晶片100不同的其它结构。经薄化装置晶片200′可在重力影响下仅仅搁置在支撑结构400上,其中支撑结构500位于经薄化装置晶片200′下方,或经薄化装置晶片200′可临时以任何合适的定向固定到支撑结构500。在支撑结构500被配置为膜框架的实施例中,支撑结构400可包含例如侧向包围经薄化晶片组合件300′的环形外围框架502以及固定到环形框架502的膜504,膜504位置邻近且在一些实施例中临时粘附固定到经薄化装置晶片200′的平面化背侧表面206′。
载体晶片100从经薄化装置晶片200′脱粘可通过数个常规粘合材料相关技术来实现,包含但不限于机械分离、紫外光(UV)固化和脱离、热固化和脱离、热滑动、化学活化或溶剂溶胀或激光活化。载体晶片100与经薄化装置晶片200′之间的粘合可在移除载体晶片100之前通过常规技术进行弱化或消除以促进载体晶片100的移除。取决于所用的牺牲材料102,例如UV固化和脱离或激光活化的一些脱粘技术可能需要从载体晶片的表面104移除牺牲材料102的剩余部分102′以允许经施加以弱化粘合材料204所提供的载体晶片100与经薄化装置晶片200′之间的粘合的能量有效地通过表面104穿透载体晶片100。然而,在其它情况下,可能在牺牲材料102的剩余部分102′处于完整状态的情况下移除载体晶片。举例来说,可通过侧向滑动或通过从经薄化装置晶片200′的一个边缘朝向另一边缘(即,提举载体晶片100的边缘)从固定到支撑结构500的经薄化装置晶片200′缓慢剥离载体晶片100来移除载体晶片100。在脱粘之后,可对载体晶片100进行清理(若存在,包含任何牺牲材料102),将新的牺牲材料102涂覆到其表面且重新用于处理新的装置晶片200。可清除经薄化装置晶片200′作用表面202上的残余粘合材料204,通过常规技术对其进行半导体裸片单分,且可通过例如常规取放设备从支撑结构400移除单分的半导体裸片或包含多个裸片的其它晶片片段。
本公开的实施例可表征为一种处理装置晶片的方法,所述方法包括:将牺牲材料涂覆于载体晶片的表面;将所述装置晶片的表面粘附到所述载体晶片的相对表面;通过仅移除所述牺牲材料的厚度的一部分来平面化所述牺牲材料的暴露表面;以及平面化所述装置晶片的相对表面。
本公开的另一实施例可表征为一种处理装置晶片的方法,其包括在不移除载体晶片材料的情况下平面化粘合到装置晶片的载体晶片的暴露表面,以及从装置晶片的暴露表面处减小装置晶片的厚度且在减小厚度之后平面化所述装置晶片的暴露表面。
本公开的另一实施例可表征为一种晶片组合件,其包括:载体晶片,其在其表面上具有大体上均匀的牺牲材料涂层;以及装置晶片,其粘合到所述载体晶片的未涂布的相对表面。
虽然已结合图式描述了某些说明性实施例,但所属领域的技术人员应认识到且了解,本公开的范围不限于在本公开中明确展示和描述的那些实施例。实际上,可对本公开中所描述的实施例作出许多添加、删除和修改以产生本公开范围内的实施例,例如特别主张的那些实施例,包含法定等同方案。另外,一个公开实施例的特征可与另一公开实施例的特征组合,同时仍然处于本公开的范围内。

Claims (23)

1.一种处理装置晶片的方法,所述方法包括:
将牺牲材料涂覆到载体晶片的表面;
将所述装置晶片的表面粘附到所述载体晶片的相对表面;
通过仅移除所述牺牲材料厚度的一部分来平面化所述牺牲材料的暴露表面;以及
平面化所述装置晶片的相对表面。
2.根据权利要求1所述的方法,其中平面化所述装置晶片的所述相对表面包括将所述装置晶片的初始厚度从700μm到800μm的范围减小到小于100μm。
3.根据权利要求1所述的方法,其中将牺牲材料涂覆到载体晶片的表面包括将牺牲材料涂覆到介于15μm与30μm之间的厚度。
4.根据权利要求3所述的方法,其中仅移除所述牺牲材料的厚度的一部分包括移除介于12μm与15μm之间的所述厚度。
5.根据权利要求1所述的方法,其中将牺牲材料涂覆到载体晶片的表面包括涂覆光致抗蚀剂、旋涂式电介质SOD材料、抗反射涂层ARC材料、氧化硅材料或氮化硅材料中的至少一种。
6.根据权利要求1所述的方法,其中将牺牲材料涂覆到载体晶片的表面包括将牺牲材料涂覆到包括半导体材料或玻璃材料的晶片。
7.根据权利要求1所述的方法,其进一步包括:
将所述装置晶片的所述相对表面固定到支撑件;
从所述装置晶片移除所述载体晶片;以及
从所述装置晶片单分半导体裸片。
8.根据权利要求7所述的方法,其进一步包括在从所述装置晶片移除所述载体晶片之前移除所述载体晶片的所述表面上的任何剩余的牺牲材料。
9.根据权利要求7所述的方法,其中将所述装置晶片的所述相对表面固定到支撑件包括将所述装置晶片的所述相对表面粘附到由膜框架支撑的膜。
10.根据权利要求1所述的方法,其中平面化装置晶片的相对表面包括将所述装置晶片的所述相对表面平面化到介于3μm与8μm之间的总厚度变化TTV。
11.一种处理装置晶片的方法,其包括:
平面化粘合到装置晶片的载体晶片的暴露表面而不从所述载体晶片移除材料;以及
从所述装置晶片的暴露表面处减小所述装置晶片的厚度,且在已减小所述厚度之后平面化所述装置晶片的暴露表面。
12.根据权利要求11所述的方法,其进一步包括:
在将所述装置晶片粘合到所述载体晶片之前,将牺牲材料涂覆到所述载体晶片的表面;以及所述方法进一步包括将所述装置晶片粘合到所述载体晶片的未涂布有所述牺牲材料的表面。
13.根据权利要求12所述的方法其进一步包括:
通过利用工具研磨掉所述牺牲材料的厚度的一部分来平面化所述载体晶片的所述暴露表面;以及
通过使用相同的所述工具研磨来减小所述装置晶片的厚度和平面化所述装置晶片。
14.根据权利要求12所述的方法,其中将牺牲材料涂覆到所述载体晶片的表面包括涂覆光致抗蚀剂、旋涂式电介质SOD材料、抗反射涂层ARC材料、氧化硅材料或氮化硅材料中的至少一种。
15.根据权利要求13所述的方法,其进一步包括将所述牺牲材料涂覆到介于15μm与30μm之间的厚度,且研磨掉所述牺牲材料的厚度的一部分包括移除12μm到15μm的所述厚度。
16.根据权利要求13所述的方法,其进一步包括从所述平面化装置晶片移除所述载体晶片,同时所述牺牲材料的一部分保持在所述载体晶片上。
17.根据权利要求13所述的方法其进一步包括:
从所述载体晶片移除所述牺牲材料的任何剩余部分;以及
接着从所述装置晶片移除所述载体晶片。
18.一种晶片组合件,其包括:
载体晶片,其在其表面上具有大体上均匀的牺牲材料涂层,其中将所述牺牲材料的暴露表面平面化;以及
装置晶片,其粘合到所述载体晶片未涂布的相对表面,其中将所述装置晶片的暴露表面平面化。
19.根据权利要求18所述的晶片组合件,其中所述牺牲材料包括光致抗蚀剂、旋涂式电介质SOD材料、抗反射涂层ARC材料、氧化硅材料或氮化硅材料中的至少一种。
20.根据权利要求18所述的晶片组合件,其中所述牺牲材料的厚度低于20μm,且所述装置晶片的所述暴露表面的总厚度变化TTV低于8μm。
21.根据权利要求18所述的晶片组合件,其中所述装置晶片具有低于100μm的厚度。
22.根据权利要求18所述的晶片组合件,其中所述装置晶片的所述暴露表面呈现介于3μm与8μm之间的总厚度变化TTV。
23.一种晶片组合件,其包括:
载体晶片,其具有未涂布有任何材料的暴露表面;以及
厚度低于100μm的装置晶片,其粘合到所述载体晶片的相对表面;
所述装置晶片在其与所述载体晶片相对的暴露表面上呈现低于8μm的总厚度变化。
CN201810933189.8A 2017-08-18 2018-08-16 用于处理半导体装置结构的方法和设备 Active CN109411359B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/680,461 2017-08-18
US15/680,461 US10326044B2 (en) 2017-08-18 2017-08-18 Method and apparatus for processing semiconductor device structures

Publications (2)

Publication Number Publication Date
CN109411359A CN109411359A (zh) 2019-03-01
CN109411359B true CN109411359B (zh) 2022-09-30

Family

ID=65360311

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810933189.8A Active CN109411359B (zh) 2017-08-18 2018-08-16 用于处理半导体装置结构的方法和设备

Country Status (2)

Country Link
US (2) US10326044B2 (zh)
CN (1) CN109411359B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10326044B2 (en) * 2017-08-18 2019-06-18 Micron Technology, Inc. Method and apparatus for processing semiconductor device structures

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US193309A (en) * 1877-07-17 Improvement in mechanisms for shifting drop shuttle-boxes in looms
US326044A (en) * 1885-09-08 Inkstand
US170559A (en) * 1875-11-30 Improvement in pad-saddles
US6596639B1 (en) 1999-10-08 2003-07-22 Agere Systems Inc. Method for chemical/mechanical planarization of a semiconductor wafer having dissimilar metal pattern densities
US7064069B2 (en) 2003-10-21 2006-06-20 Micron Technology, Inc. Substrate thinning including planarization
US7977211B2 (en) * 2007-04-17 2011-07-12 Imec Method for reducing the thickness of substrates
WO2009094558A2 (en) * 2008-01-24 2009-07-30 Brewer Science Inc. Method for reversibly mounting a device wafer to a carrier substrate
KR101500684B1 (ko) * 2008-04-17 2015-03-10 삼성디스플레이 주식회사 캐리어 기판 및 이를 이용한 가요성 표시 장치의 제조 방법
US7883991B1 (en) * 2010-02-18 2011-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Temporary carrier bonding and detaching processes
CN102157426B (zh) * 2011-01-28 2015-10-07 上海华虹宏力半导体制造有限公司 晶片支撑装置及晶片处理工艺
US8970045B2 (en) * 2011-03-31 2015-03-03 Soitec Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices
FR2977069B1 (fr) * 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
US20130168803A1 (en) * 2011-09-16 2013-07-04 Sionyx, Inc. Semiconductor-On-Insulator Devices and Associated Methods
WO2013123241A1 (en) * 2012-02-17 2013-08-22 The Regents Of The University Of California Method for the reuse of gallium nitride epitaxial substrates
KR101868867B1 (ko) * 2012-06-28 2018-06-19 엘지디스플레이 주식회사 플렉서블 표시장치의 제조 방법
US8941215B2 (en) * 2012-09-24 2015-01-27 LuxVue Technology Corporation Micro device stabilization post
WO2015009669A1 (en) * 2013-07-16 2015-01-22 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Lift-off of epitaxial layers from silicon carbide or compound semiconductor substrates
US9401303B2 (en) * 2014-08-01 2016-07-26 Globalfoundries Inc. Handler wafer removal by use of sacrificial inert layer
US9478453B2 (en) * 2014-09-17 2016-10-25 International Business Machines Corporation Sacrificial carrier dicing of semiconductor wafers
US9246311B1 (en) * 2014-11-06 2016-01-26 Soraa Laser Diode, Inc. Method of manufacture for an ultraviolet laser diode
US9915567B2 (en) * 2016-06-28 2018-03-13 Excelitas Technologies Singapore Pte. Ltd. Unreleased thermopile infrared sensor using material transfer method
US10170559B1 (en) * 2017-06-29 2019-01-01 Alpha And Omega Semiconductor (Cayman) Ltd. Reverse conducting IGBT incorporating epitaxial layer field stop zone and fabrication method
US20190006461A1 (en) * 2017-06-29 2019-01-03 Alpha And Omega Semiconductor (Cayman) Ltd. Semiconductor device incorporating epitaxial layer field stop zone
US10833021B2 (en) * 2017-06-29 2020-11-10 Alpha And Omega Semiconductor (Cayman) Ltd. Method for precisely aligning backside pattern to frontside pattern of a semiconductor wafer
US10326044B2 (en) * 2017-08-18 2019-06-18 Micron Technology, Inc. Method and apparatus for processing semiconductor device structures

Also Published As

Publication number Publication date
US20190057901A1 (en) 2019-02-21
US10749071B2 (en) 2020-08-18
US20190252575A1 (en) 2019-08-15
US10326044B2 (en) 2019-06-18
CN109411359A (zh) 2019-03-01

Similar Documents

Publication Publication Date Title
KR102050541B1 (ko) 초박막 웨이퍼의 임시 본딩을 위한 방법 및 장치
US9991150B2 (en) Procedure of processing a workpiece and an apparatus designed for the procedure
US6940181B2 (en) Thinned, strengthened semiconductor substrates and packages including same
US7064069B2 (en) Substrate thinning including planarization
KR101656376B1 (ko) 얇은 웨이퍼 캐리어
EP3159919B1 (en) A procedure of processing a workpiece and an apparatus designed for the procedure
US8846499B2 (en) Composite carrier structure
CN109390281B (zh) 半导体装置结构和其处理方法与系统
US11361969B2 (en) Device substrate with high thermal conductivity and method of manufacturing the same
US8574398B2 (en) Apparatus and method for detaping an adhesive layer from the surface of ultra thin wafers
CN109712926B (zh) 一种半导体器件的制造方法
TW201921460A (zh) 基板處理方法
CN109411359B (zh) 用于处理半导体装置结构的方法和设备
CN111834277A (zh) 用于晶片处置和处理的方法和设备
EP4166620A1 (en) Temporary bonding method, device wafer processing method, laminate for temporary bonding, and laminate for device wafer processing
US9997390B2 (en) Semiconductor manufacturing method and laminated body
US9082713B2 (en) Method of grinding wafer stacks to provide uniform residual silicon thickness
Thompson et al. A Multistep Process for Thinning Individual Die to sub-35 μm Thickness

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant