CN102714207B - 双功函数栅极结构 - Google Patents

双功函数栅极结构 Download PDF

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CN102714207B
CN102714207B CN201080053547.8A CN201080053547A CN102714207B CN 102714207 B CN102714207 B CN 102714207B CN 201080053547 A CN201080053547 A CN 201080053547A CN 102714207 B CN102714207 B CN 102714207B
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W·M·哈菲兹
A·拉赫曼
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Abstract

描述了一种具有晶体管的半导体芯片。所述晶体管具有设置在栅极电介质上的栅极电极。所述栅极电极包括设置在所述栅极电介质上的第一栅极材料和设置在所述栅极电介质上的第二栅极材料。第一栅极材料不同于第二栅极材料。第二栅极材料也位于所述栅极电极的源极区域或漏极区域处。

Description

双功函数栅极结构
技术领域
本发明的领域总地涉及半导体器件，并且更重要地涉及双功函数栅极结构。
背景技术
图1和2提供了关于诸如CMOS等互补型半导体器件技术的相关细节。图1示出了处于平衡的NMOS器件和PMOS器件两者的MOS结构的能带图。根据图1的方法（其为通常的方法），两种器件都设计为使得：处于平衡时，高K电介质102_N/NMOSP-势阱103_N界面的费米能级和高K电介质102_P/PMOSN-势阱103_P界面的费米能级在导带（Ec）与价带（Ev）之间的大约一半处。在这里，平衡实质上对应于“截止”器件，并且在Ec与Ev之间的一半处设置费米能级将器件保持在其最小的导通状态（因为导带大量缺乏自由电子，并且价带大量缺乏自由空穴）。
为了如上所述地将费米能级设置在Ec与Ev之间的一半处，选择了特定的栅极金属材料，所述栅极金属材料在NMOSP-势阱103_N和PMOSN-势阱103_P中引起适当的能带弯曲（bandbending）量。尤其，为了获得期望的能带弯曲，用于NMOS栅极101_N的材料的功函数104_N通常小于用于PMOS栅极104_P的材料的功函数（即，PMOS功函数104_P通常大于NMOS功函数104_N）。
图2示出在激活状态而非截止状态下的图1的器件。在NMOS器件的情况下，正的栅极到源极电压主要导致额外的能带弯曲，所述额外的能带弯曲将导带置于电介质/势阱界面205_N处的费米能级之下。当导带Ec在费米能级之下时，存在大量的自由电子。因此，在对应于“导通”器件的界面205_N处形成导通沟道。同样地，在PMOS器件的情况下，负的栅极到源极电压主要导致额外的能带弯曲，所述额外的能带弯曲将价带置于电介质/势阱界面205_P处的费米能级之上。当价带Ev在费米能级之上时，存在大量自由空穴。因此，在对应于“导通”器件的界面205_P处形成了导通沟道。
附图说明
通过示例而非限制的方式在附图的图示中示出了本发明，在附图中相似的附图标记指代类似的元素，并且在附图中：
图1示出了处于平衡的常规NMOS和PMOS器件；
图2示出了在激活模式下的常规NMOS和PMOS器件；
图3a和3b示出了沿常规NMOS器件的沟道的能带图；
图4a和4b示出了沿改进的NMOS器件的沟道的能带图；
图5a和5b示出了沿改进的PMOS器件的沟道的能带弯曲图；
图6a至6f示出了常规双金属栅极制造过程；
图7a至7f示出了能够制造图4a、4b和5a、5b的改进的器件的双金属栅极制造过程；
图8a示出了均具有双金属栅极的非对称NMOS和PMOS器件的实施例；
图8b示出了具有双金属栅极的垂直漏极NMOS（VDNMOS）器件的实施例；
图8c示出了具有双金属栅极的横向扩散MOS（LDMOS）器件的实施例。
具体实施方式
图3a和3b示出了沿针对图1和2a所描述的NMOS器件的沟道的能带图。图3a对应于“截止”器件而图3b则对应于“导通”器件。参考图3a，n+源极/漏极延伸（extension）的存在导致P势阱内的能带弯曲301。当先前几代器件中的栅极长度较长时，能带弯曲301仅表示栅极之下的P势阱内的能带轮廓的小部分。然而，随着栅极长度的持续缩短，能带弯曲301表示栅极之下的能带轮廓的越来越大的百分比，并且能带弯曲301的效应变得越来越显著。例如，能带弯曲301的存在被认为有助于减小阈值电压。
参考图3b，n+漏极延伸的存在导致在P势阱和n+漏极延伸的界面处/附近的尖锐的能带弯曲302。尖锐的弯曲302对应于极高的电场，所述极高的电场被认为导致了大量与“热载流子”有关的问题，诸如衬底电流、雪崩击穿、降低的能量势垒和阈值偏移。
图4a和4b示出了与图3a和3b的NMOS器件相比，在栅极电极之下具有改进的能带弯曲特性的NMOS器件的设计。图4a示出了在截止状态下的器件，而图4b则示出了在导通状态下的器件。
尤其，能够将器件的栅极结构视为具有三个部分：1）外部部分402a和402b；以及2）内部部分403。在实施例中，对于如在图4a和4b中所观察到的N型器件而言，外部部分402a和402b由P型器件栅极金属构成，而内部部分403则由N型器件栅极金属构成。因此，外部部分402a、402b的功函数高于内部部分403的功函数。
在此情况下，在栅极的外部区域402a、402b处的较高功函数材料的效应类似于针对图1的PMOS器件所观察到的效应。即，与图3a中所观察到的能级相比，较高的功函数材料引起能带弯曲，所述能带弯曲相对于费米能级“向上”牵引导带和价带。同样地，图4a的截止器件在P势阱/延伸界面区域具有比在图3a的器件中所观察到的能带弯曲301更小的能带弯曲401。因此，实际上消除或减少了由n+源极/漏极延伸的存在所导致的阈值电压降低。
类似地，参考图4b，与图3b的器件相比，由较高功函数材料402b所引起的对价带和导带的向上牵引导致了在导通器件中的P势阱/n+漏极延伸处/附近的较不尖锐的能带弯曲404。所述较不尖锐的能带弯曲404对应于会减小“热载流子”效应的较弱电场。能带弯曲也在P势阱/n+源极延伸处产生。如在图4b中所观察到的，产生了小势垒，然而，通过适当选择掺杂水平和栅极金属材料，可以最小化或消除所述势垒。
图5a和5b示出了与现有技术的PMOS器件相比，在栅极电极之下具有改进的能带弯曲特性的PMOS器件的设计。图5a示出了截止状态下的器件，而图5b则示出了导通状态下的器件。
尤其，能够将器件的栅极结构视为具有三个部分：1）外部部分502a和502b；以及2）内部部分503。在实施例中，对于在图5a和5b中所观察到的P型器件而言，外部部分502a和502b由N型器件栅极金属构成，而内部部分503则由P型器件栅极金属构成。因此，外部部分502a、502b具有比内部部分503更低的功函数。
在此情况下，在栅极的外部区域502a、502b处的较低功函数材料的效应类似于针对图1的NMOS器件所观察到的效应。即，较低的功函数材料引起能带弯曲，所述能带弯曲相对于费米能级“向下”牵引导带和价带。同样地，图5a的截止器件在N势阱/延伸界面区域处的能带弯曲501小于现有技术（单栅极金属）的PMOS器件中在N势阱/延伸界面区域处的对应的能带弯曲。因此，实际上消除或减少了由p+源极/漏极延伸的存在所导致的阈值电压降低。
类似地，参考图5b，与现有技术（单栅极金属）的PMOS器件相比，由较低功函数材料502B所引起的在价带和导带上的向下牵引导致了在导通器件中的N势阱/p+漏极延伸处/附近的较不尖锐的能带弯曲504。所述较不尖锐的能带弯曲504对应于会减小“热载流子”效应的较弱电场。能带弯曲也在N势阱/p+源极延伸处产生。如图5b中所观察到的，产生了小势垒，然而，通过适当选择掺杂水平和栅极金属材料，可以最小化或消除所述势垒。
相关地指出的是，虽然以上参考图4a、4b和5a、5b使用了术语“NMOS”和“PMOS”（通常理解为分别指代N型金属氧化物半导体器件和P型金属氧化物半导体器件），但是出于方便的考虑，应当将这些术语理解为也适用于具有从技术上讲不是氧化物的栅极电介质的器件。也可以使用术语“N型器件”和“P型器件”。而且，虽然以上参考图4a、4b和5a、5b使用了术语“栅极金属”，但是应当将术语“栅极金属”理解为适用于从技术上讲不是金属的栅极材料（诸如重掺杂的多晶硅）。也可以使用术语“栅极材料”、“栅极电极”、“栅极电极材料”，等等。另外，出于方便的考虑，器件图未描绘公知的器件结构，诸如源极/漏极电极（理解为电耦合至它们各自的源极/漏极延伸）、位于所描绘的器件的栅极金属上的金属栅极填充材料、侧壁间隔体，等等。
图6a至6f示出了用于制造具有不同的相应的栅极金属的NMOS和PMOS器件的现有技术过程。图6a示出了经过栅极电介质601a、b的沉积的NMOS和PMOS器件。在图6b中，用于NMOS器件的栅极金属602a、b沉积在两个器件的栅极电介质601a、b上。然后，如图6c中所观察到的，将光刻胶603a、b涂覆在晶圆上并对其进行构图，以在PMOS器件的栅极区域上形成开口604，从而将位于PMOS器件中的NMOS栅极金属602b暴露出来。NMOS器件上的NMOS栅极材料602a由光刻胶603a覆盖。
如图6d中所观察到的，蚀刻掉PMOS器件的栅极区域中的暴露的NMOS栅极金属602b。在蚀刻期间，由光刻胶603a保护NMOS器件的栅极区域中的NMOS栅极金属602a。如图6E中所观察到的，PMOS栅极金属605沉积在PMOS器件的栅极电介质上。如图6f中所观察到的，去除了光刻胶603a、b，而在NMOS器件的栅极区域中留下NMOS栅极材料602a并在PMOS器件的区域中留下PMOS栅极材料605。如图6f中所观察到的，所制造的器件在栅极电介质上仅具有一个栅极金属。
相比之下，图7a至7f则示出了能够制造在单个器件的栅极电介质上具有多于一个栅极材料的器件的过程。图7a示出了经过栅极电介质701a、701b的沉积的N型和P型器件。在图7b中，N型栅极材料702a、b沉积在两个器件的栅极电介质上。如图7c中所观察到的，将光刻胶703a、b涂覆在晶圆上并对其进行构图，以在N型器件的栅极边缘上形成开口对704，在P型器件的栅极中央上形成单个开口705。每个开口均暴露下方的N型栅极材料702a、b。随后，蚀刻暴露出来的N型栅极材料702b。可以用诸如基于HCl或基于SF-6的蚀刻等干法蚀刻来进行蚀刻。
当去除暴露的N型栅极材料时，P型栅极材料706a、b沉积在如图7e中所观察到的其位置中。随后去除光刻胶，从而留下在栅极电介质上具有N型和P型栅极金属的器件。
尤其，在替代方法中，可以在沉积N型栅极材料之前沉积P型栅极材料。在此情况下，与图7b相比，光刻胶图案是“交换的”（即，P型器件将具有开口对而N型器件将具有单个开口）。
用于栅极材料的材料类型可以根据实施例而变化。如以上所讨论的，根据一种方法，用于P型器件的栅极材料（“P型栅极材料”）不仅沉积在P型器件的栅极电介质上，而且沉积在N型器件的栅极电介质上。同样地，用于N型器件的栅极材料（“N型栅极材料”）不仅沉积在N型器件的栅极电介质上，而且沉积在P型器件的栅极电介质上。通常，如以上所讨论的，P型栅极材料具有比N型栅极材料更高的功函数。合适的栅极材料可以包括但不限于多晶硅、钨、钌、钯、铂、钴、镍、铪、锆、钛、钽、铝、碳化钛、碳化锆、碳化钽、碳化铪、碳化铝、其它金属碳化物、金属氮化物和金属氧化物。如本领域公知的，可以由诸如化学气相沉积或原子层沉积或溅射等各种处理来沉积栅极材料。
虽然当P型栅极材料沉积在P型器件和N型器件两者上，并且N型栅极材料沉积在N型器件和P型器件两者上时，实现了就处理步骤数量（numberprocessstep）而言的效率——替代方法可以使用仅在器件之一（N型或P型）上使用的栅极金属，以设计期望的能带弯曲。当被授权使用（bewarranted）这种方法的时候，本领域技术人员能够确定应用和材料。
此外，在实施例中，器件的栅极长度比用所述制造过程可实现的最小栅极长度更长。例如，在逻辑处理中，通常，逻辑晶体管的最小制造特征是栅极长度。因此，具有如在这里描述的栅极结构的器件的栅极长度比逻辑晶体管的栅极长度更长（因为在如以上讨论的单个栅极上形成多个特征，而不是如在逻辑晶体管的情况下的单个的、最小的制造特征）。例如，根据一个实施例，具有在这里描述的栅极结构的器件用于实施较高电压的模拟和/或混合信号电路。这种器件可以集成在具有拥有最小特征栅极长度的逻辑晶体管的相同半导体器件上。例如，具有数字部件（例如处理核、存储器，等等）和模拟/混合信号部件（例如，放大器、I/O驱动器，等等）的片上系统（SOC）可以使用具有如在这里描述的用于模拟/混合信号部件的栅极结构的器件。
相关地指出的是，虽然以上讨论的示例示出了具有下方源极/漏极延伸尖端的外部栅极边缘金属的严格对准，但是这种方法仅是示例性的。只要实现了适当的能带弯曲，双栅极金属结构的内部栅极金属与外部栅极金属之间的边界的定位就可以变化。而且，如图8a所示（以下马上会更详细地讨论），一些器件设计可以仅在边缘之一上（例如，仅在源极侧上或仅在漏极侧上）具有不同的外部边缘栅极材料。例如，主要涉及热载流子效应的器件设计可以选择将不同的外部边缘栅极材料设置在栅极的漏极侧上而不设置在栅极的源极侧上。同样地，较少涉及热载流子效应而较多涉及栅极的源极端之下的大体上非平坦的能带结构的器件设计可以选择仅将不同的栅极材料添加到栅极的源极侧上而不添加到栅极的漏极侧上。
此外，虽然以上讨论的示例表明，在源极和漏极处都存在有不同的外部边缘栅极材料的情况下，在两个边缘上使用相同的栅极材料，但是在所述一对外部边缘栅极材料本身之间是不同的情况下，可以存在替代的器件设计。例如，第一外部边缘栅极材料可以用在栅极的源极侧，以控制栅极的源极侧之下的势垒高度（图4b中所观察的），而第二外部边缘栅极材料（不同于在源极侧上所使用的栅极材料）可以用在漏极侧，以减小势阱与漏极结之间的电场。
图8a至8c示出了可以由在这里描述的双金属栅极结构形成的各种晶体管。图8a示出了N型非对称器件和P型非对称器件。尤其，这些器件仅在漏极侧附近而非源极侧附近包含不同的外部边缘金属（具体地，用于N型器件的P型栅极金属和用于P型器件的N型栅极金属）。同样地，这些器件仅试图给出减小势阱/漏极延伸附近的电场的能带弯曲。
图8b示出了具有双金属栅极结构的垂直漏极NMOS器件（VDNMOS）。如本领域公知的，VDNMOS器件通过在栅极的漏极边缘之下插入绝缘材料801来解决势阱与漏极结之间的高电场的问题。沟槽801的所述插入产生了从外部（extrinsic）漏极接触到栅极边缘的高电阻路径，由此降低了在栅极之下的区域处的电场。此外，防止高掺杂漏极注入和尖端侵入栅极之下，这也减小了峰值电场。场中的这些减小转化为较低的载流子能量和增强的器件可靠性。
图8c示出了具有双金属栅极结构的横向扩散MOS（LDMOS）器件。如本领域公知的，LDMOS器件通过在场板802之下延伸漏极延伸（DEX）来解决势阱与漏极结之间具有高电场的问题。场板802用于在更大的漏极距离上扩展所述场，从而通过减小热载流子效应而有效地降低峰值场并且延长器件寿命。
在上述说明书中，已经参考其具体示例性实施例而描述了本发明。然而，显然可以在不脱离如所附权利要求中所阐述的本发明的更宽的精神和范围的情况下，对其作出各种修改和变化。因此，本说明书和附图应当视为说明性的意义而非限制性的意义。

Claims (10)

1.一种形成双功函数栅极结构的方法，包括：
通过以下步骤形成晶体管的栅极电极：
在栅极电介质的第一区域上沉积第一栅极材料；
在所述栅极电介质的第二区域上沉积第二栅极材料，所述第二栅极材料位于所述栅极电极的源极侧或漏极侧，所述第一栅极材料和所述第二栅极材料具有不同的功函数，所述晶体管是模拟或混合信号电路的部分；以及，
在与所述晶体管相同的半导体芯片上形成第二晶体管的第二栅极电极，所述第二栅极电极的长度小于所述电极的长度，所述第二晶体管是逻辑电路的部分，
其中所述方法还包括：在所述第一栅极材料的所述沉积之后和所述第二栅极材料的所述沉积之前：
用光刻胶涂覆所述第一栅极材料；
对所述光刻胶进行构图，以去除部分所述光刻胶并暴露所述第一栅极材料的区域；以及，
蚀刻所述第一栅极材料的所述区域，以暴露所述栅极电介质的所述第二区域，并且其中所述第一栅极材料和所述第二栅极材料在所述栅极电介质上彼此横向相邻。
2.根据权利要求1所述的形成双功函数栅极结构的方法，其中所述晶体管是N型晶体管，并且所述第一栅极材料的功函数比所述第二栅极材料低。
3.根据权利要求1所述的形成双功函数栅极结构的方法，其中所述晶体管是P型晶体管，并且所述第一栅极材料的功函数比所述第二栅极材料高。
4.根据权利要求1所述的形成双功函数栅极结构的方法，还包括通过以下步骤在其上形成有所述栅极电介质的同一半导体管芯上形成第二晶体管的第二栅极电极：
在所述第二晶体管的栅极电介质的第一区域上沉积所述第二栅极材料；
在所述第二晶体管的栅极电介质的第二区域上沉积所述第一栅极材料，所述第二晶体管的栅极电介质的所述第二区域上的所述第一栅极材料在所述第二栅极电极的源极侧或漏极侧。
5.一种半导体管芯，包括：
N型晶体管，所述N型晶体管具有设置在栅极电介质上的栅极电极，所述栅极电极包括设置在所述栅极电介质上的第一栅极材料和设置在所述栅极电介质上的第二栅极材料，所述第一栅极材料的功函数比所述第二栅极材料低，所述第二栅极材料也位于所述栅极电极的源极边缘或漏极区域处；
P型晶体管，所述P型晶体管具有设置在栅极电介质上的栅极电极，所述P型晶体管的栅极电极包括设置在所述P型晶体管的栅极电介质上的所述第一栅极材料和设置在所述P型晶体管的栅极电介质上的所述第二栅极材料，所述P型晶体管的第一栅极材料位于所述P型晶体管的栅极电极的源极边缘或漏极区域处，所述N型晶体管和所述P型晶体管是模拟和/或混合信号电路的部分；并且，
其它晶体管的各自的栅极长度小于所述N型晶体管和所述P型晶体管的栅极长度，所述其它晶体管是逻辑电路的部分。
6.根据权利要求5所述的半导体管芯，其中所述N型晶体管和所述P型晶体管是非对称晶体管。
7.根据权利要求5所述的半导体管芯，其中所述N型晶体管是垂直漏极晶体管。
8.根据权利要求5所述的半导体管芯，其中所述N型晶体管是横向扩散晶体管。
9.根据权利要求5所述的半导体管芯，其中所述N型晶体管和所述P型晶体管是模拟电路或混合信号电路的部分，所述半导体管芯也具有逻辑电路。
10.根据权利要求5所述的半导体管芯，其中所述第一栅极材料和所述第二栅极材料在它们各自的晶体管的各自的栅极电介质上彼此横向相邻。
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Families Citing this family (12)

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Publication number Priority date Publication date Assignee Title
CN102117831B (zh) * 2009-12-31 2013-03-13 中国科学院微电子研究所 晶体管及其制造方法
KR101783952B1 (ko) * 2011-01-12 2017-10-10 삼성전자주식회사 반도체 장치
JP2015032651A (ja) * 2013-08-01 2015-02-16 マイクロン テクノロジー， インク． 半導体装置
KR20200108930A (ko) 2013-09-27 2020-09-21 인텔 코포레이션 공통 기판 상의 상이한 일함수를 가지는 비-평면 ｉ／ｏ 및 논리 반도체 디바이스들
CN104600113A (zh) * 2013-10-31 2015-05-06 上海华虹宏力半导体制造有限公司 Ldmos器件
KR102202603B1 (ko) 2014-09-19 2021-01-14 삼성전자주식회사 반도체 장치 및 이의 제조 방법
JP2016149442A (ja) * 2015-02-12 2016-08-18 ソニー株式会社 トランジスタ、保護回路およびトランジスタの製造方法
JP6200103B2 (ja) 2015-10-15 2017-09-20 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置
JP6317507B2 (ja) * 2017-05-24 2018-04-25 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置
DE112017007824T5 (de) * 2017-09-26 2020-04-16 Intel Corporation Gruppe-iii-v-halbleitervorrichtungen mit gate-elektroden mit doppelter austrittsarbeit
FR3089343B1 (fr) * 2018-11-29 2021-10-08 Commissariat Energie Atomique Procede de realisation d’un transistor fet
CN114078957A (zh) * 2020-08-10 2022-02-22 华为技术有限公司 一种混合栅场效应管及制备方法、开关电路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0856892A2 (en) * 1997-01-30 1998-08-05 Oki Electric Industry Co., Ltd. MOSFET and manufacturing method thereof
CN1527398A (zh) * 2003-03-06 2004-09-08 北京大学 一种组合栅场效应晶体管

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2506963B2 (ja) * 1988-07-26 1996-06-12 松下電器産業株式会社 半導体装置
JPH04144238A (ja) * 1990-10-05 1992-05-18 Nippon Steel Corp Ｍｏｓ型半導体装置
US5091763A (en) * 1990-12-19 1992-02-25 Intel Corporation Self-aligned overlap MOSFET and method of fabrication
JPH05315605A (ja) * 1992-05-07 1993-11-26 Sony Corp Ｍｏｓ型半導体装置
JPH0661482A (ja) * 1992-08-07 1994-03-04 Sony Corp Ｍｏｓ型トランジスタおよびその製造方法
JP2842125B2 (ja) * 1993-02-04 1998-12-24 日本電気株式会社 電界効果型トランジスタの製造方法
US6225669B1 (en) * 1998-09-30 2001-05-01 Advanced Micro Devices, Inc. Non-uniform gate/dielectric field effect transistor
US6187657B1 (en) * 1999-03-24 2001-02-13 Advanced Micro Devices, Inc. Dual material gate MOSFET technique
US6187567B1 (en) * 1999-09-01 2001-02-13 Akzo Nobel N.V. Methods and reagents for in situ amplification
JP2002151652A (ja) * 2000-11-10 2002-05-24 Hitachi Ltd 半導体集積回路装置
US6858483B2 (en) * 2002-12-20 2005-02-22 Intel Corporation Integrating n-type and p-type metal gate transistors
JP4477886B2 (ja) * 2003-04-28 2010-06-09 株式会社ルネサステクノロジ 半導体装置の製造方法
JP4485932B2 (ja) * 2003-12-31 2010-06-23 東部エレクトロニクス株式会社 フラッシュメモリ素子そしてこれを用いたプログラミング及び消去方法
KR100724563B1 (ko) * 2005-04-29 2007-06-04 삼성전자주식회사 다중 일함수 금속 질화물 게이트 전극을 갖는 모스트랜지스터들, 이를 채택하는 씨모스 집적회로 소자들 및그 제조방법들
US20080180160A1 (en) * 2007-01-31 2008-07-31 Infineon Technologies Ag High voltage dual gate cmos switching device and method
JP2008227365A (ja) * 2007-03-15 2008-09-25 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7605601B2 (en) * 2007-04-19 2009-10-20 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
US20080308870A1 (en) * 2007-06-15 2008-12-18 Qimonda Ag Integrated circuit with a split function gate
JP2009123944A (ja) * 2007-11-15 2009-06-04 Panasonic Corp 半導体装置及びその製造方法
US20090142915A1 (en) * 2007-12-04 2009-06-04 Weize Xiong Gate structure and method of forming the same
US7635648B2 (en) * 2008-04-10 2009-12-22 Applied Materials, Inc. Methods for fabricating dual material gate in a semiconductor device
US8003463B2 (en) * 2008-08-15 2011-08-23 International Business Machines Corporation Structure, design structure and method of manufacturing dual metal gate Vt roll-up structure
US8101471B2 (en) * 2008-12-30 2012-01-24 Intel Corporation Method of forming programmable anti-fuse element
JP2011129690A (ja) * 2009-12-17 2011-06-30 Toshiba Corp 半導体装置の製造方法および半導体装置
US8487376B2 (en) * 2010-08-18 2013-07-16 Intel Corporation High-voltage transistor architectures, processes of forming same, and systems containing same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0856892A2 (en) * 1997-01-30 1998-08-05 Oki Electric Industry Co., Ltd. MOSFET and manufacturing method thereof
CN1527398A (zh) * 2003-03-06 2004-09-08 北京大学 一种组合栅场效应晶体管

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