CN102714201B - 半导体封装和方法 - Google Patents

半导体封装和方法 Download PDF

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Publication number
CN102714201B
CN102714201B CN201080061500.6A CN201080061500A CN102714201B CN 102714201 B CN102714201 B CN 102714201B CN 201080061500 A CN201080061500 A CN 201080061500A CN 102714201 B CN102714201 B CN 102714201B
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China
Prior art keywords
leads
leadframe
dies
die
lead
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Chinese (zh)
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CN102714201A (zh
Inventor
S.乔内伊
S.贝拉尼
F.郭
S.毛
P.王
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Vishay Siliconix Inc
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Vishay Siliconix Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for individual devices of subclass H10D
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
CN201080061500.6A 2010-01-19 2010-12-07 半导体封装和方法 Active CN102714201B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US29647110P 2010-01-19 2010-01-19
US61/296,471 2010-01-19
US12/730,230 2010-03-24
US12/730,230 US8586419B2 (en) 2010-01-19 2010-03-24 Semiconductor packages including die and L-shaped lead and method of manufacture
PCT/US2010/059326 WO2011090574A2 (en) 2010-01-19 2010-12-07 Semiconductor package and method

Publications (2)

Publication Number Publication Date
CN102714201A CN102714201A (zh) 2012-10-03
CN102714201B true CN102714201B (zh) 2015-12-09

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US (1) US8586419B2 (enExample)
EP (1) EP2526565B1 (enExample)
JP (2) JP5607758B2 (enExample)
KR (1) KR101534463B1 (enExample)
CN (1) CN102714201B (enExample)
WO (1) WO2011090574A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12142548B2 (en) * 2021-12-30 2024-11-12 Alpha And Omega Semiconductor International Lp Semiconductor package having mold locking feature

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI453831B (zh) 2010-09-09 2014-09-21 台灣捷康綜合有限公司 半導體封裝結構及其製造方法
JP5333402B2 (ja) * 2010-10-06 2013-11-06 三菱電機株式会社 半導体装置の製造方法
CN102394232A (zh) * 2011-11-29 2012-03-28 杭州矽力杰半导体技术有限公司 一种引线框架及应用其的芯片倒装封装装置
US9589929B2 (en) 2013-03-14 2017-03-07 Vishay-Siliconix Method for fabricating stack die package
US9966330B2 (en) 2013-03-14 2018-05-08 Vishay-Siliconix Stack die package
KR101742896B1 (ko) * 2013-03-14 2017-06-01 비쉐이-실리코닉스 스택 다이 패키지의 제조 방법
CN103395735B (zh) * 2013-08-05 2015-12-02 天津大学 微机电系统器件的封装结构
CN103646937B (zh) * 2013-12-05 2016-02-24 江苏长电科技股份有限公司 二次先蚀后镀金属框减法埋芯片倒装凸点结构及工艺方法
CN103646938B (zh) * 2013-12-05 2016-02-24 江苏长电科技股份有限公司 一次先镀后蚀金属框减法埋芯片倒装凸点结构及工艺方法
CN103681582B (zh) * 2013-12-05 2016-03-30 江苏长电科技股份有限公司 一次先蚀后镀金属框减法埋芯片正装凸点结构及工艺方法
CN103646931B (zh) * 2013-12-05 2016-06-29 江苏长电科技股份有限公司 一次先镀后蚀金属框减法埋芯片倒装平脚结构及工艺方法
CN103646930B (zh) * 2013-12-05 2016-02-24 江苏长电科技股份有限公司 二次先蚀后镀金属框减法埋芯片倒装平脚结构及工艺方法
JP2015176871A (ja) * 2014-03-12 2015-10-05 株式会社東芝 半導体装置及びその製造方法
US9425304B2 (en) 2014-08-21 2016-08-23 Vishay-Siliconix Transistor structure with improved unclamped inductive switching immunity
CN104952737B (zh) * 2015-06-30 2017-12-26 通富微电子股份有限公司 一种具有铝带或l脚或凸起的封装框架结构及生产方法
KR101734712B1 (ko) * 2015-12-09 2017-05-11 현대자동차주식회사 파워모듈
US9870985B1 (en) * 2016-07-11 2018-01-16 Amkor Technology, Inc. Semiconductor package with clip alignment notch
JP6892796B2 (ja) * 2017-07-07 2021-06-23 新光電気工業株式会社 電子部品装置及びその製造方法
DE102019103281B4 (de) * 2019-02-11 2023-03-16 Infineon Technologies Ag Verfahren zum bilden eines die-gehäuses
CN111725173A (zh) * 2020-06-05 2020-09-29 杰群电子科技（东莞）有限公司 一种堆叠封装结构及堆叠封装结构的制造方法
DE112021005639T5 (de) * 2020-12-23 2023-08-03 Rohm Co., Ltd. Verfahren zur herstellung eines halbleiterbauteils und halbleiterbauteils
CN219123228U (zh) * 2023-01-06 2023-06-02 上海凯虹科技电子有限公司 引线框架及封装结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101326636A (zh) * 2005-12-09 2008-12-17 飞兆半导体公司 用于组装顶部与底部暴露的封装半导体的装置和方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11177007A (ja) * 1997-12-15 1999-07-02 Hitachi Ltd トランジスタパッケージ
JP4450800B2 (ja) * 1999-02-17 2010-04-14 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3314768B2 (ja) * 1999-10-26 2002-08-12 サンケン電気株式会社 半導体装置及びその製造方法
US6734536B2 (en) 2001-01-12 2004-05-11 Rohm Co., Ltd. Surface-mounting semiconductor device and method of making the same
JP2002222890A (ja) * 2001-01-25 2002-08-09 Rohm Co Ltd 半導体装置およびその製造方法
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US7132734B2 (en) * 2003-01-06 2006-11-07 Micron Technology, Inc. Microelectronic component assemblies and microelectronic component lead frame structures
JP4294405B2 (ja) * 2003-07-31 2009-07-15 株式会社ルネサステクノロジ 半導体装置
US7238551B2 (en) * 2004-11-23 2007-07-03 Siliconix Incorporated Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys
US7394150B2 (en) * 2004-11-23 2008-07-01 Siliconix Incorporated Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys
US20060108635A1 (en) 2004-11-23 2006-05-25 Alpha Omega Semiconductor Limited Trenched MOSFETS with part of the device formed on a (110) crystal plane
JP4575955B2 (ja) * 2004-11-23 2010-11-04 シリコニックス インコーポレーテッド 半導体パッケージ及びその製造方法
US7394151B2 (en) * 2005-02-15 2008-07-01 Alpha & Omega Semiconductor Limited Semiconductor package with plated connection
US20070132073A1 (en) * 2005-12-09 2007-06-14 Tiong Toong T Device and method for assembling a top and bottom exposed packaged semiconductor
US7271470B1 (en) * 2006-05-31 2007-09-18 Infineon Technologies Ag Electronic component having at least two semiconductor power devices
US20080036078A1 (en) 2006-08-14 2008-02-14 Ciclon Semiconductor Device Corp. Wirebond-less semiconductor package
JP4365856B2 (ja) * 2006-12-21 2009-11-18 株式会社オティックス カムシャフトの支持構造及び支持部材
US8035221B2 (en) * 2007-11-08 2011-10-11 Intersil Americas, Inc. Clip mount for integrated circuit leadframes

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101326636A (zh) * 2005-12-09 2008-12-17 飞兆半导体公司 用于组装顶部与底部暴露的封装半导体的装置和方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12142548B2 (en) * 2021-12-30 2024-11-12 Alpha And Omega Semiconductor International Lp Semiconductor package having mold locking feature

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