CN102683221A - 半导体装置及其组装方法 - Google Patents

半导体装置及其组装方法 Download PDF

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Publication number
CN102683221A
CN102683221A CN2011100638447A CN201110063844A CN102683221A CN 102683221 A CN102683221 A CN 102683221A CN 2011100638447 A CN2011100638447 A CN 2011100638447A CN 201110063844 A CN201110063844 A CN 201110063844A CN 102683221 A CN102683221 A CN 102683221A
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China
Prior art keywords
tube core
heat sink
semiconductor device
substrate
support component
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CN2011100638447A
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CN102683221B (zh
Inventor
高伟
龚志伟
叶德洪
张虎昌
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NXP USA Inc
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Freescale Semiconductor Inc
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Priority to CN201110063844.7A priority Critical patent/CN102683221B/zh
Priority to US13/398,811 priority patent/US8735223B2/en
Publication of CN102683221A publication Critical patent/CN102683221A/zh
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    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

本发明涉及半导体装置及其组装方法。一种形成半导体装置的方法，包括：将管芯固着到热沉以形成管芯和热沉组件，并然后将所述管芯和热沉组件放置在支撑元件上。一种半导体装置包括设置在支撑元件上的管芯和热沉组件。所述管芯和热沉组件在被设置在所述支撑元件上之前被预组装。

Description

半导体装置及其组装方法
技术领域
本发明涉及半导体装置及组装半导体装置的方法，并且更具体地，涉及用于改善半导体装置的热耗散的方法。 
背景技术
常规的形成用于高电流和/或高功率应用的半导体装置的技术典型地牵涉将功率管芯(power die)安装到管芯接合盘(die pad)上，该管芯接合盘作为热沉(heat sink)以改善功率管芯所产生的热量的耗散。需要相对高厚度的管芯接合盘(其典型地由金属材料形成)。 
当前存在两种主要的实现该厚度增加的热沉的技术，使用厚度增加的引线框架或使用双规(dual-gauge)引线框架。实现任何一个技术都使引线框架比被认为是必要的还显著地昂贵，从而使得封装处理的总体成本不希望地高。增加的厚度还在引线框架设计和制造中以及对于封装布局引入了其自身的限制。例如，引线节距(pitch)与引线框架厚度有关，要求特定的蚀刻或冲压纵横比。 
使用双规引线框架要求引线框架具有两个或更多个厚度不同的部分。某些技术要求两个引线框架部分彼此附接，其中具有较高厚度的部分作为热沉。这是相对复杂的布置，要求相对复杂的制造工艺，还导致较高成本并呈现某些设计限制。 
对于半导体产品(诸如，PQFN(功率扁平四方无引线)产品，附接半导体装置中的管芯所需的步骤必须在带载(taping)引线框架前完成，以便避免在后续的工艺步骤(诸如固化和/或回流工艺)中带的损伤。带载附接有管芯的引线框架可能导致操纵困难。例如，在管芯设置在引线框架上的情况下，必须保护管芯在引线框架带载工艺期间不受损伤或刮擦。此外，可能不能在带载机中设计并使用通用的工 具/夹具，因为每一个工艺将可能要求引线框架上的不同的布局。这意味着较高的工具加工成本以及在产品改变时增加的工具加工转换难度。另外，具有管芯的引线框架的条带翘曲大于没有管芯的引线框架，因此，导致带载机中引线框架堵塞的事件的可能性较高。 
因此，开发一种或更多种降低引线框架成本(尤其是在高功率应用中)以及消除前述操纵问题和设计限制的新的制造技术将是有利的。另外，如果这些一种或更多种新的制造技术能够允许更大的混合和匹配来自通常被认为对于半导体封装是不兼容的或者至少是难以集成的技术的部件的灵活性，这将是有利的。此外，如果这些一种或更多种新的制造技术对于热量耗散维持或者改善当前可获得的性能，这将是有利的。 
附图说明
通过示例的方式示出本发明，并且本发明不受附图的限制，在附图中，相同的附图标记表示类似的元件。图中的元件出于简化和清楚的目的而是出，并且并不必然按比例绘制。 
图1A是示出了根据本发明实施例的管芯和热沉组件的形成的放大视图； 
图1B是示出了根据本发明实施例的具有图1A的管芯和热沉组件的半导体装置的形成的放大视图； 
图1C是示出了模制包封工艺步骤之后的具有接合线的完整的图1B的半导体装置的放大视图； 
图2A是示出了根据本发明实施例的管芯和热沉组件的形成的放大视图； 
图2B是示出了根据图2A的实施例的图2A的具有管芯和热沉组件的半导体装置的形成的放大视图； 
图2C是示出了模制包封工艺步骤之后的具有接合线的完整的图2B的半导体装置的放大视图； 
图3是示出了根据本发明另外实施例的半导体装置的放大视图； 
图4A是示出了根据本发明另一实施例的半导体装置的放大视图； 
图4B是示出了根据本发明又一实施例的半导体装置的放大视图； 
图5A是示出了用于MAP BGA/LGA半导体封装中的热量耗散的第一常规布置的放大视图； 
图5B是示出了用于MAP BGA/LGA半导体封装中的热量耗散的第二常规布置的放大视图； 
图6是示出了利用用于改善热量耗散的制造工艺形成的半导体装置的放大视图； 
图7A-7N和7P是示出了用于制造图6的半导体装置的工艺的一系列的视图； 
图8是示出了使用图7A-图7P的制造工艺的原理形成的半导体装置的放大视图； 
图9是示出了使用图7A-图7P的制造工艺的原理形成的半导体装置的放大视图； 
图10是示出了使用图7A-图7P的制造工艺的原理形成的半导体装置的放大视图； 
图11是示出了使用图7A-图7P的制造工艺的原理形成的半导体装置的放大视图；以及 
图12是示出了使用图7A-图7P的制造工艺的原理形成的半导体装置的放大视图。 
具体实施方式
在一个实施例中，本发明提供了一种形成半导体装置的方法，该方法包括：将管芯固着到热沉以形成管芯和热沉组件；以及将所述管芯和热沉组件设置在所述半导体装置的支撑元件上。 
在另一实施例中，本发明提供了一种形成半导体装置的方法，该方法包括：将管芯接合盘固着到管芯接合盘以形成管芯和管芯接合盘 组件；以及将所述管芯和管芯接合盘组件设置在所述半导体装置的支撑元件上。 
在又一实施例中，本发明提供了一种半导体装置，其包括：设置在所述半导体装置的支撑元件上的管芯和热沉组件，所述管芯和热沉在被设置在所述支撑元件上之前已经被预组装。 
与常规技术相比，本发明实施例的实现方式可以提供显著的技术优点。例如，管芯和热沉组件在被设置在半导体装置的支撑元件上之前的预组装使装置组装工艺流水线化，降低了操纵问题方面的难度。例如，对于管芯和热沉组件仅必须执行一次到支撑元件上的放置操作，而不是必须执行两次(或更多次)放置操作，对于所述热沉和所述管芯中的每一个进行一次或更多次。这在实现捡取和放置技术时尤其有利。 
另外，如下面将进一步详细讨论的，半导体装置的基底部件的成本，不管是引线框架或基板，都可以通过降低其厚度而显著降低。热量耗散所需的厚度可以以另外的方式利用厚度大于基底部件厚度的热沉来提供，而没有由于具有厚度增加的基底部件或者双规基底部件(诸如，双规引线框架)而伴生的另外的费用和设计限制。 
另外，到热沉/管芯接合盘的管芯附接可以不用引线框架形式实现。在常规的半导体封装工艺中，管芯通常附接在引线框架或基板上。在本发明的实施例中，能够在封装之前将管芯附接在单个管芯接合盘/热沉上以形成管芯和管芯接合盘/热沉组件。这允许在要求较厚管芯接合盘和/或热沉的封装工艺中增加的灵活性和更大的简化。例如，热沉材料可以不同于基底部件的材料，具有用于实现较好产品性能的较佳热学特性。另外，热沉厚度和形状不再受基础部件制造技术的限制。使用预组装的管芯和管芯接合盘或热沉组件的另一优点是允许使用具有改善的热学特性的高温管芯附接材料，例如，焊料或高温固化环氧树脂。就此而言，在与其它管芯附接材料相比，如此使用焊料提供了改善的热耗散时，管芯和管芯接合盘或热沉组件的预组装可能是特别有利的。 
另外，本发明消除了带载安装有装置的引线框架的上面所述的操纵问题。 
如所述的，本发明具有跨多种半导体封装技术的宽泛的应用。例如，本发明具有在BGA/LGA制造技术(诸如，MAP BGA/LGA技术)中的应用。另外，本发明具有在制造、实现如QFN、PQFN、QFP、SOIC等技术的引线框架中的应用。 
另外，由于所涉及的工艺步骤与许多标准工艺(诸如，QFN/PQFN)是一致的或者至少非常类似的，因此本发明的实施例可以使用标准的或半标准的半导体制造加工手段来实现。另外，管芯接合盘载体(其作为用于放置单独的管芯接合盘的载体)可以类似于标准的倒装芯片工艺中的基板载体。其它的技术也可以使用管芯接合盘/热沉组件，例如，以允许在利用单颗化(singulation)工具分离之前将多个管芯附接到大的金属件。另外，可以使用普通的管芯接合工具和/或捡取和放置工具来放置所述管芯和热沉组件。对于某些制造商另外的益处是：提供预组装了管芯的或者没有预组装管芯的热沉完全是在许多引线框架供应商的制造能力范围内，从而由低成本冲压技术的实现方式提供了潜在的成本节约。当在如BGA背景中实现本发明时也可以实现类似的益处。 
还公开了一种组装半导体装置的方法，所述方法包括：提供基底部件(诸如，基板或引线框架)，其具有从其穿过的开口；将带固着到所述基底部件的下侧，所述带覆盖穿过所述基底部件的所述开口；将热沉设置或放置在所述带上，所述热沉的第一主表面与所述带接触，所述热沉安置在所述开口中；以及将管芯固着到所述热沉的第二主表面。另外，还可以将其他的元件放置到所述带上以扩展所述半导体装置的功能性，例如，另外的金属引线、SMD(表面安装装置)等。 
在该方法的一个实现方式中，所述热沉的所述第一主表面与所述基底部件(诸如，基板)的所述下侧共面。 
因为实现本发明的装置就其最主要部分而言是由本领域技术人员所知的装置部件构成的，因此为了不使本发明的教导模糊或混乱， 将不在比被认为对于理解和领会本发明的重要概念所必须的程度更大的程度上解释完全的细节。 
某些实施例可以使用各种不同基底部件实现。例如，尽管图1及其讨论描述了使用引线框架作为半导体装置中的基底部件，但是该示例性的半导体装置仅是被呈现来在讨论本发明的各方面时提供有用的参考。如将说明的，在本发明的实施例中可以使用替代的基底部件，诸如，如图2中示出的基板，或其它合适的基底部件。当然，出于讨论的目的，已经简化了对本发明实施例的说明，并且其不过是可以根据本发明使用的许多不同类型的适当的实施例之一。本领域技术人员将认识到，这些实施例仅仅是说明性的，并且替代的实施例可以采用不同的基底部件或使用替代的热沉部件。 
现在参考图1，其示出了在PQFN背景下的本发明的实施例。图1A中首先示出了独立式热沉100，利用例如焊料或者导热环氧树脂或膜104将热沉102固着于其上。在这样做时，形成管芯和热沉组件，即，预组装的管芯和热沉(通常以105表示)。 
图1B示出了利用管芯和热沉组件105形成半导体装置的方法。所述半导体装置还包括支撑元件106和基底部件108。因此，实际上，图1B示出了利用如下的方法形成的半导体封装件，所述方法包括：将管芯102固着到热沉100以形成管芯和热沉组件105；以及将所述管芯和热沉组件105设置在所述半导体装置的支撑元件106上。 
在图1B的实施例中，基底部件108包括引线框架，和/或支撑元件106包括其上设置引线框架108的带。 
所示出方法是特别有利的形成半导体装置的方法，由于其仅必须执行一个将预组装的管芯和热沉组件105放置在支撑元件106上的放置操作，而不是如上所述的必须将热沉100放置在支撑元件上并且之后利用材料104将管芯102固着到热沉100。此外，如上面所述的，常规的技术会导致与操纵有关的显著的困难。例如，在其中热沉放置在固着到引线框架下侧的带上然后固定所述管芯的常规技术中，可能发生对带和/或引线框架的损伤。利用图1的方法，可能应用高温管芯 附接材料，诸如焊料，而不导致对支撑元件106的损伤，例如，回流炉(reflow oven)内的焊料附接。 
在图1B的示例中还示出了可选的第二或另外的组件110以及关联的引线框架部件。 
在图1A中，热沉100具有第一厚度112，而在图1B中，基底部件108具有第二厚度114，并且所述第一厚度114小于所述第二厚度112。利用这样的布置，另外的厚度用于耗散来自管芯102(诸如，功率管芯)的热量，可以通过厚度增加了的热沉100来有效地耗散，而不必增加基底部件108(例如，引线框架)的厚度，从而导致在减少用于引线框架108的厚度的材料和/或提供更复杂的引线框架(诸如双规引线框架)方面的实质性的成本节约。 
在图1的实施例中，管芯和热沉组件105通过基底部件108的开口116设置在支撑元件106上。如本领域技术人员将理解的，引线框架典型地包括具有一个或更多个从其穿过的开口(诸如，开口116)的外框架。在图1的实施例中，将管芯和热沉组件105设置在带106上为管芯和热沉组件105提供了支撑物，例如，将其保持在期望的位置，以用于后续的制造操作，这将参考图1C简短地讨论。 
在图1的实施例中，所述方法可以包括利用捡取和放置装置(图1B中示出了其一个部件118)将管芯和热沉组件105设置在支撑元件(带)106上。因此，该方法有助于与标准的半导体制造工具(诸如，捡取和放置装置)一起使用。 
在一个或更多个实施例中，热沉100是管芯接合盘。在这样的实施例中，图1因此示出了一种利用如下方法形成的半导体装置，所述方法包括：将管芯102固着到管芯接合盘100以形成管芯和管芯接合盘组件105；以及将该管芯和管芯接合盘组件105设置在半导体装置的支撑元件106上。图1B示出了一种半导体装置，其包括设置在该半导体装置的支撑元件106上的管芯和管芯接合盘组件105，其中管芯102和管芯接合盘100在被设置在该支撑元件106上之前已经被预组装。另外，在这样的实施例中，图1B示出了如下的半导体装置， 其中基底部件108具有第一厚度114而管芯接合盘100具有第二厚度112，所述第一厚度114小于所述第二厚度112。在这样的实施例中，形成半导体装置的方法包括：通过基底部件108的开口116将管芯和管芯接合盘组件105设置在支撑元件106上。 
如上所述，利用带作为支撑元件106的一个特别的益处是，在半导体装置的形成过程中的后续步骤期间带可以将管芯和热沉组件105保持在适当的位置。如图1C中示出的，在通过引线框架108的开口116将管芯和热沉组件105设置在带106上之后，可以在管芯102和引线框架108之间形成接合线120。随后，使用模制包封材料122来包封已经导线接合到引线框架108的管芯和热沉组件105，以形成包封的半导体装置124。随后，可以去除带106，并通过固化的模制包封材料将管芯和热沉组件105保持在适当的位置。 
参考图2，示出了本发明的在BGA封装背景下的实施例。图2A示出了独立式热沉200，利用例如焊料或者导热环氧树脂或膜204将管芯202固着于其上。如此形成了管芯和热沉组件(通常由205表示)。 
图2B示出了利用管芯和热沉组件205组装半导体装置的方法。所述半导体装置还包括支撑元件206和基底部件208。在该实施例中，支撑元件206是带，而基底部件208是基板，诸如可以典型地在BGA半导体封装中找到的那些。示例性的合适的基板包括塑料封装基板。因此，实质上，图2B还示出了一种利用如下方法组装的半导体封装件，所述方法包括：将管芯202固着到热沉200，以形成管芯和热沉组件205；以及将管芯和热沉组件205设置在半导体装置的支撑元件206上。利用该方法，可以应用高温管芯附接材料，诸如焊料，而不导致对支撑元件206的损伤，例如，回流炉内的焊料管芯附接。 
另外，图2B示出了一种半导体装置，其包括设置在该半导体装置的支撑元件206上的管芯和热沉组件205，管芯202和热沉200在被设置在该支撑元件上之前已经被预组装。图2B中还示出了可选的第二或另外的组件210以及关联的基板部件。 
在所示出的实施例中，并且再次参考图2A，将看到热沉200具 有第一厚度212，而基底部件208具有第二厚度214。更特别地，基底部件208具有第一厚度214而热沉200具有第二厚度212，其中第一厚度214小于第二厚度212。再次地，利用这样的布置，另外的厚度用于来自管芯202(诸如，功率管芯)的热量的耗散，通过厚度增加的热沉200可以有效地进行耗散而不必增加基底部件208(例如，封装基板)的厚度，从而导致在减少用于基板206的厚度的材料方面的实质性的成本节约。在一种替代布置(未示出)中，第一厚度214可以相等或大于第二厚度212。在此之外，或者作为另外的替代，热沉200可以包括与基底部件208(其可以是有机基板)的材料不同的材料。例如，可以使用铜合金材料作为热沉，对于热量传输，该材料比基板材料更有效。 
在图2的实施例中，管芯和热沉组件205通过基底部件208的开口216设置在支撑元件206上。如本领域技术人员将理解的，封装基板206可以设置有从其穿过的开口(诸如，开口216)，或者其中设置有空腔。在图2的实施例中，管芯和热沉组件205设置在带206上为管芯和热沉组件205提供了支撑物以用于后续的操作，这将参考图2C简短地讨论。 
在图2的实施例中，所述方法还可以包括：利用捡取和放置装置(图2B中示出了其一个部件218)将管芯和热沉组件205设置在支撑元件(带)206上。因此，图2的方法有助于与标准的半导体制造工具(诸如，捡取和放置装置)一起使用。 
在一个或更多个实施例中，热沉200是管芯接合盘。在这样的环境下，图2因此示出了一种通过如下组装的半导体装置：将管芯202固着到管芯接合盘200以形成管芯和管芯接合盘组件205；以及将管芯和管芯接合盘组件205设置在该半导体装置的支撑元件206上。此外，图2B示出了一种半导体装置，其包括设置在该半导体装置的支撑元件206上的管芯和管芯接合盘组件205，其中管芯202和管芯接合盘200在被设置在该支撑元件206上之前已经被预组装。 
如上所述的，利用带作为支撑元件206的一个特别的益处是，在 半导体装置的形成过程中的后续步骤期间带可以将管芯和热沉组件205保持在适当的位置。如图2C中所示的，在管芯和热沉组件205通过基板208的开口216设置在带206上之后，可以在管芯202以及基板208之间连接接合线220。随后，使用模制包封材料222来封装已经导线接合到引线框架208的管芯和热沉组件205，来形成包封的半导体装置224。之后可以去除带，并通过固化的模制包封材料将管芯和热沉组件保持在适当的位置。 
本发明具有比图1和图2的实施例更宽泛的应用。例如，本发明还可以用于需要热沉的其它类型的封装。图3中示出了本发明的另一实施例。热沉300具有诸如通过焊料或者如利用导热环氧树脂或膜304等固着于其的管芯302。在该实施例中，预组装的管芯302和热沉300设置在作为支撑元件306的第二管芯接合盘上，还利用焊料305等将热沉300固着到管芯接合盘306。因此，图3还示出了一种半导体装置，其包括设置在该半导体装置的支撑元件306上的管芯和热沉组件302、300，管芯302和热沉300在被设置在支撑元件306上之前已经被预组装，从而形成半导体装置310。在一个或更多个实施例中，热沉300包括第一管芯接合盘，这意思是说支撑元件306是第二管芯接合盘。 
尽管图3的实施例示出了热沉300和支撑元件306尺寸可比，然而，这不应被认为是限制性的，并且当然支撑元件306(如上面所述的，其可以包括管芯接合盘)可以对于所述(第一)管芯接合盘/热沉300具有不同的尺度。因此，该方法特别有利之处在于：其在制造中对于接合盘材料、尺寸、厚度、形状等的混合提供了灵活性。 
现在转到图4，示出了设置在引线框架上的预组装的管芯和热沉组件。 
首先看图4A，热沉400具有利用焊料404等(诸如，导热环氧树脂或膜)固着于其的管芯402。热沉400反过来又设置在作为支撑元件的引线框架406上。热沉400利用焊料408或类似物(诸如，导热环氧树脂或膜)固着到引线框架406。接合线410用于管芯402和 引线框架406之间的电连接。使用一个或更多个下(down)接合线412来将管芯402接合到热沉400。包封材料414包封管芯402和热沉400组件来形成半导体装置416。在图4A的实施例中，在半导体装置416的下侧上，引线框架406的下侧418暴露，这可以改善半导体装置416的热耗散性能。 
图4B示出了类似的布置。再次地，热沉400具有利用焊料404等固着于其的管芯402。热沉400反过来又设置在作为支撑元件的引线框架406上。热沉400利用焊料408等固着到引线框架406。使用接合线410来形成管芯402和引线框架406之间的电连接。使用一个或更多个下(down)接合线412来将管芯402接合到热沉400。包封材料414包封管芯402和热沉400组件来形成半导体装置416。在图4B的实施例中，在半导体装置416的下侧上，引线框架406的下侧418不露出，利用包封材料414包封引线框架406的整个部分420。 
与常规技术相比，本发明的实施例为半导体装置的提供了改善的热耗散性能。这在管芯102、202、302、402是功率或高电流管芯的实施例中是特别有利的。利用焊接或其它方法将管芯附接/固着于其上的独立式热沉的使用提供了如上面所概述的多种技术优点。 
因此，提供了用于形成高热应用中的半导体装置的成本降低的解决方案。例如，其上预附接了管芯的独立式热沉的提供消除了对将热沉构建到引线框架或封装基板中的要求。这导致封装设计和工艺改善的灵活性，例如对于高温应用。 
本发明的实施例还允许半导体制造工艺以降低的成本和良好的可制造性来满足高温应用中的必须的性能。 
已经实现了尝试实现有效地从如MAP BGA/LGA半导体封装耗散热量的其它技术。这种类型的常规的封装典型地基于塑料封装基板。热耗散主要通过从集成电路管芯通过基板和焊料球传导到印刷电路板(PCB)而发生。塑料封装基板典型地具有非常低的热导率，在0.2瓦每米每摄氏度(W/m/℃)的范围中，并因此通常在热传导和热扩散方面通常较差。为了改善热学性能，这些常规技术在半导体封装内放 置热扩散器(heat spreader)。 
现在参考图5A，示出了用于MAP BGA/LGA半导体封装中的热耗散的第一常规技术。如此，在图5A中，半导体封装件500包括基板502，通过如焊料506将管芯504固着于其上。又利用例如导热环氧树脂或膜510或类似物(诸如焊料)将热扩散器508固着到管芯504的表面。焊料球510固着到基板502的下侧。接合线512形成管芯504和基板502之间的电连接，并且该组件被用包封材料514包封。箭头516示出了通过从管芯504通过热扩散器508的传导的热耗散。 
图5B中示出了第二常规技术，其是与图5A的有点类似的技术。半导体封装件550包括基板552，用导热环氧树脂或膜554将热扩散器553固着于其上。管芯556利用焊料558固着到热扩散器553。焊料球560固着到基板552的下侧。接合线562形成管芯556和基板552之间的电连接，并且该组件被利用包封材料564包封。箭头566示出了通过从管芯556通过热扩散器553、基板552和焊料球560的传导的热耗散。 
图5A的方法受模制化合物材料514的低的热导率(大约0.2～0.3W/m/℃)的限制，而图5B的方法受BT或FR4基板的低的热导率(大约0.2～0.9W/m/℃)的限制。因此，对于MAP BGA封装等，具有改善的热容量是期望的。另外，期望开发出高度可靠的但是复杂度降低了的用于MAP BGA封装等的制造技术。 
图6中示出了一种解决方案，图6示出了具有基板602的半导体装置600，该基板602具有固着到基板602的下侧603的带(未示出)。基板602具有从其穿过的孔604。利用例如导热环氧树脂或膜610，或者焊料，将管芯606固着到热扩散器608。接合线612形成管芯606和基板602上的镀的迹线之间的电连接。包封材料614包封管芯和热扩散器组件，在此之后，可以将带去除。焊料球616形成在基板602的下侧603上，并被通过基板602中的通路(via)(未示出)电连接到该基板的上表面上的镀的迹线。露出的热扩散器表面限定在611处的第一主表面，其是可焊接的并且可以利用焊料620直接焊接到PCB 618。箭头622示出了通过从管芯606经焊料610到热扩散器608并且经焊料620到PCB 618的热传导。箭头624表示通过经包封材料614的传导的热耗散。另外，箭头626示出了通过经焊料球616到PCB 618的传导的热耗散。 
因此，图6示出了一种已经以如下的方法形成的半导体装置，所述方法包括：提供基底部件602，所述基底部件602具有从其穿过的开口604；将带(未示出)固着到基底部件602的下侧603，所述带覆盖穿过基底部件602的开口604；将热沉608放置到所述带上，所述热沉608的第一主表面611与所述带接触，热沉608安置在所述开口604中；以及将管芯606固着到所述热沉608的第二主表面。可以在所述焊料球的附接以及单颗化之前去除所述带。 
在图6的示例中，基底部件602是封装基板，但是该技术具有宽泛的应用，例如应用到其中基底部件602是引线框架的QFN工艺。 
在图6的示例性的方法中，热沉608的第一主表面611与基底部件602的下侧603共面。 
参考图7，并在BGA背景下，逐步骤地说明图6的形成半导体装置的方法。首先参考图7A，提供具有通窗(through window)604的基板602。图7B中示出了基板602的更小比例的平面图，示出了该基板具有多个通窗604。 
在图7C中，将带700施加到基板602的下侧603。如图7D的更小比例的平面图中所示的，带700覆盖基板602的窗604。 
接着，如图7E中所示，通过基板602的窗604将热扩散器608设置或放置到带700上。图7F以部分平面图对此进行了示出。 
现在转到图7G，管芯606被示出为利用例如环氧树脂膜610附接到热扩散器608。图7H以部分平面图对此进行了示出。 
利用接合线612，在管芯606和基板602上的镀的迹线之间形成电连接，如图7I和7J中所示。 
然后执行模制工艺以利用包封材料614将管芯和热沉组件包封在基板602上，如图7K中所示，并将包封材料固化。 
如图7L中所示，去除带700，从而露出现在被利用固化的包封材料614保持在适当的位置的基板602的下侧603和热沉608。图7M示出了具有露出的热沉608的基板的下侧视图603。 
图7N示出了在已经将焊料球616附接到基板602的下侧603之后的半导体封装件。在图7P中以透视图示出了单颗化之后完成的封装件的下侧，其中在下侧603上可以看到露出的热沉608以及焊料球616。 
因此，所示出的技术提供了在基板中心处的通窗。在基板的BGA侧的中心处的露出的热扩散器可以通过例如焊接固着到PCB。如所示的，在该工艺期间在包封之前使用粘合剂来将热沉维持在适当的位置。 
除了提供了热耗散方面的改进和改善的可制造性，所示的技术还在以下方面提供了另外的显著的益处：该工艺的许多步骤是与常规的MAP BGA工艺中使用的制造工艺相同或至少类似。另外，用于带载工艺的工具类似于QFN带载工艺工具。此外，可以使用普通的管芯接合工具或捡取及放置工具以用于热沉和/或管芯的附接。此外，预期许多基板制造商将能够提供所需的具有通窗的基板。 
可以通过具有带的晶片环或窝伏尔组件(waffle pack)来应用热扩散器/热沉。 
图6中所示的形成半导体装置的方法可以改善BGA/LGA封装件的性能，使它们与EPAD引线封装件(诸如，EPAD QFP)相比具有等同的热学性能，以及具有改善的可制造性和可靠性。另外，根据图6和图7中所示的技术形成的封装件可以具有大约400W/m/℃的增加的热导率，特别是在利用热扩散器和焊料时。 
图6中所示的技术和上面讨论的常规技术之间的一显著的不同是：图6的技术不需要基板602和热扩散器608之间的连接或界面。已经发现常规技术中的在基板和热沉在之间连接在可靠性测试期间是脆弱点，这是利用图6的其中热沉定位在穿过基板的孔或窗中的技术所消除的一个问题。 
图6的通窗基板和带载工艺使露出的热扩散器BGA/LGA封装更 加可靠，并具有增加的制造灵活性。图6的半导体装置满足高温应用中的性能要求，同时提供了简化的工艺和改善的可制造性。 
所示的技术还具有在如QFN/PQFN背景下的应用，并允许利用BGA/LGA/QFN或其它技术形成的半导体封装件以增加的灵活性设计具有多个热扩散器、功率引线、无源装置和管芯。尤其是，该技术可以在其中通过包封材料和/或基板/引线框架材料形成平的表面的QFN/PQFN背景下实现。 
图8到图11示出了图6和图7的技术的变体。 
参考图8，半导体装置800包括第一和第二管芯802、804，所述第一和第二管芯802、804利用管芯附接材料(诸如，焊料或环氧树脂)805固着到热沉/管芯接合盘806。接合线808形成在第一和第二管芯802、804与基板809之间。随后，使用模制包封材料810来包封装置800的部件，并且在固化之后，包封材料810凝固化以将这些部件保持在适当的位置。示出了固化的包封材料810的下侧812。随后，焊料球814附接到装置800.的下侧。尽管图8中未示出，但是在包封材料的固化之前使用带将管芯和热沉保持在适当的位置。在将焊料球814附接到基板809之前将带去除。 
如图9中所示，半导体装置900包括第一和第二管芯902、904，所述第一和第二管芯902、904利用管芯附接材料905固着到相应的第一和第二热沉/管芯接合盘906、908。在第一和第二管芯902、904与基板912之间形成接合线910。在图9的半导体装置900中，基板912还具有设置在第一管芯906和第二管芯908之间的“内”部分912A。当然部分912A可以是与基板部分912完全分离的。随后，使用模制包封材料914来包封该装置的部件，并且在固化之后，包封材料914凝固化以将部件保持在适当的位置。示出了固化的包封材料914的下侧916。随后，将焊料球918附接到装置900的下侧。尽管在图9中未示出，但是在包封材料的固化之前，使用带来将管芯、热沉以及基板的部分(或多个部分)保持在适当的位置。在将焊料球918附接到基板912之前将带去除。 
图10中示出了半导体装置1000。装置1000包括第一和第二管芯1002、1004，所述第一和第二管芯1002、1004利用管芯附接材料1005固着到相应的热沉/管芯接合盘1006、1008。一个或更多个元件(例如，金属引线端子)1014设置在带(未示出)上。这可以与管芯和热沉在带上的设置同时地或不同时地进行。接合线1010分别形成在该第一和第二管芯1002、1004与基板1012和元件1014之间。如前所述，采用具有下侧1018的包封材料1016来包封装置1000的部件。在组装工艺期间，使用带(如上所述未示出)来将装置1000的单独的部件保持在适当的位置。在包封材料的固化之后，将带去除，并将焊料球1020附接到基板1012的下侧。 
图11的半导体装置1100包括第一和第二管芯1102、1104，所述第一和第二管芯1102、1104利用管芯附接材料1105固着到相应的热沉/管芯接合盘1106、1108。SMD(表面安装装置)1114设置在该带(未示出)上。这可以与管芯和热沉在带上的设置同时地或不同时地进行。接合线1110形成在该第一和第二管芯1102、1104与基板1112之间。如上面所述的，半导体装置1100还包括一个或更多个SMD1114。如前所述，采用具有下侧1118的包封材料1116来包封装置1100的部件。在组装工艺期间，使用带(未示出)来将装置1100的单独的部件保持在适当的位置。在包封材料的固化之后，将带去除，并将焊料球1020附接到基板1112的下侧。 
半导体装置1200(图12)包括第一和第二管芯1202、1204，所述第一和第二管芯1202、1204利用管芯附接材料1205固着到相应的热沉/管芯接合盘1206、1208。接合线1210形成在第一和第二管芯1202、1204与放置的引线端子1212之间。包封材料1214包封装置1200的部件，并且在固化之后将所述部件保持在适当的位置。示出了包封材料1214的下侧1216。 
因此，如图10到12中所示，半导体封装元件(包括但是不限于，引线端子和表面安装装置)被放置到半导体装置的支撑元件(诸如所述组装工艺中使用的带)上，在管芯和如此放置的封装元件之间连接 有或没有连接导线。所放置的元件被与管芯一起包封。 
至此应当理解，已经提供了一种新颖的形成其中设置有预组装的管芯和热沉组件的半导体装置的方法。如上面所述的，这提供了显著的技术优点。还公开了一种新颖的通过如下形成半导体装置的方法：通过半导体装置的基底部件(诸如，基板或引线框架)的通孔将热沉放置到带上；以及将管芯固着到热沉。再次地，还是如上面所述的，这提供了显著的技术优点。 
尽管此处参考特定实施例描述了本发明，但是也可以进行多种修改和改变而不偏离如下面的权利要求所提出的本发明的范围。例如，可以使用一个以上的管芯和热沉组件。基底部件可以是基板或引线框架，或者其它合适的基底部件。因此，本申请文件和附图应被认为是说明性的而不是限制性的意思，并且意图将所有这样的修改包括在本发明的范围内。此处就特定实施例描述的任何益处、优点、或对问题的解决方案意图不应被认为是任何或全部权利要求的关键的、需要的、或实质性的特征或要素。 

Claims (9)

1.一种组装半导体装置的方法，所述方法包括：
将管芯固着到热沉以形成管芯和热沉组件；以及
将所述管芯和热沉组件设置在所述半导体装置的支撑元件上。
2.如权利要求1所述的方法，其中所述支撑元件包括带，其上设置所述半导体装置的基底部件。
3.如权利要求2所述的方法，其中所述基底部件是引线框架。
4.如权利要求2所述的方法，其中所述基底部件是基板。
5.如权利要求2所述的方法，其中所述基底部件具有第一厚度，而所述热沉具有第二厚度，所述第一厚度小于所述第二厚度。
6.如权利要求2所述的方法，还包括：通过所述基底部件的开口将所述管芯和热沉组件设置在所述支撑元件上。
7.如权利要求1所述的方法，还包括：利用捡取和放置装置将所述管芯和热沉组件设置在所述支撑元件上。
8.如权利要求1所述的方法，其中所述支撑元件是引线框架。
9.一种半导体装置，包括：
支撑元件；
管芯和热沉组件，其设置在所述支撑元件上，其中所述管芯和热沉在被设置在所述支撑元件上之前被预组装。
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