CN102610580A - 用于fcbga的非金属加强圈 - Google Patents

用于fcbga的非金属加强圈 Download PDF

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CN102610580A
CN102610580A CN2012100164680A CN201210016468A CN102610580A CN 102610580 A CN102610580 A CN 102610580A CN 2012100164680 A CN2012100164680 A CN 2012100164680A CN 201210016468 A CN201210016468 A CN 201210016468A CN 102610580 A CN102610580 A CN 102610580A
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loop configuration
substrate
thickness
assembly according
stiffening ring
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何中雄
黄文鸿
潘保同
张静慧
陈怡斌
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Koninklijke Philips NV
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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Abstract

PCB或类似材料用于在倒装芯片球栅阵列(FCBGA)封装中支撑热沉的加强圈。封装的衬底材料和加强圈共用相同或相似的热膨胀系数。可以采用刳刨工具由PCB或类似材料制造加强圈。

Description

用于FCBGA的非金属加强圈
背景技术
球栅阵列(BGA)是一种集成电路封装技术，其特征在于使用衬底，该衬底的上表面安装有半导体芯片，且该衬底的下表面安装有焊球的栅格阵列。在表面安装技术工艺期间，例如，BGA封装可以通过焊球的栅格阵列机械地焊接结合并电连接至印刷电路板(PCB)。
倒装芯片球栅阵列(FCBGA)是一种BGA技术，其采用倒装芯片技术，以倒置方式将芯片管芯的有源侧安装在衬底上，并通过使用附着至管芯输入/输出焊盘的焊料凸块结合至衬底。由于管芯和FCBGA封装部件(例如，衬底和底层填料(在芯片和衬底之间流动的粘合剂))之间的热膨胀系数失配，在FCBGA封装中经常产生热应力。对于管芯的热问题可以通过将热沉附着至管芯来减小，其中热沉在管芯处由加强圈机械地支撑。
附图说明
图1a以侧视图示出了具有热沉的现有技术FCBGA封装。
图1b以顶视图示出了现有技术FCBGA封装。
图1c以侧视图示出了具有热沉的现有技术FCBGA封装。
图1d以侧视图示出了具有热沉的现有技术FCBGA封装。
图2以侧视图示出了根据本发明实施例的具有热沉的FCBGA封装。
图3以顶视图示出了根据本发明实施例的FCBGA封装。
图4a示出了用于根据本发明实施例的“O”形加强圈的PCB布局。
图4b示出了用于根据本发明实施例的“C”形加强圈的PCB布局。
图5示出了用于根据本发明实施例的“C”形加强圈的PCB布局的多层堆叠。
具体实施方式
图1a示出了典型的现有技术倒装芯片球栅阵列封装(FCBGA)100的剖视图。FCBGA封装100包括管芯140，其采用焊料凸块145附着至下层衬底150上的接触焊盘(未示出)。底层填料135通常用在管芯140和衬底150之间，以提供粘附力，帮助避免管芯140从FCBGA封装100的衬底150上分离。焊球155通常附着至衬底150底部上的接触焊盘(未示出)，以通常提供FCBGA封装100至印刷电路板(PCB)160或诸如陶瓷型材料之类的其它衬底的电接触和连接。铝或其它典型的金属“O”型加强圈120采用粘合剂125安装在衬底150上，热沉170安装在FCBGA封装100的管芯140的顶部上。图1b示出了具有热沉170的现有技术FCBGA封装100的顶视图，其中去除了热沉170以示出典型的金属“O”型加强圈120。热沉170用来散发由管芯140产生的热量，加强圈120用来支撑由管芯140和焊料凸块145产生的间隙138，使得可以维持管芯140和热沉170之间良好的接触。典型的现有技术FCBGA封装100可以具有热界面材料(未示出)，热界面材料插入管芯140和热沉170之间，以帮助将热量从管芯140传递至热沉170。金属加强圈120通常仅在具有特定厚度时是可用的，因此间隙138的尺寸可能不能与金属加强圈120的厚度密切地配合。如果金属加强圈120的厚度如图1c以横截面示出的那样太厚，通过产生间隙101，可能会导致管芯140和热沉170之间不能形成最佳的热接触。如果金属加强圈120的厚度如图1d以横截面示出的那样太薄，通过引起热沉170倾斜由此产生间隙102，这可能会导致管芯140和热沉170之间不能形成最佳的热接触。两种间隙101和间隙102都不利地影响热沉170对来自管芯140的热量进行散热的能力。
图2示出了根据本发明实施例的剖视图。FCBGA封装200包括管芯240，其采用焊料凸块245附着至下层衬底250上的接触焊盘(未示出)。底层填料235通常用在管芯240和衬底250之间，以提供粘附力，帮助避免管芯240从FCBGA封装200的衬底250上分离。焊球255通常附着至衬底150底部上的接触焊盘(未示出)，以通常提供FCBGA封装200至印刷电路板(PCB)160或其它衬底的电接触和连接。加强圈220采用粘合剂225安装在衬底250上，热沉270安装在FCBGA封装200的管芯240的顶部上。根据本发明，加强圈220由与衬底250相同的材料(例如，PCB)制成，以针对加强圈220和衬底250二者获得相同的CTE，以减少CTE失配效应。在现有技术中，加强圈120通常由不具有与衬底250相同的CTE但可以匹配或接近热沉270的CTE的铝或其它金属制成。热沉270用来对由管芯240产生的热进行散热。加强圈220用来向热沉270提供支撑，确保热沉270与管芯240进行良好的热接触。
为加强圈220使用PCB或类似材料带来了费用节省，因为采用PCB或类似材料通常比采用诸如铝之类的金属便宜。为加强圈采用PCB或类似材料还允许由加强圈220对由焊料凸块245和管芯240的组合厚度形成的间隙238进行更好的厚度匹配。这是因为它相对容易定制PCB或类似材料的厚度。通常通过改变层叠在一起的电介质层的厚度、改变层叠在一起的电介质层的数量、改变将电介质层层叠在一起的环氧树脂半固化片(PP)层的厚度或者改变焊料掩膜厚度，可以调整PCB或类似材料的厚度。因此，存在大量的方法来调整PCB材料的厚度，从而允许精确地控制加强圈220的厚度，并避免分别如图1c和1d所示的间隙101和102的形成。
图3示出了具有热沉270的FCBGA封装200的顶视图，其中去除了热沉270以示出根据本发明实施例的具有“C”型形状的加强圈220，其代替现有技术中使用的典型的“O”形形状。典型地，加强圈220的间隙290是加强圈220的厚度295的两倍。
根据本发明为加强圈220使用“C”形形状代替典型的“O”形形状允许节省材料成本，同时不会不利地影响加强圈220在支撑热沉270方面的性能。加强圈220的“C”形形状节省材料成本的能力在图4a和4b中示出。对于给定尺寸的衬底板400，在根据本发明实施例中其通常由PCB材料制成，图4a示出了用于形成典型的“O”型加强圈410的布局设计。注意到，衬底板400由与衬底250相同的材料制成，以确保CTE与根据本发明的CTE实质上相同。在该示例性实施例中，可以从衬底板400上获得24个“O”型加强圈410，但在形成加强圈410时，“O”型加强圈410内部的区域浪费了。相反，图4b示出了用于形成根据本发明的实施例中的“C”型加强圈420的布局设计。图4b示出了通过与“O”型加强圈相反地形成“C”型加强圈，可以从衬底板400上获得48个“C”型加强圈420。因此，在根据本发明的实施例中，通过使用“C”型加强圈420使得来自衬底板400的产量加倍。“O”型加强圈410和“C”型加强圈420都可以通过衬底制造工厂中通常使用的刳刨工具来切割诸如PCB之类的衬底而由衬底板400制成。衬底制造工厂中的刳刨工具为铣刀，其通常是计算机控制的，并且能够切掉如图4a和4b中示出的加强圈410和420的形状。
为了增强由刳刨工具560制造加强圈410和420的生产力，根据本发明，如图5所示，衬底板400通常可以堆叠成四层或更多层。在图5中，衬底板510、520、530和540垂直堆叠，使得在刳刨工具560在衬底板510中切出加强圈420时，也在衬底板520、530和540中切出加强圈420，从而提高加强圈420的生产能力。根据本发明，根据衬底板510、520、530和540的总厚度和刳刨工具560的能力，可以垂直堆叠多于四层的衬底板510、520、530和540，以提高生产能力。
虽然已经根据示例性实施方式描述了本发明，但本发明不限于此。更确切地说，应当宽泛地解释所附权利要求，以包括本发明的其他变体和实施例，可以由本领域技术人员在不偏离本发明的保护范围和等同物范围的情况下实现所述其他变体和实施例。

Claims (10)

1.一种组件，包括：
衬底；
半导体管芯，安装在衬底的第一侧上；
环形结构，具有与所述管芯可比较的第一厚度并具有形状，所述环形结构接合至衬底的第一侧；以及
热沉，附着至所述环形结构，使得所述环形结构为热沉提供机械支撑，并且其中所述环形结构与衬底由实质上相同的材料制成。
2.根据权利要求1所述的组件，其中所述衬底由印刷电路板PCB材料制成。
3.根据权利要求2所述的组件，其中所述环形结构包括采用环氧树脂半固化片层叠在一起的多个电介质层，每个电介质层具有厚度。
4.根据权利要求3所述的组件，其中所述环形结构还包括焊料掩膜层。
5.根据权利要求3所述的组件，其中通过改变电介质层的数量来调节所述环形结构的第一厚度。
6.根据权利要求3所述的组件，其中通过改变所述多个电介质层中的至少一个的厚度来调节所述环形结构的第一厚度。
7.根据权利要求4所述的组件，其中通过改变焊料掩膜层的厚度来调节所述环形结构的第一厚度。
8.根据权利要求1所述的组件，其中所示环形结构具有“C”形形状。
9.根据权利要求8所述的组件，其中通过采用计算机控制的刳刨工具从PCB板上切出环形结构形状来形成所述环形结构。
10.根据权利要求8所述的组件，其中通过采用计算机控制的刳刨工具从堆叠在彼此顶部上的多个PCB板上切出所述环形结构形状来形成多个环形结构。
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