CN100420004C - 倒装芯片封装体 - Google Patents

倒装芯片封装体 Download PDF

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CN100420004C
CN100420004C CNB2004100016538A CN200410001653A CN100420004C CN 100420004 C CN100420004 C CN 100420004C CN B2004100016538 A CNB2004100016538 A CN B2004100016538A CN 200410001653 A CN200410001653 A CN 200410001653A CN 100420004 C CN100420004 C CN 100420004C
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陈裕文
邱已豪
王盟仁
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

一种倒装芯片封装体，至少包含一载板、一芯片、一拦坝、一散热片、一底胶与复数个导电凸块。该芯片通过复数个导电凸块覆晶接合于载板的上表面，而拦坝设置于载板上且用以支撑该散热片。此外，填充底胶于拦坝所包围的区域中，以使底胶至少包覆该芯片、复数个导电凸块及载板的一部分，并且使底胶能与散热片、拦坝及载板相接合，故能通过散热片、底胶与拦坝所组合而成的加强结构，以降低芯片与载板接合处的应力，以避免连接芯片与载板的导电凸块受到破坏。

Description

倒装芯片封装体
技术领域
本发明涉及一种具散热片的倒装芯片封装体，特别是采用一拦坝结构以控制底胶适当地连接载板与散热片，以降低芯片接点的应力，防止连接芯片与载板间凸块破坏倒装芯片封装体。
背景技术
倒装芯片接合技术(Flip Chip Interconnect Technology，简称FC)乃是将配置于芯片的主动表面上的导电凸块，倒装芯片接合于载板上，使得芯片可经由导电凸块与载板电性连接，并经由载板的内部线路而电性连接至外界的电子装置。值得注意的是，由于倒装芯片接合技术适用于高脚数的芯片封装结构，并同时具有缩小芯片封装面积及缩短讯号传输路径等诸多优点，故倒装芯片接合技术目前已经广泛地应用于芯片封装领域。
承上所述，芯片与载板间以导电凸块电性连接。然而载板的热膨胀系数(约为16×10-6ppm/℃)远大于芯片的热膨胀系数(约为4×10-6ppm/℃)，故倒装芯片封装体进行相关测试或进行运作时，常因为载板与芯片的热膨胀系数的差异，造成连接芯片与载板间导电凸块受到破坏。虽然于芯片主动表面与载板间填充底胶，可用以降低导电凸块所承受的应力，然而其成效有限，故无法完全克服载板与芯片间因热膨胀系数的差异，而造成芯片与载板间导电凸块受到破坏。
有鉴于此，为避免前述倒装芯片封装体的缺点，以提升倒装芯片封装体中的芯片效能，实为一重要的课题。
发明内容
有鉴于上述课题，本发明的目的是提供一种倒装芯片封装体，通过底胶、散热片及拦坝所组合而成的加强结构，以避免连接设置于载板上方的芯片与载板间的导电凸块受到破坏。
为了达成上述目的，本发明提供一种倒装芯片封装体，其技术手段主要包含一载板、一芯片、一拦坝、一散热片、一底胶与复数个导电凸块。该芯片通过复数个导电凸块倒装芯片接合于载板的上表面，而拦坝为一胶体，该拦坝直接与该载板上表面接触；且用以支撑该散热片，而使散热片固定设置于该第一芯片的背面，且散热片与该拦坝直接接触；此外，填充底胶于拦坝所包围的区域中，以使底胶至少包覆该芯片、复数个导电凸块及载板的一部分，并且使底胶能与散热片、拦坝及载板相接合，故能通过散热片、底胶与拦坝所组合而成的加强结构，以降低芯片与载板接合处的应力，避免连接芯片与载板的导电凸块受到破坏。
综上所述，本发明的倒装芯片封装体主要利用拦坝以适当地控制底胶进行包覆芯片、导电凸块及载板的步骤，以避免溢胶的问题。此外，底胶能与散热片、拦坝及载板相接合，故可提供对载板与芯片的热形变限制的能力。再者，在散热片的热膨胀系数与载板相当的倒装芯片封装体中，可使强度较高的载板及散热片作为贴面层(faces)，而包覆芯片的底胶作为核心层，以形成三明治梁(sandwich beam)结构。通过此种结构，可使作为核心层的底胶吸收大部分能量，以减缓芯片接点(导电凸块)所承受的剪应力。另外，由于位于底胶两侧的载板与散热片的热膨胀系数接近，故可减少结构翘曲变形，并增加疲劳寿命及其可靠度。由于散热片设置于芯片背面，故亦能提升封装体的散热效能。
附图说明
图1为现有技术一种倒装芯片封装体的剖面示意图。
图2为本发明较佳实施例的倒装芯片封装体的剖面示意图。
图中符号说明：
110、210芯片
212芯片背面
120、220载板
122、222开口
124、224载板上表面
126、226载板下表面
128、228焊球
240拦坝
250散热片
260底胶
270导电凸块
290粘着层(导热胶)
300底胶填充空间
具体实施方式
以下将参照相关附图，说明依本发明较佳实施例的倒装芯片封装体。
图2显示本发明较佳实施例的倒装芯片封装体。本发明的倒装芯片封装体至少包含一芯片210、载板220、一拦坝240、一散热片250、一底胶260与复数个导电凸块270。其中，芯片210通过复数个导电凸块270倒装芯片接合于载板220的上表面224。再者，利用一粘着层(导热胶)290将散热片250同时粘着于芯片210的背面212上，并使其设置于载板220上表面224的拦坝240上。此外，拦坝240、散热片250、载板上表面224可定义一底胶填充空间300用以填充一底胶260，使至少该芯片210、该载板220及复数个导电凸块270被底胶260所包覆的，以使底胶260与散热片250、拦坝240及载板220相接合，故能通过散热片250、底胶260与拦坝240所形成的加强结构，同时限制载板220与芯片210的热形变，以进一步避免连接载板220与芯片210间的导电凸块270，因载板220与芯片210的热膨胀系数的差异而破坏。此外，该载板220的下表面226可设置有复数个焊球228，用以与外界电性导通。
承上所述，该拦坝240可为一胶体，利用点滞的方式形成于载板220上并环绕于芯片210的外围设置，故拦坝240可为一环形拦坝。再者，上述的底胶亦可以其它的封胶材料替代的，如环氧胶。
此外，在散热片250的热膨胀系数与载板220相当的倒装芯片封装体中，可使强度较高的载板220及散热片250作为贴面层(faces)，而包覆芯片210的底胶260作为核心层，以形成三明治梁(sandwich beam)结构。通过此种结构，可使作为核心层的底胶260吸收大部分能量，以减缓芯片210接点(导电凸块270)所承受的剪应力。另外，由于位于底胶260两侧的载板220与散热片250的热膨胀系数接近，故可减少结构翘曲变形，并增加疲劳寿命及其可靠度。
值得注意的是，该散热片250为一平面板型式，且该散热片250的材质可包含一铜金属或一铝金属，故散热片除可配合底胶与拦坝组合成一加强结构外，更可通过其有较大的导热面积及导热能力以提升封装体的散热效能。
于本实施例的详细说明中所提出的具体的实施例仅为了易于说明本发明的技术内容，而并非将本发明狭义地限制于该实施例，因此，在不超出本发明的精神及以下权利要求的情况，可作种种变化实施。

Claims (9)

1. 一种倒装芯片封装体，包含：
一载板，具有一上表面、一下表面；
一芯片，具有一主动表面及一背面，其中该芯片通过复数个导电凸块与该载板的该上表面倒装芯片接合；
一拦坝，该拦坝为一胶体，该拦坝直接与该载板上表面接触；
一散热片，该散热片设置于该芯片的该背面，且散热片与该拦坝直接接触；
一封胶材料，填充于该拦坝、该散热片、该载板上表面所形成的空间，所述封胶材料至少包覆该芯片、该导电凸块、该载板上表面，且与该散热片及该拦坝相接合。
2. 如权利要求1所述的倒装芯片封装体，其中该散热片与该芯片间更设置一粘着层。
3. 如权利要求2所述的倒装芯片封装体，其中该粘着层为一导热胶。
4. 如权利要求1所述的倒装芯片封装体，其中该封胶材料为一底胶。
5. 如权利要求第1所述的倒装芯片封装体，其中该散热片的材质包含铜金属、或铝金属。
6. 如权利要求第1所述的倒装芯片封装体，其中该散热片为一平面板。
7. 如权利要求第1所述的倒装芯片封装体，其中该拦坝为一环状。
8. 如权利要求第1所述的倒装芯片封装体，其中该拦坝环绕该芯片的外围设置。
9. 如权利要求第1所述的倒装芯片封装体，其中该载板的该下表面更具有一焊球。
CNB2004100016538A 2004-01-09 2004-01-09 倒装芯片封装体 Expired - Lifetime CN100420004C (zh)

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CN102610580A (zh) * 2011-01-21 2012-07-25 Nxp股份有限公司 用于fcbga的非金属加强圈
CN102623414A (zh) * 2012-04-11 2012-08-01 日月光半导体制造股份有限公司 半导体封装

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