CN102194774A - 散热型覆晶封装结构及其应用 - Google Patents

散热型覆晶封装结构及其应用 Download PDF

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CN102194774A
CN102194774A CN201010127924XA CN201010127924A CN102194774A CN 102194774 A CN102194774 A CN 102194774A CN 201010127924X A CN201010127924X A CN 201010127924XA CN 201010127924 A CN201010127924 A CN 201010127924A CN 102194774 A CN102194774 A CN 102194774A
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chip
lead frame
pin
heat
circuit board
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杨玉林
董利铭
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Richtek Technology Corp
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Richtek Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明公开一种散热型覆晶封装结构及其应用。该散热型覆晶封装结构包含芯片倒置于导线架的下方，该芯片上表面的凸块与该导线架的引脚电性连接，该芯片下表面有晶背金属裸露在封装胶体外。使用时，若将该覆晶封装结构应用于电路板上，则将该芯片的凸块及引脚与电路板的金属电性连接，以及将该芯片的晶背金属与电路板上的导热材料热接触。

Description

散热型覆晶封装结构及其应用
技术领域
本发明涉及一种覆晶(flip-chip)封装结构，特别是关于一种散热型覆晶封装结构。
背景技术
覆晶封装也称为「倒晶封装」，是芯片封装技术的一种。此封装技术有别于过去的芯片封装，主要在于：以往是将芯片贴附在垫片(chip pad)上，再用打线法(wire bonding)将芯片与基板上的连结点连接，而覆晶封装是将芯片的连接点沉积成凸块(bump)，然后将芯片翻转(flip)过来使凸块与基板上的连结点直接连结。覆晶封装可以达到低讯号干扰、电性佳、最低连接电路损耗及有效率的散热途径。应用于微细间距(fine pitch)、高频或输入输出(I/O)脚数很多时，覆晶技术就可以展现其优点。
未来电子产品持续朝向轻薄短小、高速、高脚数发展，以导线架为基础的传统封装将渐不适用，其应用范围也将局限于低阶/低单价的产品。在未来覆晶封装的发展趋势上，依然会朝着高脚数、细间距的目标前进。因此，需要有散热能力较高的覆晶封装结构。
发明内容
本发明的目的之一，在于提出一种散热型覆晶封装结构及其应用。
根据本发明，一种散热型覆晶封装结构包含具有引脚的导线架，具有凸块及晶背金属的芯片置于该导线架下方，该凸块在该芯片的上表面与该引脚电性连接，该晶背金属在该芯片的下表面，以及包覆该芯片及该导线架的封装胶体，裸露出该晶背金属。
根据本发明，若将该覆晶封装结构应用于电路板上，则将该芯片的凸块及引脚与电路板的金属电性连接，以及将该芯片的晶背金属与电路板上的导热材料热接触。
根据本发明，芯片的热能可以通过晶背金属向外部传导，散热效果较佳。
附图说明
图1是本发明所使用的芯片结构；
图2是本发明的第一实施例；
图3是本发明的第二实施例；以及
图4是图2的实施例的应用示意图。
具体实施例
下面结合说明书附图对本发明的具体实施方式做详细描述。
图1是本发明所使用的芯片结构，芯片10的连接点有凸块12供电性连接外部电路。除了凸块12之外，芯片10的背面贴附一晶背金属14，用以将芯片10的热能往外部传导。本申请文件中，所述“晶背金属”即为置于芯片背面的金属，主要用于散热，因此要求该金属的热传导系数高，散热效果好，也可称之为“散热金属”；常见的，该晶背金属可以是银、锡等等，后续不再赘述。
图2是本发明的第一实施例，其包含具有多个引脚162的导线架16，以及封装胶体18包覆凸块12、芯片10的部分区域以及导线架16的部份区域。芯片10不需要像现有的覆晶封装被翻转，而是直接倒置于导线架16下，引脚162和凸块12形成电性连接，但是还是与现有的覆晶封装一样具有低讯号干扰、电性佳、最低连接电路损耗及有效率的散热途径等优点。晶背金属14裸露于封装胶体18外，使芯片10直接向外部环境散热，因此具有更好的散热效果。在此实施例中，导线架16的引脚162仅部分被封装胶体18包覆，另部分形成外引脚。
图3是本发明的第二实施例。与图2的实施例相同，芯片10倒置于导线架16下，引脚162和凸块12形成电性连接，晶背金属14裸露于封装胶体20外。但是本实施例的导线架16完全被封装胶体20包覆，因此无外引脚延伸到封装胶体20外，只有裸露出引脚162的部分下表面164。
图4是图2的实施例的应用示意图。将图2的覆晶封装置于电路板22上，芯片10通过凸块12及引脚162与电路板22的金属24电性连接，晶背金属14热接触电路板22上的导热材料26。可以将晶背金属14焊接导热材料26，或将导热胶涂布在二者之间。芯片10在工作期间，其产生的热经晶背金属14传递到导热材料26上，因此可以使芯片10于稳定的工作温度下。在其它实施例中，电路板22上的导热材料26可直接使用电路板22的金属24。
以上，仅为本发明的较佳实施例，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求所界定的保护范围为准。

Claims (4)

1.一种散热型的覆晶封装结构，其特征在于，包含：
具有引脚的导线架；
具有凸块及晶背金属的芯片，置于该导线架下方，该凸块在该芯片的上表面与该引脚电性连接，该晶背金属在该芯片的下表面；以及
包覆该芯片及该导线架的封装胶体，裸露出该晶背金属，使其可接触到外部电路板上的导热材料。
2.如权利要求1所述的覆晶封装结构，其特征在于，该封装胶体包覆该凸块、该导线架的部份区域以及该芯片的部分区域，露出该导线架的引脚。
3.如权利要求2所述的覆晶封装结构，其特征在于，该封装胶体露出该引脚的部分下表面。
4.一种如权利要求1所述的覆晶封装结构的应用，将该覆晶封装结构应用于电路板上，其特征在于，包括：
将该芯片的凸块及引脚与电路板的金属电性连接，以及
将该芯片的晶背金属与电路板上的导热材料热接触。
CN201010127924XA 2010-03-19 2010-03-19 散热型覆晶封装结构及其应用 Pending CN102194774A (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165562A (zh) * 2011-12-15 2013-06-19 飞思卡尔半导体公司 无引线封装半导体器件
CN107706164A (zh) * 2017-10-18 2018-02-16 天津力芯伟业科技有限公司 一种吸热式碳化硅芯片封装
CN112382621A (zh) * 2020-11-09 2021-02-19 海光信息技术股份有限公司 多芯片封装模块及方法
WO2021257312A1 (en) 2020-06-17 2021-12-23 Texas Instruments Incorporated Semiconductor package including undermounted die with exposed backside metal

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US5625226A (en) * 1994-09-19 1997-04-29 International Rectifier Corporation Surface mount package with improved heat transfer
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US20030214049A1 (en) * 2002-05-16 2003-11-20 Hortaleza Edgardo R. Heat dissipating flip-chip ball grid array
CN1507041A (zh) * 2002-12-09 2004-06-23 先进封装解决方案私人有限公司 带有倒焊晶片的无引线半导体封装结构及制造方法
CN1641865A (zh) * 2004-01-09 2005-07-20 日月光半导体制造股份有限公司 覆晶封装体
US20090267171A1 (en) * 2008-04-24 2009-10-29 Micron Technology, Inc. Pre-encapsulated cavity interposer

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685148A (ja) * 1992-09-04 1994-03-25 Nec Corp 樹脂封止型半導体装置
US5625226A (en) * 1994-09-19 1997-04-29 International Rectifier Corporation Surface mount package with improved heat transfer
US5986334A (en) * 1996-10-04 1999-11-16 Anam Industrial Co., Ltd. Semiconductor package having light, thin, simple and compact structure
US20030214049A1 (en) * 2002-05-16 2003-11-20 Hortaleza Edgardo R. Heat dissipating flip-chip ball grid array
CN2575844Y (zh) * 2002-09-29 2003-09-24 威盛电子股份有限公司 高散热效率的封装结构
CN1507041A (zh) * 2002-12-09 2004-06-23 先进封装解决方案私人有限公司 带有倒焊晶片的无引线半导体封装结构及制造方法
CN1641865A (zh) * 2004-01-09 2005-07-20 日月光半导体制造股份有限公司 覆晶封装体
US20090267171A1 (en) * 2008-04-24 2009-10-29 Micron Technology, Inc. Pre-encapsulated cavity interposer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165562A (zh) * 2011-12-15 2013-06-19 飞思卡尔半导体公司 无引线封装半导体器件
CN107706164A (zh) * 2017-10-18 2018-02-16 天津力芯伟业科技有限公司 一种吸热式碳化硅芯片封装
WO2021257312A1 (en) 2020-06-17 2021-12-23 Texas Instruments Incorporated Semiconductor package including undermounted die with exposed backside metal
EP4169067A4 (en) * 2020-06-17 2023-12-27 Texas Instruments Incorporated SEMICONDUCTOR PACKAGE INCLUDING UNDERMOUNTED CHIP WITH EXPOSED BACK METAL
CN112382621A (zh) * 2020-11-09 2021-02-19 海光信息技术股份有限公司 多芯片封装模块及方法

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Application publication date: 20110921