CN1025261C - 具有识别电路的半导体集成电路芯片 - Google Patents
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Abstract
一种具有一个识别电路的半导体集成电路芯片包括一对电源供给端、多个输入端及一个连接在任一电源供给端和任一输入端间的识别电路装置。该识别电路装置包括:一个限制在电源供给端和输入端之间的输入电位差、具有一预定限幅电压电平的电压限幅器及与电压限幅器连接的选择装置,根据电流通路是否在制造工艺中形成来决定芯片的识别信息。芯片的识别测试是用已有的输入端、输出端和电源端完成的,无须额外测试、特征管脚、激光设备等。
Description
本发明涉及一种半导体集成电路芯片,特别涉及一种在其内具有识别电路的半导体集成电路(IC)芯片,该识别电路用于通过测试把芯片分类。
最近,随着半导体技术的发展,在整个工业界存在一种实行电子电路系列化的不断增长的趋势。因此,要求电子系统的特征要适应每个领域的特色。由于这个原因,半导体制造厂家一直没有忽视将半导体产品多样化的努力,以满足用户的各种各样的需求。例如,按照动态随机询问存贮器(DRAM)的存储容量已被增大到兆位,开发了除一种基本操作模式外的其它操作模式。也就是,在1M或4M的DRAM中,根据输出数据的数目,其操作模式可分为1位,4位和8位等等,根据输入的控制信号,其操作模式又可分为快速页模式(fast page mode),半字节模式(nibble mode)和静态列模式(static column mode)等等。所以,为了满足用户的各种需求,DRAM的供应者现在提供了各种执行不同模式的DRAM,这取决于在制造工艺当中,除配置一种DRAM基本操作模式外,通过有选择地提供一些专用操作模式而选定不同模式。例如,快速页模式在单一DRAM生产线中做为一种基本操作模式,而半字节或静态列模式DRAM则可通过分别在制造过程中有选择地提供操作模式而得
到。
这种选择措施是逐片进行的,制得的DRAM按模式分拣。接着,在DRAM被制成之后,在组装工艺当中,经过划片工艺,片子被分割成一个个的晶片或芯片,经过晶片固定,焊线和模塑成型工艺,分开的晶片封装在一个专用的封装组件,通过产品测试,再标上产品数据,诸如系列号、生产日期和生产线后,封装的DRAM成为最终产品。
然而,用前面所述工艺来制造DRAM时,当在单一生产线上生产晶片和芯片时,分拣成各种模式的晶片或芯片经常与其它种类芯片相混淆。在这种情况下,操作模式不一致的产品在下一步测试当中,被做为一个错误芯片检出,并按劣质产品处理,致使成品率下降。
另外,为防止同类晶片与其它类晶片相混淆,需要加倍小心,因而也降低了工作效率。
于是,需要一种技术,即当不同模式的芯片在封装前相互混杂时,在测试步骤当中,可以分拣或识别出同类芯片的技术。
在美国专利US-4,150,331和US-4,510,673中已公开这样一种半导体芯片的识别技术。在US-4,150,331中,公开了一种利用在芯片表面上的可编程的电路装置识别各种芯片的技术。该电路装置是根据附加设置的测试及识别管脚和选择的输入/输出管脚之间是否形成一二极管,而编程一个识别码。
然而,上述技术有一个缺点,即因为设置了额外的测试管脚,包
装尺寸变大,严重影响半导体芯片的成本。
在US-4,510,673中公开了一种技术,按此技术,用激光器在半导体芯片背面做出一专用的识别标记,人或设备可用激光或光学设备加以区别这些识别标记。然而,这种专利技术也有一个缺陷,即要配备昂贵的激光设备,来标出该专用识别标记,例如,生产线,制造日期。
本发明的一个目的是提供一种具有新的识别电路而不需要附加测试和识别管脚的半导体集成电路芯片,从而解决了上述现有技术中的问题。
本发明的另一个目的是提供一种具有识别电路的半导体集成电路芯片,该识别电路的结构简单、易于识别半导体芯片。
为了实现本发明的上述目的,提供一种半导体集成电路芯片,它具有一对电源供电端和多个输入端,以及一种连在任一电源供电端和任一输入端之间的识别电路装置。其中,
所说的识别电路装置包括:
一个电压限幅器,它具有预定的限定电压电平,用以限制在一个所说的电源供给端和一个所说的输入端之间的输入电位差,和
一个选择装置,它与所说的电压限幅器串联,用以根据在所说的芯片制造过程中是否形成电流通路来确定所说的芯片的识别信息。
根据本发明,还提供一种半导体集成电路芯片,它具有一对电源供给端和至少三个输入端,以及一个与一个所说的电源供给端相连,又
与所说的至少三个输入端中的三个端子相连的识别电路装置。其中,
所说的识别电路装置包括:
一个电压限幅器,它具有预定的限定电压电平,用以限制在所说的电源供给端和所说的三个输入端之一之间的输入电位差,然后根据对限定的电压电平的分压产生一个预定的控制电压;
一个选择装置,它连在所说三个输入端中的二个输入端之间,用以根据在所说芯片的制造工艺中是否形成电流通路来决定所说的芯片的识别信息;以及
一个与所说的选择装置串联的开关装置,所说的开关装置被由来自所说的电压限幅器的所说控制电压来接通。
按这些结构,本发明可采用一种不附加额外的管脚(诸如测试脚和识别脚)的芯片识别电路。
图1是一种根据本发明的具有识别电路的半导体集成电路芯片的实施例简图。
图2是一种根据本发明的具有识别电路的半导体集成电路芯片的另一实施例简图。
图3是图1和图2所示的选择装置的一种变型的电路图。
图4以简化的形式表明了根据本发明的具有识别电路的半导体集成电路芯片的又一实施例。
下文将参照附图详细介绍本发明的一个优选实施例。
图1以原理图的形式叙述了具有本发明的识别电路的半导体集成电路芯片。在图1中,一个集成电路芯片1包括一个内电路10、输入保护电路PC1~PCn、输出缓冲器B1~Bn、输入端IN1~INn、输出端OUT1~OUTn以及一对电源供给端Vdd和Vss。IC芯片与一个电源连接(未示出),通过电源供给端Vdd,比如接受5V的电源电压,通过电源供给端Vss接受一个地电位。从所说的电源供给端Vdd和Vss接受工作电压的内电路10,根据在输入端IN1~INn收到的外加输入信号执行一种给定的功能,并产生预定的输出信号,送到输出端OUT1~OUTn。另外,所说的输入端IN1~INn均通过各自的输入保护电路PC1~PCn与内电路10相连接,防止内电路10由于加到输入端的噪声电压、电冲击等产生的损坏。
输出端OUT1~OUTn均通过各自的输出缓冲器B1~Bn与内电路10相连接。
一个识别电路20,本发明的特征部分被接在诸输入端的一个输入端IN1和IC芯片1的电源供给端Vss之间。该识别电路包括:一个电压限幅器22和一个选择装置24。提供电压限幅器22是为把施加在输入端IN1和电源端Vss之间的输入信号的电平限制在一个预定的逻辑电平,然后再施加到内电路10。此电压限幅器22由多个串接的MOS晶体管M1~Mn组成,它们各自的栅极与各自的漏极相连接。另外,该电压限幅器22能用每个MOS晶体管的阈值电压和设定预定逻辑电平。
例如,当TTL电平被施加到输入端时,预定逻辑电平将设置得略高于2.5V;当CMOS电平被施加到输入端时,该预定逻辑电平将略高于+3V。
虽然,在本实施例中用了MOS晶体管的二极管的接法,人们应注意,任何具有一预定阈值电压而单向导电的器件,例如PN结二极管或齐纳二极管等均可用作电压限幅器。
提供选择装置24是为在制造过程当中确定流过电压限幅器22的电流,它与电压限幅器22串联。为设置选择装置24,这里采用了一种简单的选择处理技术,即用一根在制造工艺当中形成的熔断丝或金属丝的连接或不连接确定芯片的模式。在此实施例中,在熔断丝形成之后,芯片的识别信息被在其内规定了用激光烧毁工艺把熔断丝熔断的选择工艺写入。
例如,在芯片制造工艺中,芯片中的熔断丝FU处于连接状态,使DRAM为快速页模式操作,FU熔掉后,使DRAM为半字节模式操作,由此可识别芯片。在芯片生产工序的测试步骤中,对于已做前述识别处理的芯片,将输入端IN1与一预定的高压源2,例如一个约15V的电压源相连接,而电源供给端Vss与安培表3相连接,这就可能区别DRAM的模式。用电流表3检测电流的流动,如果有电流流过,该样品被认定是高速页模式操作的DRAM;反之,如果没有电流流过,该样品则被认定是半字节模式操作的DRAM。
这里,在半字节模式的情况,熔断丝被熔掉,所以在芯片的正常
操作当中,输入信号被传送给内电路10,而与识别电路20的存在无关;但是在高速页模式的情况下,如果它不是用了一个电压限幅器22,输入端IN1通过熔断丝FU应当总处于逻辑“0”状态。这种出现的现象将由电压限幅器22防止。再详细些,当逻辑“0”被施加到输入端IN1时,逻辑“0”被输入到内电路10,与识别电路20的连接状态无关;但是当逻辑“1”被施加到输入端IN1时,电流流过识别电路20,因此在电限幅器22内就产生一个预定的电压差,使内电路10有一个逻辑“1”的输入。
识别电路20最好通过输入保护电路PC1与输入端IN1相连接,以保护识别电路免遭外来电冲击等造成的损坏。
图2表明依照本发明的半导体集成电路芯片的另一个实施例,其中,电路结构与第一实施例相同,只是识别电路20被连接在电源供给端Vdd和输入端IN1之间。由于加给输入端的+15V电压高于识别测试中来自电源供给端Vdd的外加+5V电压,所以芯片的操作基本规则与第一实施例相同。
图3表明选择装置24的改型,用于识别两种或两种以上的芯片。如图3所示,该选择装置24包括许多MOS晶体管MA1~MAn,其栅极均与它们的漏极相连接,许多熔断丝FU1~FUn分别连到各自的MOS晶体管。MOS晶体管与熔断丝组合的各线路相互并联连接在电压限幅器22和电源供给端Vss(或Vdd)之间。
为了用上述结构电路识别芯片,识别信息可由列于表1的流过选择装置的电流值给出。
表1
熔断丝的连接状态 识别
FU1 FU2 FU3 信息
快速页模式 连接 连接 连接 I1+I2+I3
半字节模式 熔掉 连接 连接 I2+I3
静态列模式 熔掉 熔掉 连接 I3
其它模式 熔掉 熔掉 熔掉 0
图4表示识别电路的一种改型,用来识别两种或两种以上的芯片。在图4中,识别装置30与功率源供给端Vss以及三个输入端IN1~IN3相连接。识别装置30包括一个电压限幅器32,一个选择装置34和一个开关装置36。
电压限幅器32是这样构成的,使得它能把加在输入端IN3和电源供给端Vss之间的输入电压差限制在内电路10接受的逻辑电平,然后划分给定的逻辑电平,以产生一个预定的控制电压VR。该电压限幅器包括多个其栅极被连到各自的漏极的MOS晶体管MB1~MBn和一个与这
些MOS晶体管相连接的电阻R,所说的多个MOS晶体管和电阻被连在输入端IN3和电源供给端Vss之间。在电阻R两端分配到的电压被施加给开关装置36作为一个控制电压VR。开关装置36与选择装置串联连接在输入端IN1和IN2之间,根据所说的电压限幅器32的控制电压VR,将切换要被导通的电流。开关装置36由多个MOS晶体管MC1~MCn组成,其中,每个MOS晶体管的漏极与输入端IN1相连接;其栅极施加以控制电压VR;源极被连接到选择装置34的相应的熔断丝,后文介绍。
在此实施例中,该选择装置34由多个熔断丝FUA1~FUAn组成,每根熔断丝与所说的开关装置36的相应的MOS晶体管相连接。MOS晶体管和熔断丝组成的各组合线路互相并联连接在输入端IN1和IN2之间。这里,选择装置的各个熔断丝的熔化是在芯片的制造过程中完成的,以提供所需的识别信息。
为了识别如上所述实施例的设置了识别电路的芯片,输入端IN1与一预定电压,如5V的电源相连接,输入端IN2与一个安培表A相连接,而一个更高电压,如15V的电压电源被连接在输入端IN3和电源供给端Vss之间。按照这些电源的供电,将有电流流过电压限幅器32,一预定电压降落在电阻R上,产生加给开关装置36的控制电压VR。由于控制电压VR,开关装置36的各个MOS晶体管MC1到MCn变为通导。这样一来,在输入端IN1和IN2间流过的电流由安培表A指示出来。这里,根据熔断丝FUA1~FUAn是否被熔掉,所得到的电流值示于表2。
表2
熔断丝的连接状态 识别
FUA1 FUA2 FUA3 信息
连接 连接 连接 I1+I2+I3
熔掉 连接 连接 I2+I3
熔掉 熔掉 连接 I3
熔掉 熔掉 熔掉 0
应注意:表2中,芯片能写入能识别四种不同模式芯片的识别信息。
当芯片未处于芯片识别测试时,地电位通过电阻R加给开关装置36的各个MOS晶体管MC1~MCn的栅极,这样就保证了芯片的正常操作。
如上所述,根据本发明,在片子制造过程当中,通过使这种简单的电路有选择地连接或不连接而把芯片的识别信息写入,该写入的识别信息在芯片的通常组装工艺的测试步骤中被测,从而可检测出同类的芯片,并在随后的工艺中分别处理。
在本发明的芯片中,芯片的识别测试是通过已有的输入端、输出端和电源供给端,以不同于常规的方法完成的,所以常规制造体系在不作任何改变情况下,得以极大限度的利用。这是很经济的,也是所希求的。
而且,本发明的芯片不要求识别芯片的额外测试、识别管脚、昂贵的激光设备等。
人们应注意:已介绍了依照本发明的芯片对于上述实施例中的MOS晶体管是有用的,但根据各种要求也能适用于各种不同的应用。这样,在所附权利要求书所限定的本发明的范畴内本芯片可做出各种形式的改型。
Claims (4)
1、一种半导体集成电路芯片,该芯片具有一对电源供给端,多个输入端和连接于任一所述电源电压供给端和任一所述输入端之间的改进识别电路装置,其特征在于,所述改进的识别电路装置包括:
一个用于限制所述的一对电源供给端的一个与所述多个输入端的一个端间的电位差、且具有预定限制电压电平的电压限幅器;
串联连接到所述电压限幅器的选择装置,包括由其栅极分别连接到其漏极的MOS晶体管和分别连接到源极的熔断丝组成的多个组合线路,所述组合线路相互并联连接,根据所述熔断丝的数目来设定所述芯片的识别信息,按照芯片制造过程中电流通路的构造来判定该芯片的识别信息。
2、一种半导体集成电路芯片,该芯片具有一对电源供给端、至少三个输入端,以及一个识别电路装置,所说的识别电路装置与一个所说的电源供给端相连接,还与至少三个输入端的三个端相连接,其特征在于,所说的识别电路装置包括:
一个用于限制所说的电源供给端和所说的三个输入端的一端之间的电位差,再通过划分被限定的电压电平产生一个预定的控制电压的电压限幅器;
一个用于根据电流通路是否在所说的芯片的制造过程中被形成来判定识别信息的、连接在所说的三个输入端的其余两端之间的选择装置;以及
一个与所说的选择装置串联连接的开关装置,所说的开关装置是由来自所说的电压限幅器的所说控制电压所导通的;
3、一种如权利要求2所限定的半导体集成电路芯片,其中,所说的电压限幅器包括:
多个串联连接的MOS晶体管,其各自的栅极与各自的漏极相连接;以及
一个与所说的多个MOS晶体连接的电阻,所说的限幅电压电平是所说的电阻的端电压与所说的多个MOS晶体管的多个阈值电压之总和,所说的控制电压是所说的电阻的端电压;
4、一种如权利要求2所限定的半导体集成电路芯片,其中,所说的选择装置包括多个熔断丝,所说的开关装置包括多个MOS晶体管,所说的多个熔断丝的每一个与所说的多个MOS晶体管的相应一个是相互串联连接,所说的MOS晶体管是被所说的施加到其栅极的控制电压所导通的,所说芯片的识别信息是根据所说的熔断丝被熔掉的数目决定的。
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KR1019900007481A KR920007535B1 (ko) | 1990-05-23 | 1990-05-23 | 식별회로를 구비한 반도체 집적회로 칩 |
KR7481/90 | 1990-05-23 |
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US (1) | US5103166A (zh) |
JP (2) | JPH079753B2 (zh) |
KR (1) | KR920007535B1 (zh) |
CN (1) | CN1025261C (zh) |
DE (1) | DE4026326C2 (zh) |
FR (1) | FR2662505B1 (zh) |
GB (1) | GB2244339B (zh) |
HK (1) | HK21896A (zh) |
IT (1) | IT1242519B (zh) |
NL (1) | NL194814C (zh) |
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Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5332973A (en) * | 1992-05-01 | 1994-07-26 | The University Of Manitoba | Built-in fault testing of integrated circuits |
US5363134A (en) * | 1992-05-20 | 1994-11-08 | Hewlett-Packard Corporation | Integrated circuit printhead for an ink jet printer including an integrated identification circuit |
US5787174A (en) * | 1992-06-17 | 1998-07-28 | Micron Technology, Inc. | Remote identification of integrated circuit |
JP3659981B2 (ja) * | 1992-07-09 | 2005-06-15 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | ダイ特定情報に特徴付けられるダイ上の集積回路を含む装置 |
US7158031B2 (en) * | 1992-08-12 | 2007-01-02 | Micron Technology, Inc. | Thin, flexible, RFID label and system for use |
US5426375A (en) * | 1993-02-26 | 1995-06-20 | Hitachi Micro Systems, Inc. | Method and apparatus for optimizing high speed performance and hot carrier lifetime in a MOS integrated circuit |
US5440230A (en) * | 1993-04-02 | 1995-08-08 | Heflinger; Bruce L. | Combinatorial signature for component identification |
US5686759A (en) * | 1995-09-29 | 1997-11-11 | Intel Corporation | Integrated circuit package with permanent identification of device characteristics and method for adding the same |
US5818251A (en) * | 1996-06-11 | 1998-10-06 | National Semiconductor Corporation | Apparatus and method for testing the connections between an integrated circuit and a printed circuit board |
US5867505A (en) * | 1996-08-07 | 1999-02-02 | Micron Technology, Inc. | Method and apparatus for testing an integrated circuit including the step/means for storing an associated test identifier in association with integrated circuit identifier for each test to be performed on the integrated circuit |
US5927512A (en) * | 1997-01-17 | 1999-07-27 | Micron Technology, Inc. | Method for sorting integrated circuit devices |
US6100486A (en) | 1998-08-13 | 2000-08-08 | Micron Technology, Inc. | Method for sorting integrated circuit devices |
US6072574A (en) | 1997-01-30 | 2000-06-06 | Micron Technology, Inc. | Integrated circuit defect review and classification process |
US5844803A (en) * | 1997-02-17 | 1998-12-01 | Micron Technology, Inc. | Method of sorting a group of integrated circuit devices for those devices requiring special testing |
US5915231A (en) * | 1997-02-26 | 1999-06-22 | Micron Technology, Inc. | Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture |
US5856923A (en) | 1997-03-24 | 1999-01-05 | Micron Technology, Inc. | Method for continuous, non lot-based integrated circuit manufacturing |
US5959912A (en) * | 1997-04-30 | 1999-09-28 | Texas Instruments Incorporated | ROM embedded mask release number for built-in self-test |
US5984190A (en) * | 1997-05-15 | 1999-11-16 | Micron Technology, Inc. | Method and apparatus for identifying integrated circuits |
US5907492A (en) | 1997-06-06 | 1999-05-25 | Micron Technology, Inc. | Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs |
US7120513B1 (en) | 1997-06-06 | 2006-10-10 | Micron Technology, Inc. | Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICS will undergo, such as additional repairs |
US6339385B1 (en) | 1997-08-20 | 2002-01-15 | Micron Technology, Inc. | Electronic communication devices, methods of forming electrical communication devices, and communication methods |
US6049624A (en) | 1998-02-20 | 2000-04-11 | Micron Technology, Inc. | Non-lot based method for assembling integrated circuit devices |
KR100261223B1 (ko) | 1998-05-04 | 2000-07-01 | 윤종용 | 식별 회로를 구비하는 반도체장치 및 그 기능 식별방법 |
US6265232B1 (en) | 1998-08-21 | 2001-07-24 | Micron Technology, Inc. | Yield based, in-line defect sampling method |
US6268228B1 (en) * | 1999-01-27 | 2001-07-31 | International Business Machines Corporation | Electrical mask identification of memory modules |
US6351116B1 (en) | 1999-09-30 | 2002-02-26 | Rockwell Automation Technologies, Inc. | System and method for on-line hall sensor programming |
US6791157B1 (en) * | 2000-01-18 | 2004-09-14 | Advanced Micro Devices, Inc. | Integrated circuit package incorporating programmable elements |
US6430016B1 (en) | 2000-02-11 | 2002-08-06 | Micron Technology, Inc. | Setpoint silicon controlled rectifier (SCR) electrostatic discharge (ESD) core clamp |
US6772356B1 (en) | 2000-04-05 | 2004-08-03 | Advanced Micro Devices, Inc. | System for specifying core voltage for a microprocessor by selectively outputting one of a first, fixed and a second, variable voltage control settings from the microprocessor |
DE10018356B4 (de) * | 2000-04-13 | 2005-05-04 | Siemens Ag | Verfahren zum Identifizieren eines elektronischen Steuergeräts und dafür geeignetes Steuergerät |
WO2002050910A1 (fr) * | 2000-12-01 | 2002-06-27 | Hitachi, Ltd | Procede d'identification de dispositif de circuit integre semi-conducteur, procede de production de dispositif de circuit integre semi-conducteur et dispositif correspondant |
GB2374426B (en) * | 2001-02-07 | 2003-10-29 | Samsung Electronics Co Ltd | Apparatus for recognizing chip identification and semiconductor device comprising the apparatus |
KR100393214B1 (ko) | 2001-02-07 | 2003-07-31 | 삼성전자주식회사 | 패드의 수를 최소화하기 위한 칩 식별 부호 인식 장치 및이를 내장한 반도체 장치 |
US7188261B1 (en) | 2001-05-01 | 2007-03-06 | Advanced Micro Devices, Inc. | Processor operational range indicator |
JP3941620B2 (ja) * | 2001-08-31 | 2007-07-04 | 株式会社デンソーウェーブ | Idタグ内蔵電子機器 |
US7573159B1 (en) | 2001-10-22 | 2009-08-11 | Apple Inc. | Power adapters for powering and/or charging peripheral devices |
DE10241141B4 (de) * | 2002-09-05 | 2015-07-16 | Infineon Technologies Ag | Halbleiter-Bauelement-Test-Verfahren für ein Halbleiter-Bauelement-Test-System mit reduzierter Anzahl an Test-Kanälen |
US7319935B2 (en) * | 2003-02-12 | 2008-01-15 | Micron Technology, Inc. | System and method for analyzing electrical failure data |
JP4272968B2 (ja) * | 2003-10-16 | 2009-06-03 | エルピーダメモリ株式会社 | 半導体装置および半導体チップ制御方法 |
KR100688518B1 (ko) * | 2005-01-12 | 2007-03-02 | 삼성전자주식회사 | 개별 칩들의 디바이스 정보를 직접 판독할 수 있는시그너처 식별 장치를 갖는 멀티 칩 패키지 |
GB0617697D0 (en) * | 2006-09-08 | 2006-10-18 | Algotronix Ltd | Method of actively tagging electronic designs and intellectual property cores |
KR101161966B1 (ko) * | 2010-07-09 | 2012-07-04 | 에스케이하이닉스 주식회사 | 칩 어드레스 회로를 포함하는 멀티 칩 패키지 장치 |
US9879897B2 (en) | 2010-12-02 | 2018-01-30 | Frosty Cold, Llc | Cooling agent for cold packs and food and beverage containers |
US10155698B2 (en) | 2010-12-02 | 2018-12-18 | Frosty Cold, Llc | Cooling agent for cold packs and food and beverage containers |
CN104228347B (zh) * | 2013-06-18 | 2016-08-17 | 研能科技股份有限公司 | 喷墨头芯片 |
JP6091393B2 (ja) * | 2013-10-01 | 2017-03-08 | 三菱電機株式会社 | 半導体装置 |
US20160065334A1 (en) * | 2014-08-29 | 2016-03-03 | R&D Circuits, Inc | Structure and Implementation Method for implementing an embedded serial data test loopback, residing directly under the device within a printed circuit board |
JP7305934B2 (ja) * | 2018-08-02 | 2023-07-11 | 富士電機株式会社 | 差動増幅回路を備える装置 |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE756139A (fr) * | 1969-09-15 | 1971-02-15 | Rca Corp | Circuit intermediaire integre pour le couplage d'un circuit de commandea impedance de sortie faible a une charge a impedance d'entree elevee |
US4020365A (en) * | 1976-03-22 | 1977-04-26 | Intersil Incorporated | Integrated field-effect transistor switch |
US4055802A (en) * | 1976-08-12 | 1977-10-25 | Bell Telephone Laboratories, Incorporated | Electrical identification of multiply configurable circuit array |
US4150331A (en) * | 1977-07-29 | 1979-04-17 | Burroughs Corporation | Signature encoding for integrated circuits |
US4301403A (en) * | 1978-12-21 | 1981-11-17 | Measurement Technology Ltd. | Electrical circuit testing |
DE3002894C2 (de) * | 1980-01-28 | 1982-03-18 | Siemens AG, 1000 Berlin und 8000 München | Monolithisch integrierte Halbleiterschaltung mit Transistoren |
JPS57191896A (en) * | 1981-05-21 | 1982-11-25 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
US4480199A (en) * | 1982-03-19 | 1984-10-30 | Fairchild Camera & Instrument Corp. | Identification of repaired integrated circuits |
US4465973A (en) * | 1982-05-17 | 1984-08-14 | Motorola, Inc. | Pad for accelerated memory test |
JPS59112499A (ja) * | 1982-12-18 | 1984-06-28 | Mitsubishi Electric Corp | 半導体メモリ装置 |
JPS59129999A (ja) * | 1983-01-17 | 1984-07-26 | Mitsubishi Electric Corp | 半導体メモリ装置 |
JPS59157900A (ja) * | 1983-02-25 | 1984-09-07 | Nec Corp | 冗長ビツト使用の検出回路を有するメモリ装置 |
US4510673A (en) * | 1983-06-23 | 1985-04-16 | International Business Machines Corporation | Laser written chip identification method |
US4595875A (en) * | 1983-12-22 | 1986-06-17 | Monolithic Memories, Incorporated | Short detector for PROMS |
GB8428405D0 (en) * | 1984-11-09 | 1984-12-19 | Membrain Ltd | Automatic test equipment |
US4719418A (en) * | 1985-02-19 | 1988-01-12 | International Business Machines Corporation | Defect leakage screen system |
JPH0782746B2 (ja) * | 1985-03-25 | 1995-09-06 | 株式会社日立製作所 | ダイナミツク型ram |
JPS61265829A (ja) * | 1985-05-20 | 1986-11-25 | Fujitsu Ltd | 半導体集積回路 |
DE3526485A1 (de) * | 1985-07-24 | 1987-02-05 | Heinz Krug | Schaltungsanordnung zum pruefen integrierter schaltungseinheiten |
US4698589A (en) * | 1986-03-21 | 1987-10-06 | Harris Corporation | Test circuitry for testing fuse link programmable memory devices |
US4970454A (en) * | 1986-12-09 | 1990-11-13 | Texas Instruments Incorporated | Packaged semiconductor device with test circuits for determining fabrication parameters |
US4779043A (en) * | 1987-08-26 | 1988-10-18 | Hewlett-Packard Company | Reversed IC test device and method |
US4853628A (en) * | 1987-09-10 | 1989-08-01 | Gazelle Microcircuits, Inc. | Apparatus for measuring circuit parameters of a packaged semiconductor device |
JPH0175400U (zh) * | 1987-11-09 | 1989-05-22 | ||
GB2220272B (en) * | 1988-06-29 | 1992-09-30 | Texas Instruments Ltd | Improvements in or relating to integrated circuits |
JPH0291898A (ja) * | 1988-09-27 | 1990-03-30 | Nec Corp | 半導体記憶装置 |
JP2705142B2 (ja) * | 1988-10-13 | 1998-01-26 | 日本電気株式会社 | 半導体集積回路装置 |
US4942358A (en) * | 1988-11-02 | 1990-07-17 | Motorola, Inc. | Integrated circuit option identification circuit and method |
-
1990
- 1990-05-23 KR KR1019900007481A patent/KR920007535B1/ko not_active IP Right Cessation
- 1990-08-14 GB GB9017779A patent/GB2244339B/en not_active Expired - Lifetime
- 1990-08-14 IT IT02127490A patent/IT1242519B/it active IP Right Grant
- 1990-08-17 NL NL9001837A patent/NL194814C/nl not_active IP Right Cessation
- 1990-08-20 FR FR909010474A patent/FR2662505B1/fr not_active Expired - Lifetime
- 1990-08-20 SE SE9002701A patent/SE508000C2/sv not_active IP Right Cessation
- 1990-08-20 DE DE4026326A patent/DE4026326C2/de not_active Expired - Lifetime
- 1990-08-20 JP JP2219871A patent/JPH079753B2/ja not_active Expired - Lifetime
- 1990-08-25 CN CN90107204A patent/CN1025261C/zh not_active Expired - Lifetime
- 1990-09-04 RU SU904830937A patent/RU2034306C1/ru active
- 1990-09-06 US US07/578,284 patent/US5103166A/en not_active Expired - Lifetime
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1996
- 1996-02-01 HK HK21896A patent/HK21896A/xx not_active IP Right Cessation
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- 2000-09-08 JP JP2000272748A patent/JP3343345B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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CN1056770A (zh) | 1991-12-04 |
DE4026326A1 (de) | 1991-11-28 |
NL9001837A (nl) | 1991-12-16 |
RU2034306C1 (ru) | 1995-04-30 |
FR2662505B1 (fr) | 1994-09-09 |
NL194814B (nl) | 2002-11-01 |
KR920007535B1 (ko) | 1992-09-05 |
GB2244339B (en) | 1994-04-27 |
GB2244339A (en) | 1991-11-27 |
KR910020883A (ko) | 1991-12-20 |
NL194814C (nl) | 2003-03-04 |
HK21896A (en) | 1996-02-09 |
GB9017779D0 (en) | 1990-09-26 |
JP2001135796A (ja) | 2001-05-18 |
DE4026326C2 (de) | 1995-07-27 |
JPH079753B2 (ja) | 1995-02-01 |
IT9021274A1 (it) | 1991-11-24 |
IT9021274A0 (it) | 1990-08-14 |
FR2662505A1 (fr) | 1991-11-29 |
IT1242519B (it) | 1994-05-16 |
SE9002701D0 (sv) | 1990-08-20 |
JP3343345B2 (ja) | 2002-11-11 |
SE9002701L (sv) | 1991-11-24 |
SE508000C2 (sv) | 1998-08-10 |
US5103166A (en) | 1992-04-07 |
JPH0428088A (ja) | 1992-01-30 |
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