CN102473649B - 电接触结构及其形成方法 - Google Patents

电接触结构及其形成方法 Download PDF

Info

Publication number
CN102473649B
CN102473649B CN201080035469.9A CN201080035469A CN102473649B CN 102473649 B CN102473649 B CN 102473649B CN 201080035469 A CN201080035469 A CN 201080035469A CN 102473649 B CN102473649 B CN 102473649B
Authority
CN
China
Prior art keywords
conductor wire
spacing
dielectric layer
vertical plane
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201080035469.9A
Other languages
English (en)
Chinese (zh)
Other versions
CN102473649A (zh
Inventor
S·邦萨伦提普
D·C·埃德尔斯坦
W·D·辛斯伯格
H-C·金
S·克斯特
P·M·索罗曼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN102473649A publication Critical patent/CN102473649A/zh
Application granted granted Critical
Publication of CN102473649B publication Critical patent/CN102473649B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN201080035469.9A 2009-08-13 2010-08-04 电接触结构及其形成方法 Active CN102473649B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/540,759 US8247904B2 (en) 2009-08-13 2009-08-13 Interconnection between sublithographic-pitched structures and lithographic-pitched structures
US12/540,759 2009-08-13
PCT/US2010/044326 WO2011019552A1 (en) 2009-08-13 2010-08-04 Interconnection between sublithographic-pitched structures and lithographic-pitched structures

Publications (2)

Publication Number Publication Date
CN102473649A CN102473649A (zh) 2012-05-23
CN102473649B true CN102473649B (zh) 2015-03-18

Family

ID=43586394

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201080035469.9A Active CN102473649B (zh) 2009-08-13 2010-08-04 电接触结构及其形成方法

Country Status (7)

Country Link
US (1) US8247904B2 (https=)
JP (1) JP5559329B2 (https=)
CN (1) CN102473649B (https=)
DE (1) DE112010003269B4 (https=)
GB (1) GB2485493B (https=)
TW (1) TWI527154B (https=)
WO (1) WO2011019552A1 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7405147B2 (en) * 2004-01-30 2008-07-29 International Business Machines Corporation Device and methodology for reducing effective dielectric constant in semiconductor devices
US9105590B2 (en) * 2011-08-10 2015-08-11 United Microelectronics Corp. Semiconductor structure having material layers which are level with each other and manufacturing method thereof
US20130320451A1 (en) * 2012-06-01 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") Semiconductor device having non-orthogonal element
US9581899B2 (en) * 2012-11-27 2017-02-28 International Business Machines Corporation 2-dimensional patterning employing tone inverted graphoepitaxy
US9136168B2 (en) * 2013-06-28 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive line patterning
JP6522662B2 (ja) * 2014-06-13 2019-05-29 インテル・コーポレーション 電子ビームによる一方向の層上金属
US9306164B1 (en) 2015-01-30 2016-04-05 International Business Machines Corporation Electrode pair fabrication using directed self assembly of diblock copolymers
KR102705024B1 (ko) 2016-12-14 2024-09-09 삼성전자주식회사 반도체 장치
US10361158B2 (en) 2017-08-29 2019-07-23 Micron Technology, Inc. Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU610249B2 (en) * 1987-09-29 1991-05-16 Microelectronics And Computer Technology Corporation Customizable circuitry
US5886410A (en) * 1996-06-26 1999-03-23 Intel Corporation Interconnect structure with hard mask and low dielectric constant materials
US6262487B1 (en) * 1998-06-23 2001-07-17 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US6194667B1 (en) * 1998-08-19 2001-02-27 International Business Machines Corporation Receptor pad structure for chip carriers
US6795367B1 (en) * 2000-05-16 2004-09-21 Micron Technology, Inc. Layout technique for address signal lines in decoders including stitched blocks
JP2001352053A (ja) * 2000-06-08 2001-12-21 Nikon Corp 固体撮像装置
US6531357B2 (en) * 2000-08-17 2003-03-11 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
JP3964608B2 (ja) * 2000-08-17 2007-08-22 株式会社東芝 半導体装置
JP2003330385A (ja) * 2002-05-17 2003-11-19 Dainippon Printing Co Ltd 電極パターンおよびその検査方法
JP2004048032A (ja) * 2002-07-12 2004-02-12 Sharp Corp 配線構造、表示装置および能動素子基板
DE10259634B4 (de) * 2002-12-18 2008-02-21 Qimonda Ag Verfahren zur Herstellung von Kontakten auf einem Wafer
JP4498088B2 (ja) * 2004-10-07 2010-07-07 株式会社東芝 半導体記憶装置およびその製造方法
JP2006173186A (ja) * 2004-12-13 2006-06-29 Toshiba Corp 半導体装置、パターンレイアウト作成方法および露光マスク
JP4936659B2 (ja) * 2004-12-27 2012-05-23 株式会社東芝 半導体装置の製造方法
DE602005023597D1 (de) * 2005-07-08 2010-10-28 St Microelectronics Srl Verfahren zur Realisierung einer elektrischen Verbindung in einer elektronischen Halbleitervorrichtung zwischen einem nanometrischen Schaltungsarchitektur und elektronischen Standardkomponenten
US8618221B2 (en) * 2005-10-14 2013-12-31 Wisconsin Alumni Research Foundation Directed assembly of triblock copolymers
JP2007194496A (ja) * 2006-01-20 2007-08-02 Toshiba Corp 半導体集積回路
US20080085600A1 (en) * 2006-10-10 2008-04-10 Toshiharu Furukawa Method of forming lithographic and sub-lithographic dimensioned structures
US7553760B2 (en) * 2006-10-19 2009-06-30 International Business Machines Corporation Sub-lithographic nano interconnect structures, and method for forming same
TWM314988U (en) * 2006-12-29 2007-07-01 Innolux Display Corp Flexible printed circuit board
US7767099B2 (en) * 2007-01-26 2010-08-03 International Business Machines Corporaiton Sub-lithographic interconnect patterning using self-assembling polymers
US7964107B2 (en) * 2007-02-08 2011-06-21 Micron Technology, Inc. Methods using block copolymer self-assembly for sub-lithographic patterning
US8018070B2 (en) * 2007-04-20 2011-09-13 Qimonda Ag Semiconductor device, method for manufacturing semiconductor devices and mask systems used in the manufacturing of semiconductor devices
US20090001045A1 (en) * 2007-06-27 2009-01-01 International Business Machines Corporation Methods of patterning self-assembly nano-structure and forming porous dielectric
US7741721B2 (en) * 2007-07-31 2010-06-22 International Business Machines Corporation Electrical fuses and resistors having sublithographic dimensions
JP2008047904A (ja) * 2007-08-10 2008-02-28 Hitachi Ltd 半導体装置
JP2009042660A (ja) * 2007-08-10 2009-02-26 Renesas Technology Corp 半導体装置、フォトマスク、半導体装置の製造方法およびパターンレイアウト方法
US8043964B2 (en) * 2009-05-20 2011-10-25 Micron Technology, Inc. Method for providing electrical connections to spaced conductive lines

Also Published As

Publication number Publication date
GB2485493A (en) 2012-05-16
US8247904B2 (en) 2012-08-21
CN102473649A (zh) 2012-05-23
GB2485493B (en) 2014-01-15
DE112010003269T5 (de) 2013-04-25
TWI527154B (zh) 2016-03-21
JP5559329B2 (ja) 2014-07-23
WO2011019552A1 (en) 2011-02-17
JP2013502072A (ja) 2013-01-17
GB201200163D0 (en) 2012-02-15
DE112010003269B4 (de) 2014-05-15
US20110037175A1 (en) 2011-02-17
TW201123351A (en) 2011-07-01

Similar Documents

Publication Publication Date Title
CN102473649B (zh) 电接触结构及其形成方法
CN105845622B (zh) 半导体结构及其形成方法
JP5505904B2 (ja) 二次元自己組織化サブリソグラフィ・ナノスケール構造およびこれを製造するための方法（自己組織化材料を用いた二次元パターニング）
CN103839881B (zh) 具有自对准端对端导线结构的半导体器件及其制造方法
KR101331250B1 (ko) 쓰루 콘택을 가지는 반도체 디바이스 및 그 제조 방법
US9305834B1 (en) Methods for fabricating integrated circuits using designs of integrated circuits adapted to directed self-assembly fabrication to form via and contact structures
CN107452673A (zh) 形成用于心轴及非心轴互连线的自对准连续性区块的方法
US20200135547A1 (en) Semiconductor device and method of manufacture
CN103378054A (zh) 具有自对准互连件的半导体器件
CN108511387B (zh) 在电介质层中形成导电路径图案的方法
CN108511338A (zh) 一种在介电层中限定用于导电路径的图案的方法
US20140353762A1 (en) Multi-orientation semiconductor devices employing directed self-assembly
KR20230037438A (ko) 비아를 포함하는 집적 회로 장치 및 그 제조 방법
TWI524375B (zh) 製造半導體裝置之方法
CN112750773A (zh) 生产接触晶体管的栅极和源极/漏极通孔连接的方法
CN114446770B (zh) 半导体结构及其形成方法
KR100866964B1 (ko) 반도체 소자 제조를 위한 상호 연결된 미세 하드마스크패턴 형성 방법
CN111477586A (zh) 形成图案的方法及对集成式组合件的导电结构进行图案化的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20171025

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171025

Address after: American New York

Patentee after: Core USA second LLC

Address before: American New York

Patentee before: International Business Machines Corp.