TWI527154B - 電接觸結構及其形成方法 - Google Patents

電接觸結構及其形成方法 Download PDF

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Publication number
TWI527154B
TWI527154B TW099126312A TW99126312A TWI527154B TW I527154 B TWI527154 B TW I527154B TW 099126312 A TW099126312 A TW 099126312A TW 99126312 A TW99126312 A TW 99126312A TW I527154 B TWI527154 B TW I527154B
Authority
TW
Taiwan
Prior art keywords
wires
pitch
dielectric layer
layer
forming
Prior art date
Application number
TW099126312A
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English (en)
Chinese (zh)
Other versions
TW201123351A (en
Inventor
薩瑞亞 班薩朗提
丹尼爾Ｃ 艾戴斯坦
威廉Ｄ 海斯伯
金浩哲
史帝文 寇斯特
保羅Ｍ 所羅門
Original Assignee
萬國商業機器公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 萬國商業機器公司 filed Critical 萬國商業機器公司
Publication of TW201123351A publication Critical patent/TW201123351A/zh
Application granted granted Critical
Publication of TWI527154B publication Critical patent/TWI527154B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW099126312A 2009-08-13 2010-08-06 電接觸結構及其形成方法 TWI527154B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/540,759 US8247904B2 (en) 2009-08-13 2009-08-13 Interconnection between sublithographic-pitched structures and lithographic-pitched structures

Publications (2)

Publication Number Publication Date
TW201123351A TW201123351A (en) 2011-07-01
TWI527154B true TWI527154B (zh) 2016-03-21

Family

ID=43586394

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099126312A TWI527154B (zh) 2009-08-13 2010-08-06 電接觸結構及其形成方法

Country Status (7)

Country Link
US (1) US8247904B2 (https=)
JP (1) JP5559329B2 (https=)
CN (1) CN102473649B (https=)
DE (1) DE112010003269B4 (https=)
GB (1) GB2485493B (https=)
TW (1) TWI527154B (https=)
WO (1) WO2011019552A1 (https=)

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US7405147B2 (en) * 2004-01-30 2008-07-29 International Business Machines Corporation Device and methodology for reducing effective dielectric constant in semiconductor devices
US9105590B2 (en) * 2011-08-10 2015-08-11 United Microelectronics Corp. Semiconductor structure having material layers which are level with each other and manufacturing method thereof
US20130320451A1 (en) * 2012-06-01 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") Semiconductor device having non-orthogonal element
US9581899B2 (en) * 2012-11-27 2017-02-28 International Business Machines Corporation 2-dimensional patterning employing tone inverted graphoepitaxy
US9136168B2 (en) * 2013-06-28 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive line patterning
JP6522662B2 (ja) * 2014-06-13 2019-05-29 インテル・コーポレーション 電子ビームによる一方向の層上金属
US9306164B1 (en) 2015-01-30 2016-04-05 International Business Machines Corporation Electrode pair fabrication using directed self assembly of diblock copolymers
KR102705024B1 (ko) 2016-12-14 2024-09-09 삼성전자주식회사 반도체 장치
US10361158B2 (en) 2017-08-29 2019-07-23 Micron Technology, Inc. Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch

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US6262487B1 (en) * 1998-06-23 2001-07-17 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US6194667B1 (en) * 1998-08-19 2001-02-27 International Business Machines Corporation Receptor pad structure for chip carriers
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JP2001352053A (ja) * 2000-06-08 2001-12-21 Nikon Corp 固体撮像装置
US6531357B2 (en) * 2000-08-17 2003-03-11 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
JP3964608B2 (ja) * 2000-08-17 2007-08-22 株式会社東芝 半導体装置
JP2003330385A (ja) * 2002-05-17 2003-11-19 Dainippon Printing Co Ltd 電極パターンおよびその検査方法
JP2004048032A (ja) * 2002-07-12 2004-02-12 Sharp Corp 配線構造、表示装置および能動素子基板
DE10259634B4 (de) * 2002-12-18 2008-02-21 Qimonda Ag Verfahren zur Herstellung von Kontakten auf einem Wafer
JP4498088B2 (ja) * 2004-10-07 2010-07-07 株式会社東芝 半導体記憶装置およびその製造方法
JP2006173186A (ja) * 2004-12-13 2006-06-29 Toshiba Corp 半導体装置、パターンレイアウト作成方法および露光マスク
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Also Published As

Publication number Publication date
GB2485493A (en) 2012-05-16
US8247904B2 (en) 2012-08-21
CN102473649A (zh) 2012-05-23
GB2485493B (en) 2014-01-15
DE112010003269T5 (de) 2013-04-25
JP5559329B2 (ja) 2014-07-23
WO2011019552A1 (en) 2011-02-17
JP2013502072A (ja) 2013-01-17
GB201200163D0 (en) 2012-02-15
DE112010003269B4 (de) 2014-05-15
US20110037175A1 (en) 2011-02-17
TW201123351A (en) 2011-07-01
CN102473649B (zh) 2015-03-18

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