GB2485493B - Interconnection between sublithographic-pitched structures and lithographic-pitched structures - Google Patents

Interconnection between sublithographic-pitched structures and lithographic-pitched structures

Info

Publication number
GB2485493B
GB2485493B GB1200163.2A GB201200163A GB2485493B GB 2485493 B GB2485493 B GB 2485493B GB 201200163 A GB201200163 A GB 201200163A GB 2485493 B GB2485493 B GB 2485493B
Authority
GB
United Kingdom
Prior art keywords
sublithographic
lithographic
conductive lines
pitch
pitched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB1200163.2A
Other languages
English (en)
Other versions
GB2485493A (en
GB201200163D0 (en
Inventor
Sarunya Bangsaruntip
Daniel C Edelstein
Ho-Cheol Kim
Steven Koester
Paul M Solomon
William Hinsberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB201200163D0 publication Critical patent/GB201200163D0/en
Publication of GB2485493A publication Critical patent/GB2485493A/en
Application granted granted Critical
Publication of GB2485493B publication Critical patent/GB2485493B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
GB1200163.2A 2009-08-13 2010-08-04 Interconnection between sublithographic-pitched structures and lithographic-pitched structures Expired - Fee Related GB2485493B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/540,759 US8247904B2 (en) 2009-08-13 2009-08-13 Interconnection between sublithographic-pitched structures and lithographic-pitched structures
PCT/US2010/044326 WO2011019552A1 (en) 2009-08-13 2010-08-04 Interconnection between sublithographic-pitched structures and lithographic-pitched structures

Publications (3)

Publication Number Publication Date
GB201200163D0 GB201200163D0 (en) 2012-02-15
GB2485493A GB2485493A (en) 2012-05-16
GB2485493B true GB2485493B (en) 2014-01-15

Family

ID=43586394

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1200163.2A Expired - Fee Related GB2485493B (en) 2009-08-13 2010-08-04 Interconnection between sublithographic-pitched structures and lithographic-pitched structures

Country Status (7)

Country Link
US (1) US8247904B2 (https=)
JP (1) JP5559329B2 (https=)
CN (1) CN102473649B (https=)
DE (1) DE112010003269B4 (https=)
GB (1) GB2485493B (https=)
TW (1) TWI527154B (https=)
WO (1) WO2011019552A1 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7405147B2 (en) * 2004-01-30 2008-07-29 International Business Machines Corporation Device and methodology for reducing effective dielectric constant in semiconductor devices
US9105590B2 (en) * 2011-08-10 2015-08-11 United Microelectronics Corp. Semiconductor structure having material layers which are level with each other and manufacturing method thereof
US20130320451A1 (en) * 2012-06-01 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") Semiconductor device having non-orthogonal element
US9581899B2 (en) * 2012-11-27 2017-02-28 International Business Machines Corporation 2-dimensional patterning employing tone inverted graphoepitaxy
US9136168B2 (en) * 2013-06-28 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive line patterning
JP6522662B2 (ja) * 2014-06-13 2019-05-29 インテル・コーポレーション 電子ビームによる一方向の層上金属
US9306164B1 (en) 2015-01-30 2016-04-05 International Business Machines Corporation Electrode pair fabrication using directed self assembly of diblock copolymers
KR102705024B1 (ko) 2016-12-14 2024-09-09 삼성전자주식회사 반도체 장치
US10361158B2 (en) 2017-08-29 2019-07-23 Micron Technology, Inc. Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch

Citations (11)

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US5132878A (en) * 1987-09-29 1992-07-21 Microelectronics And Computer Technology Corporation Customizable circuitry
US6027995A (en) * 1996-06-26 2000-02-22 Intel Corporation Method for fabricating an interconnect structure with hard mask and low dielectric constant materials
US6194667B1 (en) * 1998-08-19 2001-02-27 International Business Machines Corporation Receptor pad structure for chip carriers
US6645842B2 (en) * 1998-06-23 2003-11-11 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US20040184341A1 (en) * 2000-05-16 2004-09-23 Tsai Richard H. Layout technique for address signal lines in decoders including stitched blocks
US20060276019A1 (en) * 2002-12-18 2006-12-07 Werner Graf Method for production of contacts on a wafer
US20070038966A1 (en) * 2005-07-08 2007-02-15 Stmicroelectronics S.R.I. Method for realizing an electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components
US20080182402A1 (en) * 2007-01-26 2008-07-31 International Business Machines Corporation Sub-lithographic interconnect patterning using self-assembling polymers
US20080193658A1 (en) * 2007-02-08 2008-08-14 Micron Technology, Inc. Methods using block copolymer self-assembly for sub-lithographic patterning
US7429177B2 (en) * 2006-12-29 2008-09-30 Innocom Technology (Shenzhen) Co., Ltd. Flexible printed circuit board with contoured conductive lines
US20090087664A1 (en) * 2005-10-14 2009-04-02 Wisconsin Alumni Research Foundation Directed assembly of triblock copolymers

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JP2001352053A (ja) * 2000-06-08 2001-12-21 Nikon Corp 固体撮像装置
US6531357B2 (en) * 2000-08-17 2003-03-11 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
JP3964608B2 (ja) * 2000-08-17 2007-08-22 株式会社東芝 半導体装置
JP2003330385A (ja) * 2002-05-17 2003-11-19 Dainippon Printing Co Ltd 電極パターンおよびその検査方法
JP2004048032A (ja) * 2002-07-12 2004-02-12 Sharp Corp 配線構造、表示装置および能動素子基板
JP4498088B2 (ja) * 2004-10-07 2010-07-07 株式会社東芝 半導体記憶装置およびその製造方法
JP2006173186A (ja) * 2004-12-13 2006-06-29 Toshiba Corp 半導体装置、パターンレイアウト作成方法および露光マスク
JP4936659B2 (ja) * 2004-12-27 2012-05-23 株式会社東芝 半導体装置の製造方法
JP2007194496A (ja) * 2006-01-20 2007-08-02 Toshiba Corp 半導体集積回路
US20080085600A1 (en) * 2006-10-10 2008-04-10 Toshiharu Furukawa Method of forming lithographic and sub-lithographic dimensioned structures
US7553760B2 (en) * 2006-10-19 2009-06-30 International Business Machines Corporation Sub-lithographic nano interconnect structures, and method for forming same
US8018070B2 (en) * 2007-04-20 2011-09-13 Qimonda Ag Semiconductor device, method for manufacturing semiconductor devices and mask systems used in the manufacturing of semiconductor devices
US20090001045A1 (en) * 2007-06-27 2009-01-01 International Business Machines Corporation Methods of patterning self-assembly nano-structure and forming porous dielectric
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Publication number Priority date Publication date Assignee Title
US5132878A (en) * 1987-09-29 1992-07-21 Microelectronics And Computer Technology Corporation Customizable circuitry
US6027995A (en) * 1996-06-26 2000-02-22 Intel Corporation Method for fabricating an interconnect structure with hard mask and low dielectric constant materials
US6645842B2 (en) * 1998-06-23 2003-11-11 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US6194667B1 (en) * 1998-08-19 2001-02-27 International Business Machines Corporation Receptor pad structure for chip carriers
US20040184341A1 (en) * 2000-05-16 2004-09-23 Tsai Richard H. Layout technique for address signal lines in decoders including stitched blocks
US20060276019A1 (en) * 2002-12-18 2006-12-07 Werner Graf Method for production of contacts on a wafer
US20070038966A1 (en) * 2005-07-08 2007-02-15 Stmicroelectronics S.R.I. Method for realizing an electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components
US20090087664A1 (en) * 2005-10-14 2009-04-02 Wisconsin Alumni Research Foundation Directed assembly of triblock copolymers
US7429177B2 (en) * 2006-12-29 2008-09-30 Innocom Technology (Shenzhen) Co., Ltd. Flexible printed circuit board with contoured conductive lines
US20080182402A1 (en) * 2007-01-26 2008-07-31 International Business Machines Corporation Sub-lithographic interconnect patterning using self-assembling polymers
US20080193658A1 (en) * 2007-02-08 2008-08-14 Micron Technology, Inc. Methods using block copolymer self-assembly for sub-lithographic patterning

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATIL et al, Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits, 8 June 2007; retrieved from internet: , Figs 1.1, 1.2 *

Also Published As

Publication number Publication date
GB2485493A (en) 2012-05-16
US8247904B2 (en) 2012-08-21
CN102473649A (zh) 2012-05-23
DE112010003269T5 (de) 2013-04-25
TWI527154B (zh) 2016-03-21
JP5559329B2 (ja) 2014-07-23
WO2011019552A1 (en) 2011-02-17
JP2013502072A (ja) 2013-01-17
GB201200163D0 (en) 2012-02-15
DE112010003269B4 (de) 2014-05-15
US20110037175A1 (en) 2011-02-17
TW201123351A (en) 2011-07-01
CN102473649B (zh) 2015-03-18

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Legal Events

Date Code Title Description
746 Register noted 'licences of right' (sect. 46/1977)

Effective date: 20140127

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20160804