CN102460670A - 半导体器件、半导体器件制造方法和使用半导体器件的电路器件 - Google Patents

半导体器件、半导体器件制造方法和使用半导体器件的电路器件 Download PDF

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CN102460670A
CN102460670A CN2010800284431A CN201080028443A CN102460670A CN 102460670 A CN102460670 A CN 102460670A CN 2010800284431 A CN2010800284431 A CN 2010800284431A CN 201080028443 A CN201080028443 A CN 201080028443A CN 102460670 A CN102460670 A CN 102460670A
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semiconductor device
bonding
main material
ledge
electrode
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难波兼二
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NEC Corp
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NEC Corp
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Abstract

公开一种尤其在倒装法装配中实现细节距、高产量和高连接可靠性的半导体器件。也提供一种用于制造该半导体器件的方法和使用该半导体器件的电路器件。该半导体器件具有：电极；绝缘部分，在电极上具有开口；突出部分，形成于电极上；保护部分，形成于突出部分的周界并且电隔离突出部分；以及键合部分，通过与突出部分间隔开来形成于保护部分上。突出部分的上表面、保护部分的上表面和键合部分的上表面形成相同平面。

Description

半导体器件、半导体器件制造方法和使用半导体器件的电路器件
技术领域
本发明涉及一种半导体器件和用于制造该半导体器件的方法。具体而言，本发明涉及一种在倒装法装配中实现细节距、高产量和高连接可靠性的半导体器件、用于制造该半导体器件的方法和使用该半导体器件的电路器件。
背景技术
近年来公知SiP(封装中的系统)结构作为适合于半导体器件优良性能和复杂功能的封装结构。根据SiP结构，通过层叠诸如CPU(中央处理单元)、存储器等多个半导体元件并且通过在封装上装配层叠的半导体元件来构建系统。另外根据SiP结构，近年来已经发展使管脚进一步增加、并且使电极之间的节距更细以便提高在半导体元件之间传送数据的能力。
图9A和图9B示出了根据相关技术的用于制造半导体器件的方法的示例。
首先布置两个半导体器件1101为彼此相对。对于每个半导体器件1101，主要构成为锡(Sn)的焊块15通过阻挡金属14形成于半导体元件1的电极2上。或者由金(Au)制成的薄膜可以形成于半导体元件1之一的阻挡金属14上(图9A)。此后，存在于对应位置的焊块15相互接触、然后被加热和压印。因而焊块起反应并且相互连接。最终具有热硬化性质的底部填充树脂填充于两个半导体元件1之间。底部填充树脂在硬化工艺中变成键合树脂层7。通过执行上述工艺来获得电路器件1201(图9B)。
为了提高产率，公开号为2007-142232的日本待审专利申请(专利文献1)公开一种用于使得液体树脂在衬底侧上流动之后装配半导体元件、以及继而将电极相互连接并且针对树脂执行热硬化工艺的制造方法。
公开号为2005-294430的日本待审专利申请(专利文献2)公开一种用于在装配半导体元件之前供应树脂的制造方法。具体而言，专利文献2公开一种用于在半导体元件侧上形成处于半硬状态的键合树脂层，并且通过研磨焊块和随后研磨键合树脂层使焊块的表面从键合树脂层暴露并且使半导体元件的表面平坦的制造方法。
公开号为2004-172491的日本待审专利申请(专利文献3)公开如下结构，其中使突出电极的表面和和停止物掩模层齐平。此外，专利文献3公开了将具有粘合性质的热塑树脂或低变软点(熔点)玻璃应用至停止物掩模层。
[相关技术文献]
[专利文献]
[专利文献1]公开号为2007-142232的日本待审专利申请
[专利文献2]公开号为2005-294430的日本待审专利申请
[专利文献3]公开号为2004-172491的日本待审专利申请
发明内容
[本发明将要解决的问题]
然而根据相关技术的结构具有若干问题。
第一问题在于往往由于底部填充树脂的填充性质下降而出现空隙。空隙之所以出现是因为由于越来越多的管脚和在电极之间的细节距使得在凸块之间的距离变短并且凸块的高度变低，而且在半导体元件之间的间隙变窄。在半导体元件之间的间隙窄的情况下，进入填充区域的填充速度与半导体元件边缘周围的流动速度之差变得明显。因而由于包含空气而出现空隙。另外，在填充区域中，在凸块布置区域中和在其它区域中填充底部填充树脂的速度也互不相同。因而空隙往往出现于凸块连接区域中。
第二问题在于组装封装的产率低。原因在于单独执行用于装配半导体元件的工艺和用于填充底部填充树脂的工艺。另外，产率变低，因为通过调节诸如底部填充树脂的粘度、涂敷量等条件来影响填充时间并且单独执行每个底部填充工艺。
根据在专利文献1中描述的制造方法，当装配半导体元件时容易在半导体元件与树脂之间包含空气。因而空隙往往出现于树脂内。在细节距和窄间隙的情况下难以排放在树脂热硬化工艺之前由使用树脂的流动而包含的空气。另一问题在于由于在包括电极的衬底上预先涂敷树脂，所以树脂穿插于接合部分之间、并因而电极的连接区域变小。
根据在专利文献2中描述的制造方法，担心在刮擦时在焊块上生成刮擦的下陷，因为处于半硬状态的键合树脂层和由金属制成的焊块在硬度上互不相同。因而在电极之间的节距变细的情况下有刮擦的下陷引起与相邻凸块的短路这样的可能性。另外由于电极的尺寸根据精炼也变细，所以另一问题在于由于在形成凸块时的板变化所致的影响变得明显。
尽管专利文献3描述了向停止物掩模层施加具有粘合性质的热塑树脂或者低软化点(熔点)玻璃，但是专利文献3未考虑在电极之间的绝缘性。有必要将电极之间的绝缘性与在电极之间的粘合性一起考虑以便使突出电极之间的节距变细。
本发明的目的在于提供一种解决上述问题的半导体器件、用于制造该半导体器件的方法和使用该半导体器件的电路器件。
用于解决问题的措施
作为第一观点，根据本发明的一种具有电极的半导体器件包括：绝缘部分，在电极上具有开口；突出部分，形成于电极上；保护部分，形成于突出部分的周界并且电隔离突出部分；以及键合部分，形成于保护部分上与突出部分间隔开。突出部分的上表面、保护部分的上表面和键合部分的上表面形成相同平面。
在此，每个元件或者每个构件的上表面意味着存在于每个元件或者每个部件的顶端上并且向外界暴露的表面。
作为第二观点，根据本发明的一种用于制造半导体器件的方法包括：在具有电极的半导体元件上形成绝缘部分的步骤，绝缘部分在电极上具有开口；在电极上形成突出部分的主要材料部分的步骤；在绝缘部分和主要材料部分上形成保护部分的步骤；在保护部分上供应键合部分的材料的步骤；以及执行平坦化工艺使得主要材料部分的表面、在主要材料部分的周界中的保护部分的表面和键合部分的表面形成相同平面的步骤。
作为第三观点，根据本发明的一种用于制造半导体器件的方法包括：在具有电极的半导体元件上形成绝缘部分的步骤，绝缘部分在电极上具有开口；在电极上形成突出部分的主要材料部分的步骤；在绝缘部分和主要材料部分上形成保护部分的步骤；执行平坦化工艺使得主要材料部分的表面和在主要材料部分的周界中的保护部分的表面形成相同平面的步骤；去除形成于划片线上的保护部分的步骤；供应键合部分的材料的步骤；以及通过使用掩模对键合部分成形的步骤。
作为第四观点，根据本发明的一种电路器件包括具有电极的半导体器件。半导体器件包括：绝缘部分，在电极上具有开口；突出部分，形成于电极上；保护部分，形成于突出部分的周界并且电隔离突出部分；以及键合部分，形成于保护部分上与突出部分间隔开。突出部分的上表面、保护部分的上表面和键合部分的上表面形成相同平面。
本发明的效果
根据该半导体器件，尤其在倒装法装配中有可能一起实现高连接可靠性、细节距和高产量。
附图说明
图1是示出了根据本发明第一实施例的半导体器件的结构示例的示意横截面图。
图2是示出了根据本发明第二实施例的半导体器件的结构示例的示意横截面图。
图3是示出了用于制造根据本发明第一和第二示例性实施例的半导体器件的方法示例的示意横截面图。
图4是示出了用于制造根据本发明第一示例性实施例的半导体器件的方法示例的示意横截面图。
图5是示出了用于制造根据本发明第二示例性实施例的半导体器件的方法示例的示意横截面图。
图6是示出了用于制造根据本发明第三示例性实施例的半导体器件的方法示例的示意横截面图。
图7是示出了用于制造根据本发明第四示例性实施例的半导体器件的方法示例的示意横截面图。
图8是示出了根据本发明第一示例性实施例的电路器件示例的示意横截面图。
图9是示出了根据相关技术的半导体器件的接合结构和接合方法的示意横截面图。
具体实施方式
下文将参照附图描述更多具体示例性实施例。
[第一示例性实施例]
[半导体器件]
将参照图1具体描述根据本发明的示例性实施例1的半导体器件。图1示出了根据本发明的示例性实施例1的半导体器件101的横截面示例。这里，图1A和图1B为如下横截面图，这些横截面图示出了用划片方法(后文称为制造方法)切割和分离的两种共同制造的半导体器件的横截面。
根据每幅图1A和图1B，电极2和在电极2上具有开口的比如氮氧化硅(SiON)或者氧化硅(SiO2)的绝缘膜3(绝缘部分)布置于半导体器件1的电路平面上，由铜(Cu)制成的凸块10(突出部分)的主要材料部分8布置于电极2上，膜状的并且由比如Sn或者Au制成的接合材料部分9形成于凸块10的主要材料部分8的表面上。另外，绝缘膜3和凸块10的周界由具有高绝缘性质的保护膜6(保护部分)覆盖。这里向保护膜6施加有机树脂(比如聚酰亚胺)或者与绝缘膜3类似地由SiON、SiO等制成的无机膜。
这里，粘合层4和键合层5形成于电极2(包括绝缘膜3的部分)与凸块10的主要材料部分8之间。
另外，处于半硬状态的键合树脂层7(键合部分)布置于除了凸块10的周界之外的保护膜6上。接合材料部分9的表面、在凸块10的周界处的保护膜6的表面和键合树脂层7的表面形成相同平面。键合树脂层7包括热硬化树脂、热塑树脂或者热硬化和光敏性的组合型树脂。
根据本示例性实施例的半导体器件，由于键合树脂层形成于半导体器件的表面的部分上，所以不必向接合部分执行底部填充树脂填充工艺。因而有可能实现高产率。另外由于凸块的接合材料部分的表面从键合树脂层暴露并且接合材料部分的表面和键合树脂层的表面形成相同平面，所以可以抑制由于在装配部件时穿插树脂所致的不良接合。另外由于凸块的周界由具有高绝缘性质的保护膜覆盖，所以可以针对具有细节距的电极保证在相邻凸块之间的高绝缘性。
[用于制造半导体器件的方法]
将参照图3和图4描述用于制造根据本发明第一示例性实施例的半导体器件的方法。图3A示出了包括多个半导体器件的半导体元件1装配于晶片的表面上的状态。由铝(Al)等制成的电极2、在电极2的部分上具有开口并且覆盖电路平面的由SiON、SiO2等制成的绝缘膜3设置于半导体器件的电路平面上。这里，在根据本示例性实施例的制造方法的最终工艺中沿着划片线11(在图中的纵向方向上)切割半导体元件1，因而制造多个半导体器件。
接着在电极2和绝缘膜3的全部表面上用溅射方法等形成由钛(Ti)、钛钨合金(TiW)等制成的粘合层4。继而通过旋涂等在键合层5上供应光敏抗蚀剂12，并且进一步对抗蚀剂12曝光和显影，由此在电极2上的预期区域中形成开口。另外，根据电解电镀方法等在抗蚀剂12的开口上提取Cu(Cu将为凸块10的主要材料部分8)，并且获得图3B中所示结构。这时，电极2上的主要材料部分8的高度可以在电极2之间变化。
此后去除抗蚀剂12并且用湿蚀刻方法等去除在除了由主要材料部分8覆盖的区域之外的区域中形成的粘合层4和键合层5，因而获得图3C中所示结构。
接着通过旋涂等在半导体元件1的的整个表面(包括主要材料部分8的表面)上供应有机树脂(比如热硬化型或者光敏型聚酰亚胺)。通过针对有机树脂执行硬化工艺来形成保护膜6(图3D)。待供应的树脂的量优选为如下量，该量使得接触绝缘膜3的形成的保护膜6的厚度不多于针对其执行最终工艺的凸块10(主要材料部分8和接合材料部分9)的高度的一半。在向保护膜6施加SiON或者SiO2的情况下，用溅射方法供应树脂。在这一情况下希望保护膜6的厚度不多于1微米。
此后在保护膜6上供应变成键合树脂层7的树脂(图4E)。在向键合树脂层7施加热硬化树脂或者热塑树脂的情况下，膜状的树脂层叠于保护膜6上。这里，在施加热硬化树脂的情况下，树脂在层叠之后仍然处于半硬状态。
作为用于供应键合树脂层7的方法，可以采用一种通过旋涂等在保护膜6上供应液体型热硬化树脂并且加热树脂来形成处于半硬状态的键合树脂层7的方法。另外，在向键合树脂层7施加热硬化和光敏树脂的情况下，可以采用一种通过旋涂等供应树脂并且对树脂曝光来形成处于半硬状态的键合树脂层7的方法。
接着用抛光方法、研磨方法、化学机械抛光方法等针对键合树脂层7、保护膜6和凸块10的主要材料部分8执行平坦化工艺(图4F)。另外，用无电镀覆方法等在主要材料部分8的暴露表面上供应将成为薄膜状接合材料部分9的金属(图4G)。这里在采用无电镀覆方法的情况下，可以通过使用浸镀浴来供应具有预期镀覆厚度的接合材料部分9。另外可以优选的是可以向接合材料部分9施加Au或者Sn。
最终通过沿着划片线11执行划片工艺将晶片切割成多件。通过执行划片工艺来生产根据本发明的示例性实施例1的半导体器件101(图4H)。另外可以用抛光方法等加工半导体元件1的背表面使得晶片可以具有预期厚度，此后执行划片工艺。
根据本发明示例性实施例的制造方法，有可能通过在晶片上一起供应键合树脂层来实现高产率。另外通过在凸块的主要材料部分的周界由已经变硬的保护膜覆盖的状态中执行用于平坦化凸块的工艺，可以抑制凸块在加工时下陷，并且甚至在细电极节距的情况下防止相邻凸块之间的短路。另外通过在用于平坦化凸块的工艺之后形成薄接合材料部分，有可能阻止镀覆厚度变化，并且可以获得具有高接合可靠性的凸块形状。另外通过在供应接合材料部分时使用浸镀浴来应用无电镀覆方法，有可能供应接合材料部分而又保持与键合树脂层平齐。
[电路器件]
接着将参照图8具体描述如下电路器件，该电路器件使用根据本发明示例性实施例的半导体器件。首先调节根据本发明示例性实施例的半导体器件101的位置和半导体器件102的位置(凸块的主要材料部分8的表面和保护膜6的表面形成相同平面)(图8A)。此后通过使半导体器件101的接合材料部分9和半导体102的凸块的主要材料部分8相互接触并且通过加热和加压使接合材料部分9和两个主要材料部分的金属起反应并且接合在一起来产生电路器件201(图8B)。这时通过也加热和热硬化键合树脂层7来完成在半导体器件之间的所有边界之上的键合。
根据本发明的示例性实施例1的电路器件，通过预先形成键合树脂层，当装配部件时同时执行电连接电极、向接合部分中填充树脂以及硬化树脂。因而有可能实现高产率。另外通过装配表面平坦的构件，即使电极节距细并且间隙窄，仍然可以抑制由于在装配部件时包含空气而在树脂内出现空隙。
尽管在示例性实施例中示出了与半导体器件有关的结构，但是本发明不限于此。也就是说，本示例性实施例可以涉及接合半导体器件与衬底或者将衬底接合在一起。另外根据本发明，电路器件可以包括相互接合的半导体器件101。另外，电路器件可以包括如下结构，在该结构中，接合部分和另一部分形成如下相同平面，根据本发明的半导体器件的结构连接到该平面。在这一情况下获得相似效果。另外可以向两个半导体器件供应接合材料部分。
[第二示例性实施例]
接着将参照图2描述第二示例性实施例。图2是根据示例性实施例2的半导体器件103的横截面图。如图2中所示，根据本示例性实施例的半导体器件103与根据第一示例性实施例的半导体器件101不同点在于保护膜6的一侧表面(半导体器件的侧表面)由键合树脂层7覆盖。这里，图2中的图2A和图2B示出了两种半导体器件103的横截面图。
根据本示例性实施例，由于保护膜的侧表面(半导体器件的侧表面)由键合树脂层覆盖，所以键合树脂层7放松在半导体器件103上装配部件之后由外力和热膨胀差生成的内部应力。因而作为一个起点，在保护膜6的侧表面抑制表面脱落。
[制造方法]
接着将参照图3和图5描述用于制造根据本示例性实施例的半导体器件的方法。
根据本示例性实施例，由于直至供应保护膜6的工艺与在根据第一示例性实施例的制造方法相同(从图3A至图3D)，所以将省略对这些工艺的描述。
接着沿着从晶片切割成件的部分的划片线11用激光方法等去除保护膜6(图5E)。在向保护膜6施加有机树脂(比如光敏聚酰亚胺)的情况下，可以执行曝光和显影使得当硬化树脂时可以在划片线11上形成开口。此后供应变成键合树脂层7的树脂(图5F)。在向键合树脂层7施加热硬化树脂或者热塑树脂的情况下，膜状的树脂可以层叠于保护膜6上。这里，在施加热硬化树脂的情况下，树脂在层叠之后处于半硬状态。
作为用于供应键合树脂层7的方法，可以采用一种通过旋涂等在保护膜6上供应液体型热硬化树脂并且加热树脂来形成处于半硬状态的键合树脂层7的方法。另外，在向键合树脂层7施加热硬化和光敏树脂的情况下，可以采用一种通过旋涂等供应树脂并且对树脂曝光来形成处于半硬状态的键合树脂层7的方法。
接着通过使用抛光方法、研磨方法、化学机械抛光方法等针对键合树脂层7、保护膜6和凸块10的主要材料部分8执行平坦化工艺(图5G)。另外，用无电镀覆方法等在主要材料部分8的暴露表面上供应将成为薄膜状接合材料部分9的金属(图5H)。这里在采用无电镀覆方法的情况下，可以通过使用浸镀浴来供应具有预期镀覆厚度的接合材料部分9。另外可以向接合材料部分9施加Au、Sn或者其合金。
最终通过沿着划片线11的划片工艺将晶片切割成多件。通过划片工艺生产根据本发明第二示例性实施例的半导体器件103(图5I)。另外可以用抛光方法等加工半导体元件1的背表面使得晶片可以具有预期厚度，此后执行划片工艺。
根据本示例性实施例的制造方法，通过在沿着划片线的保护膜已被预先去除的状态中执行划片工艺来防止可能在划片工艺中出现的保护膜脱落。
[第三示例性实施例]
接着将参照图3和图6描述制造根据第三示例性实施例的半导体器件的方法。
如图3和图6中所示，用于制造根据本示例性实施例的半导体器件104的方法与用于制造根据第一示例性实施例或者第二示例性实施例的半导体器件的方法不同点在于执行用于平坦化凸块10的主要材料部分8的工艺并且在供应变成键合树脂层7的树脂之前形成接合材料部分10。
下文将具体描述本示例性实施例。根据本示例性实施例，由于直至供应保护膜6的工艺与在第一或者第二示例性实施例中相同(图3A至图3D)，所以将省略对这些工艺的描述。
接着用抛光方法、研磨方法、化学机械抛光方法等针对保护膜6和凸块10的主要材料部分8执行平坦化工艺(图6E)。另外用无电镀覆方法等在从保护膜6暴露的主要材料部分8的表面上供应将成为薄膜状接合材料部分9的金属(图6F)。这里，在采用无电镀覆方法的情况下，可以通过使用浸镀浴来供应具有预期镀覆厚度的接合材料部分9。另外可以向接合材料部分9施加Au、Sn或者其合金。
此后在从晶片切割成件的部分的划片线11上，用激光方法等去除保护膜6(图6G)。在向保护膜6施加有机树脂(比如光敏聚酰亚胺)的情况下，可以执行曝光和显影使得当硬化树脂时可以在划片线11上形成开口。
接着供应变成键合树脂层7的树脂(图6H)。例如在向键合树脂层7施加热硬化树脂或者热塑树脂的情况下，膜状的树脂优选地层叠于保护膜6上。这里在施加热硬化树脂的情况下，树脂在层叠之后也仍然处于半硬状态。
作为用于供应键合树脂层7的方法，可以采用一种通过旋涂等在保护膜6上供应液体型热硬化树脂或者液体型热硬化和光敏树脂的方法。
此后用具有平坦形状的掩模13通过压印来对变成键合树脂层7的树脂成形。在对树脂成形之后，去除留在接合材料部分9的表面上的键合树脂残留物，并且用干蚀刻方法暴露接合材料部分9(图6I)。这里在向键合树脂层7施加热硬化树脂或者热塑树脂的情况下，优选地通过用掩模13压印并且在加热树脂之时成形来形成键合树脂层7。另外，在使用热硬化树脂的情况下，优选地随温度和时间执行成形使得热硬化树脂在成形之后也将半硬。另外，在施加热硬化和光敏树脂的情况下，例如用由玻璃等制成的掩模13借助压印来曝光树脂。
最终通过沿着划片线11执行划片工艺将晶片切割成多件。通过执行划片工艺来生产根据本发明第三示例性实施例的半导体器件104(图6J)。另外可以用抛光方法等加工半导体元件1的背表面使得晶片可以具有预期厚度，并且此后执行划片工艺。
根据本示例性实施例的制造方法，在供应变成键合树脂层7的树脂之后执行用于平坦化凸块10的主要材料部分8的工艺，并且形成接合材料部分10。因而可以防止在用无电镀覆方法等形成键合材料部分时镀覆溶剂对键合树脂层的树脂物理性质的影响。
[第四示例性实施例]
接着将参照图3和图7描述用于制造根据第四示例性实施例的半导体器件的方法。
如图3和图7中所示，用于制造根据本示例性实施例的半导体器件105的方法与用于制造根据第一、第二或者第三示例性实施例的半导体器件的方法不同点在于当对键合树脂层7成形时去除沿着划片线11的键合树脂层7。
下文将具体描述本示例性实施例。根据本示例性实施例，由于直至供应变成键合树脂层7的树脂的工艺与在根据第三示例性实施例的制造方法中相同(图3A至图3D和图7E至图7H)，所以将省略对这些工艺的描述。
接着在划片线11上的部分上压印具有突起的掩模13，并且对变成键合树脂层7的树脂成形。在对树脂成形之后，用干蚀刻方法等去除在接合材料部分9的表面上和在与划片线11接近的位置余留的键合树脂残留物，继而曝光接合材料部分9和划片线(图7I)。这里在向键合树脂层7施加热硬化树脂或者热塑树脂的情况下，通过用掩模13压印并且在加热树脂之时成形来形成键合树脂层7。另外，在使用热硬化树脂的情况下，优选地随温度和时间执行成形使得热硬化树脂在成形之后将半硬。同时，在施加热硬化和光敏树脂的情况下，在例如用具有相似形状的由玻璃等制成的掩模13压印之时曝光树脂。
另外，在施加热硬化和光敏树脂的情况下，可以在用具有平坦形状的掩模13压印树脂之时执行曝光和显影使得可以打开划片线部分11。
最终通过沿着划片线11执行划片工艺将晶片切割成多件。通过执行划片工艺来生产根据本发明第四示例性实施例的半导体器件105(图7J)。另外可以用抛光方法等加工半导体元件1的背表面使得晶片可以具有预期厚度，并且此后执行划片工艺。
根据本示例性实施例的制造方法，在对键合树脂层7成形时，通过去除在划片线的部分上供应的键合树脂层，有可能防止在划片工艺中将晶片切割成多件的时候树脂阻碍划片刀片。因而可以防止在划片工艺中出现的半导体元件碎片或者裂缝出现并且提高可靠性。
[示例]
接下来将参照图3和图4描述根据本发明的用于制造半导体器件的方法的示例。
首先，半导体元件1例如具有直径为8英寸而厚度为725微米的晶片形状，并且例如在电路平面上包括布置于20微米的节距区域阵列中的、由Al制成的电极2，以及在电极2的部分上具有开口并且覆盖电路平面的、由SiON制成的绝缘膜3(图3A)。
接下来，用溅射方法在电极2和绝缘膜3的全部表面上形成由Ti制成的粘合层4和由Cu制成的键合层5。然后通过旋涂在键合层5上供应光敏抗蚀剂12，此后执行曝光和显影。因而在电极2上形成直径例如为10微米的开口。另外，用无电镀覆方法在抗蚀剂12的开口上提取将成为主要材料部分8的Cu。提取的Cu的高度例如不低于10微米(图3B)。这时，主要材料部分8的高度在电极2之间变化。
此后去除抗蚀剂12，并且更进一步利用湿蚀刻方法去除除了在主要材料部分8之下形成的粘合层4和键合层5之外的粘合层4和键合层5(图3C)。接着在整个表面(包括主要材料部分8的表面)上从上侧供应变成保护膜6的聚酰亚胺有机树脂，此后热硬化树脂(图3D)。供应恰当量的聚酰亚胺树脂使得绝缘膜3上的已经成形的保护膜6的厚度例如为3微米。此后用85摄氏度的加热温度和0.5兆帕(MPa)的真空压强借助真空层叠方法在保护膜6上供应变成键合树脂层7，并且例如30微米厚的膜状热硬化树脂(图4E)。树脂在层叠之后也仍然处于半硬状态。
接下来用研磨方法针对键合树脂层7、保护膜6和主要材料部分8执行平坦化工艺(图4F)。主要材料部分8的高度在平坦化工艺之后为8微米。另外，通过使用Au浸镀浴借助无电镀覆方法在主要材料部分8的暴露表面上形成薄膜状的、由Au制成的接合材料部分9(图4G)。薄膜状Au例如为0.03微米厚。最终用抛光方法抛光半导体元件1的背表面以变薄，从而使得厚度变成120微米，并且执行划片工艺以将晶片划片成尺寸为8平方毫米的多个矩形。结果，获得根据本发明示例的半导体器件(图4H)。
[电路器件]
接下来将参照图8描述用于制造根据本发明的电路器件的方法的示例。
如图8中所示，调节根据本发明的本示例性实施例的半导体器件101的位置和半导体器件102的位置(直径为13微米的由Cu制成的主要材料部分8的表面和由聚酰亚胺制成的保护膜6的表面形成相同平面)(图8A)。此后使半导体器件101中的由Au制成的接合材料部分9和半导体器件102中的主要材料部分8相互接触，并且在300摄氏度的温度加热，而且用每个芯片75牛顿的装配负荷同时按压15秒，然后两个半导体器件的接合材料部分9和主要材料部分8起反应并且接合在一起(图8B)。这时，通过热硬化在不低于150摄氏度的温度开始反应的键合树脂层7来完成用于将半导体器件键合在一起的工艺。
在第一观点中，凸块优选地包括主要材料部分和接合材料部分这两层。
主要材料部分优选地由Cu制成。另外，凸块的接合材料部分优选为Au和Sn中的任一种。
半导体器件的至少一侧表面优选地由键合树脂层覆盖以免暴露保护膜。
保护膜优选地具有在两个相邻凸块之间的中心凹入的弓形形状。
可以向保护膜施加由聚酰亚胺制成的有机膜。保护膜可以是无机膜。
保护膜的厚度优选地在凸块之间的位置处不多于凸块的高度的一半。
键合树脂层优选地由处于半硬状态的热硬化树脂、热硬化和光敏树脂以及热塑树脂中的至少一种制成。
在第二观点中，优选还包括在用于在半导体元件的绝缘层上和在凸块的主要材料部分上形成保护膜的工艺，以及用于在保护膜上供应变成键合树脂层的材料的工艺之间用于去除在划片线上的保护膜的工艺。
优选还包括用于在凸块的主要材料部分的表面上形成接合材料部分的工艺。
在第三观点中，优选还包括用于在凸块的主要材料部分的表面上形成接合材料部分的工艺。
另外，优选地通过使用浸镀浴借助无电镀覆方法执行用于在凸块的主要材料部分的表面上形成接合材料部分的工艺。
用于供应变成键合树脂层的材料的工艺优选为用于用层叠方法供应膜状半硬树脂的工艺。
用于供应变成键合树脂层的材料的工艺优选为用于通过旋涂供应液体树脂、并且此后通过加热或者曝光来使液体树脂半硬的工艺。
优选地用抛光方法、研磨方法和化学机械抛光方法中的至少一种方法执行用于平坦化凸块的主要材料部分的表面和在凸块的主要材料部分附近的保护膜(包括键合树脂层)的表面以使表面形成相同平面的工艺。
优选地用激光方法和光刻方法中的任一方法执行用于去除在划片线上的保护膜的工艺。
优选地通过用在划片线上用具有突起的掩模压印树脂并且对树脂成形来执行用于通过使用掩模对变成键合树脂层的树脂成形的工艺。
优选地通过使用具有平坦形状的掩模借助光刻方法来执行用于通过使用掩模对变成键合树脂层的树脂成形的工艺。
尽管已经参照本发明的示例性实施例及其示例具体示出和描述本发明，但是本发明并不限于示例性实施例和示例。有可能在形式和细节上作出本领域普通技术人员可以理解的各种改变而不脱离本发明的精神实质和范围。
本申请基于并要求2009年6月24日提交的第2009-149945号日本专利申请的优先权，其公开内容通过引用整体结合于此。
工业实用性
本发明可以应用于一种实现细节距和高产量的半导体器件和一种使用该半导体器件的电路器件
参考标号列表
1半导体元件
2电极
3绝缘膜
4粘合层
5键合层
6保护膜
7键合树脂层
8主要材料部分
9接合材料部分
10凸块
11划片线
12抗蚀剂
13掩模
14阻挡金属
15焊块
101、102、103、104、105和1101半导体器件
201和1201电路器件

Claims (25)

1.一种具有电极的半导体器件，其特征在于包括：
绝缘部分，在所述电极上具有开口；
突出部分，形成于所述电极上；
保护部分，形成于所述突出部分的周界，并且电隔离所述突出部分；以及
键合部分，形成于所述保护部分上与所述突出部分间隔开，其中：
所述突出部分的上表面、所述保护部分的上表面和所述键合部分的上表面形成相同平面。
2.根据权利要求1所述的半导体器件，其特征在于：
所述突出部分包括主要材料部分和接合材料部分，并且
所述接合材料部分为层状，并且形成于所述主要材料部分上。
3.根据权利要求2所述的半导体器件，其特征在于：
所述主要材料部分包括铜(Cu)。
4.根据权利要求2或者3所述的半导体器件，其特征在于：
所述接合材料部分包括银(Au)和锡(Sn)中的至少一种。
5.根据权利要求1至4中的任一权利要求所述的半导体器件，其特征在于：
在一侧表面上，所述保护部分由所述键合部分所覆盖。
6.根据权利要求1至5中的任一权利要求所述的半导体器件，其特征在于还包括多个突出部分，其中：
所述保护部分具有在所述突出部分之间为弓形形状的横截面。
7.根据权利要求1至6中的任一权利要求所述的半导体器件，其特征在于：
所述保护部分为包括聚酰亚胺的有机膜。
8.根据权利要求1至6中的任一权利要求所述的半导体器件，其特征在于：
所述保护部分包括无机膜。
9.根据权利要求1至8中的任一权利要求所述的半导体器件，其特征在于还包括多个突出部分，其中：
所述保护部分在所述突出部分之间、具有不多于所述多个突出部分的高度的一半的厚度。
10.根据权利要求1至9中的任一权利要求所述的半导体器件，其特征在于：
所述键合部分包括处于半硬状态的热硬化树脂、热硬化和光敏树脂以及热塑树脂中的至少一种。
11.一种用于制造半导体器件的方法，其特征在于包括：
在具有电极的半导体元件上形成绝缘部分的步骤，所述绝缘部分在所述电极上具有开口；
在所述电极上形成突出部分的主要材料部分的步骤；
在所述绝缘部分和所述主要材料部分上形成保护部分的步骤；
在所述保护部分上供应键合部分的材料的步骤；以及
执行平坦化工艺，从而使得所述主要材料部分的表面、在所述主要材料部分的周界中的所述保护部分的表面和所述键合部分的表面形成相同平面的步骤。
12.根据权利要求11所述的用于制造半导体器件的方法，其特征在于还包括：
在所述绝缘部分和所述主要材料部分上形成所述保护部分的步骤之后、并且在所述保护部分上供应所述键合部分的材料的步骤之前的去除形成于划片线上的所述保护部分的步骤。
13.根据权利要求11或者12所述的用于制造半导体器件的方法，其特征在于还包括：
在所述主要材料部分的表面上形成接合材料部分的步骤。
14.一种用于制造半导体器件的方法，其特征在于包括：
在具有电极的半导体元件上形成绝缘部分的步骤，所述绝缘部分在所述电极上具有开口；
在所述电极上形成突出部分的主要材料部分的步骤；
在所述绝缘部分和所述主要材料部分上形成保护部分的步骤；
执行平坦化工艺，从而使得所述主要材料部分的表面和在所述主要材料部分的周界中的所述保护部分的表面形成相同平面的步骤；
去除形成于划片线上的保护部分的步骤；
供应键合部分的材料的步骤；以及
通过使用掩模对所述键合部分成形的步骤。
15.根据权利要求14所述的用于制造半导体器件的方法，其特征在于还包括：
在所述主要材料部分的表面上形成接合材料部分的步骤；以及
针对所述键合部分执行干蚀刻、并且暴露所述接合材料部分的表面的步骤。
16.根据权利要求14或者15所述的用于制造半导体器件的方法，其特征在于：
通过使用浸镀浴借助无电镀覆方法执行所述在所述主要材料部分的表面上形成接合材料部分的步骤。
17.根据权利要求11至16中的任一权利要求所述的用于制造半导体器件的方法，其特征在于：
所述供应所述键合部分的材料的步骤是层叠膜状半硬树脂的步骤。
18.根据权利要求11至16中的任一权利要求所述的用于制造半导体器件的方法，其特征在于：
所述供应所述键合部分的材料的步骤是通过旋涂供应液体树脂、并且此后加热所述树脂以使所述树脂变成半硬状态的步骤。
19.根据权利要求11至16中的任一权利要求所述的用于制造半导体器件的方法，其特征在于：
所述供应所述键合部分的材料的步骤是通过旋涂供应液体树脂、并且此后暴露所述树脂以使所述树脂处于半硬状态的步骤。
20.根据权利要求11至13中的任一权利要求所述的用于制造半导体器件的方法，其特征在于：
用抛光方法、研磨方法和化学机械抛光方法中的至少一种方法执行所述执行平坦化工艺，从而使得所述主要材料部分的表面、在所述主要材料部分的周界中的所述保护部分的表面和所述键合部分的表面形成相同平面的步骤。
21.根据权利要求14至16中的任一权利要求所述的用于制造半导体器件的方法，其特征在于：
用抛光方法、研磨方法和化学机械抛光方法中的至少一种方法执行所述执行平坦化工艺，从而使得所述主要材料部分的表面和在所述主要材料部分的周界中的所述保护部分的表面形成相同平面的步骤。
22.根据权利要求12至14中的任一权利要求所述的用于制造半导体器件的方法，其特征在于：
用激光方法和光刻方法中的至少一种方法执行所述去除形成于所述划片线上的所述保护部分的步骤。
23.根据权利要求14至16中的任一权利要求所述的用于制造半导体器件的方法，其特征在于：
所述掩模包括突出部分，并且
所述通过使用所述掩模对所述键合部分成形的步骤包括在所述划片线上压印所述突出部分的步骤。
24.根据权利要求14至16中的任一权利要求所述的用于制造半导体器件的方法，其特征在于：
通过用光刻方法执行所述通过使用所述掩模对所述键合部分成形的步骤。
25.一种电路器件，包括具有电极的半导体器件，其特征在于：
所述半导体器件包括：
绝缘部分，在所述电极上具有开口；
突出部分，形成于所述电极上；
保护部分，形成于所述突出部分的周界，并且电隔离所述突出部分；以及
键合部分，形成于所述保护部分上与所述突出部分间隔开，其中：
所述突出部分的上表面、所述保护部分的上表面和所述键合部分的上表面形成相同平面。
CN2010800284431A 2009-06-24 2010-06-23 半导体器件、半导体器件制造方法和使用半导体器件的电路器件 Pending CN102460670A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990292A (zh) * 2015-03-17 2016-10-05 株式会社东芝 半导体装置及其制造方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9082832B2 (en) 2011-09-21 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming protection and support structure for conductive interconnect structure
US9484259B2 (en) * 2011-09-21 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming protection and support structure for conductive interconnect structure
US8653658B2 (en) 2011-11-30 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Planarized bumps for underfill control
US9202714B2 (en) * 2012-04-24 2015-12-01 Micron Technology, Inc. Methods for forming semiconductor device packages
US8659153B2 (en) * 2012-07-16 2014-02-25 Micron Technology, Inc. Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods
US9236277B2 (en) * 2012-08-10 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit with a thermally conductive underfill and methods of forming same
US10115703B2 (en) 2015-03-17 2018-10-30 Toshiba Memory Corporation Semiconductor device and manufacturing method thereof
KR102598752B1 (ko) 2018-05-30 2023-11-03 삼성전자주식회사 유전 복합체, 및 이를 포함하는 적층형 커패시터 및 전자 소자

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077145A (ja) * 1999-09-07 2001-03-23 Casio Comput Co Ltd 半導体装置の製造方法
JP2003086626A (ja) * 2001-09-13 2003-03-20 Matsushita Electric Ind Co Ltd 電子部品、その製造方法、電子部品の実装体および実装方法
JP2005129874A (ja) * 2003-10-27 2005-05-19 Seiko Epson Corp 半導体チップ、半導体チップの製造方法、半導体実装基板、電子デバイスおよび電子機器
US20080191357A1 (en) * 2007-01-25 2008-08-14 Casio Computer Co., Ltd. Semiconductor device comprising electromigration prevention film and manufacturing method thereof

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05291262A (ja) * 1992-04-07 1993-11-05 Toshiba Corp バンプ電極の形成方法
JP4120133B2 (ja) * 2000-04-28 2008-07-16 沖電気工業株式会社 半導体装置及びその製造方法
JP3851607B2 (ja) 2002-11-21 2006-11-29 ローム株式会社 半導体装置の製造方法
TWI223363B (en) * 2003-11-06 2004-11-01 Ind Tech Res Inst Bonding structure with compliant bumps
US7960830B2 (en) * 2003-11-14 2011-06-14 Industrial Technology Research Institute Electronic assembly having a multilayer adhesive structure
JP4353845B2 (ja) 2004-03-31 2009-10-28 富士通株式会社 半導体装置の製造方法
KR101134168B1 (ko) * 2005-08-24 2012-04-09 삼성전자주식회사 반도체 칩 및 그 제조 방법과, 그를 이용한 표시 패널 및그 제조 방법
JP2007142232A (ja) 2005-11-21 2007-06-07 Henkel Corp バンプ付電子部品の実装方法
JP2008244383A (ja) * 2007-03-29 2008-10-09 Casio Comput Co Ltd 半導体装置およびその製造方法
US7781867B2 (en) * 2007-12-28 2010-08-24 Fujitsu Limited Method and system for providing an aligned semiconductor assembly
EP2257143A1 (en) * 2008-02-29 2010-12-01 Sumitomo Bakelite Co., Ltd. Solder connecting method, electronic device and method for manufacturing same
US7851346B2 (en) * 2008-07-21 2010-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding metallurgy for three-dimensional interconnect
WO2010047006A1 (ja) * 2008-10-23 2010-04-29 パナソニック株式会社 半導体装置およびその製造方法
KR101234597B1 (ko) * 2009-10-15 2013-02-22 한국전자통신연구원 플립 칩 본딩 방법 및 그의 구조
US8610270B2 (en) * 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US9018758B2 (en) * 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077145A (ja) * 1999-09-07 2001-03-23 Casio Comput Co Ltd 半導体装置の製造方法
JP2003086626A (ja) * 2001-09-13 2003-03-20 Matsushita Electric Ind Co Ltd 電子部品、その製造方法、電子部品の実装体および実装方法
JP2005129874A (ja) * 2003-10-27 2005-05-19 Seiko Epson Corp 半導体チップ、半導体チップの製造方法、半導体実装基板、電子デバイスおよび電子機器
US20080191357A1 (en) * 2007-01-25 2008-08-14 Casio Computer Co., Ltd. Semiconductor device comprising electromigration prevention film and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990292A (zh) * 2015-03-17 2016-10-05 株式会社东芝 半导体装置及其制造方法

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