CN102456587A - 实现连接结构的方法 - Google Patents

实现连接结构的方法 Download PDF

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Publication number
CN102456587A
CN102456587A CN2011103070017A CN201110307001A CN102456587A CN 102456587 A CN102456587 A CN 102456587A CN 2011103070017 A CN2011103070017 A CN 2011103070017A CN 201110307001 A CN201110307001 A CN 201110307001A CN 102456587 A CN102456587 A CN 102456587A
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semiconductor substrate
substrate
syndeton
layer
block structure
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CN102456587B (zh
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迪迪埃·朗德吕
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Sony Semiconductor Solutions Corp
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Soitec SA
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Abstract

本发明涉及实现半导体衬底(1000)中的连接结构(2200)的方法，并且涉及相应地实现的半导体衬底。半导体衬底(1000)至少具有第一表面并沿第一表面与第二衬底(1700)3D集成，其中该3D集成经受至少一个维度上的横向错位，该横向错位具有错位值；本发明的方法可包括生长扩散阻挡结构(2211)以防止导电层的元素扩散到半导体衬底的其余部分的步骤，其特征在于：扩散阻挡结构(2211)的第一端面可以在横向错位的方向上具有依赖于错位值的长度，该第一端面是扩散阻挡结构的沿垂直于第一表面且从衬底向第一表面的方向的与第一表面大致平行的最外侧表面，其中扩散阻挡结构(2211)的长度被选择为在3D集成结构中防止第二衬底(1700)的导电层的元素在集成状态下扩散。

Description

实现连接结构的方法
技术领域
本发明涉及实现半导体衬底中的连接结构的方法和包括实现这种连接结构的半导体衬底的半导体系统。
背景技术
随着标准半导体制造技术向着更短的栅级长度推进，这些技术接近了常规半导体技术的制造极限。为了进一步提高性能、降低功耗和封装成本，诸如3D集成的集成技术变得越来越普遍。
3D集成在于通过将诸如半导体管芯、光学模块、散热模块、生物学模块和存储器的至少两个模块一个接一个地堆叠起来以使它们连接。这种方案具有很多优点。由于集成是在竖直方向上进行的，因此更加放宽了对PCB的要求。通过将模块彼此连接而不使用长的连接电缆或者导线，改善了输入/输出接口的功耗并提高了信号质量。由于要求单个封装而不是多个封装，成本降低。这种集成技术使得能够将单个封装中的高复杂度的系统小型化。
已经开发出了连接相互堆叠的多个模块的多种技术。为了将两个模块一个接一个地相互连接起来，一种可能的技术是直接接合。在该技术中，两个模块(例如，两个半导体管芯)被一个压一个地布置，并且在相对低的温度相互压紧，从而可以产生两个管芯之间的界面处的电接触。
例如，如图8A可见，具有第一表面8100的第一半导体管芯8000可以包括由导电层8220构成的连接结构8200，导电层8220被扩散阻挡层8211包围。同时，第二半导体管芯8700可以具有第一表面8710并且可以具有包括导电层8220和扩散阻挡层8211的连接结构8200。第一半导体管芯8000的连接结构8200和第二半导体管芯8700的连接结构8200可以大致相似。
通过在第一半导体管芯8000的顶部按压第二半导体管芯8700而使得第二半导体管芯8700的第一表面8710挤压第一半导体管芯8000的第一表面8100，可以进行3D集成。在该过程中，应至少沿方向1900将第一半导体管芯8000与第二半导体管芯8700对准，使得第一半导体管芯8000的连接结构8200与第二半导体管芯8700的大致相似的连接结构8200对准。在图8B和专利文献US 6,962,835中对此进行了例示。
然而，由于技术限制，可能很难获得完美的对准。实际上，至少在一个方向上可能存在小的错位(mismatch)。例如，在方向1900上，如图8A中的错位值M所例示的那样。当这种3D集成的执行受到错位值M的影响时，可以得到如图8C所例示的结果。
从图8C可见，第一半导体管芯8000的连接结构8200可能不与第二半导体管芯8700的连接结构8200对准。因此可以存在不重合区域8500，其中，第二半导体管芯8700的连接结构8200的导电层8220被置于第一半导体管芯8000的连接结构8200的扩散阻挡层8211上并且被置于半导体管芯8000的不包括第一半导体管芯8000的连接结构8200的区域上。
在这种情况下，如果例如使用铜来实现第二半导体管芯8700的连接结构8200的导电层8220并且第一半导体管芯例如是硅半导体管芯，则铜有可能通过区域8500扩散到第一半导体管芯8000的不对应于第一半导体管芯8000的连接结构8200的部分中。
该问题存在于当前的3D集成技术中，并且因此可阻碍或者限制这种技术在集成系统的工业制造中得到应用。
发明内容
因此，本发明的目的是提供一种经受3D集成的半导体衬底的连接结构，使得即使在3D集成处理期间存在错位的情况下也阻止构成连接结构的金属扩散。
上述目的可以通过本发明的教导来获得。
根据本发明的实施方式，一种实现半导体衬底中的连接结构的方法，所述半导体衬底至少具有第一表面并且将沿所述第一表面与第二衬底进行3D集成，其中，所述3D集成经受至少一个维度上的横向错位，所述错位具有错位值(M)；该方法可以包括生长扩散阻挡结构以防止导电层的元素扩散到所述半导体衬底的其余部分的步骤，其特征在于：所述扩散阻挡结构的第一端面可以在所述横向错位的方向上具有依赖于所述错位值长度，所述第一端面是所述扩散阻挡层的沿与所述第一表面垂直并且从所述衬底向着所述第一表面的方向与所述第一表面大体平行的最外侧表面，其中，选择所述扩散阻挡结构的所述长度，使得在3D集成结构中，在集成状态下防止来自所述第二衬底的导电层的元素扩散。
通过执行该方法，可以实现一种连接结构，即使在3D集成期间存在错位的情况下，该连接结构也可以在3D集成过程中与对应的第一集成衬底上的连接结构对准。通过将错位值考虑在内，可以调整扩散阻挡结构的大小以补偿错位并防止导电元素扩散。
在一些实施方式中，所述长度可以至少与所述横向错位值相同。
通过选择扩散阻挡结构的长度使得该长度至少是错位值，即使在存在最大错位的情况下，也可以确保防止导电元素的扩散。
在一些实施方式中，所述长度可以至少与所述第二衬底的所述导电层沿错位方向的长度相同。
通过选择扩散阻挡结构的长度使得该长度至少与第二衬底的导电层沿错位方向的长度相同，只要实现了第一衬底的导电层与第二衬底的导电层之间的接触就可以确保防止导电元素的扩散。
在一些实施方式中，实现连接结构的方法可以还包括以下步骤：在生长了所述扩散阻挡结构之后，至少生长导电层，使得所述导电层至少被所述扩散阻挡结构从所述半导体衬底分隔开。
通过在生长扩散阻挡结构之后生长导电元素，能够获得具有第一端面的长度的扩散阻挡结构，该长度对应于扩散阻挡结构的厚度，接着将导电元素直接淀积在扩散阻挡结构的顶部。这样，仅需要扩散阻挡结构和导电元素这两种淀积物。
在一些实施方式中，该实现连接结构的方法还可以包括以下步骤：在生长所述扩散阻挡结构之前，至少生长导电层。
通过在生长扩散阻挡结构之前生长导电元素，能够仅在与已生长了导电元素的位置的特定区域中获得具有要求的长度的扩散阻挡结构。
在一些实施方式中，所述生长所述扩散阻挡结构的步骤可以包括生长扩散阻挡层的步骤。
通过使用扩散阻挡层作为扩散阻挡结构，可以精确地控制生长扩散阻挡结构的过程。另外，通过使用扩散阻挡层作为扩散阻挡结构，生长扩散阻挡结构可以仅需要单个制造步骤。
在一些实施方式中，所述生长所述扩散阻挡结构的步骤还可以包括以下步骤：在所述扩散阻挡层上生长第二层，该第二层的生长速度高于所述扩散阻挡层的生长速度。
通过将两个层用于生长扩散阻挡结构，能够采用一个具有低生长速度的较薄的扩散阻挡层以及具有较快生长速度的第二层。在这种情况下，能够使用同一组掩膜来淀积两个层。然而，由于第二层的较快生长速度，可获得更迅速的生产。
在一些实施方式中，所述生长所述扩散阻挡层的步骤可以包括以下步骤：生长钽(Ta)、氮化钽(TaN)、氮化硅(Si3N4)中的至少一种的层。
通过在这些元素之间选择扩散阻挡层，可以获得防止导电材料扩散的最优效果。
在一些实施方式中，所述扩散阻挡结构的所述长度可以介于20nm与1μm之间。
通过生长长度大体上比标准扩散阻挡层的通常长度长的扩散阻挡结构，即使在错位的情况下也可以实现防止导电元素扩散的优点。
根据本发明的另一实施方式的用于获得至少两个半导体衬底的3D集成的方法可以包括以下步骤：根据上述本发明的实施方式，根据实现半导体衬底中的连接结构的方法而在两个半导体衬底中的至少一个半导体衬底但优选地在每一个半导体衬底中实现连接结构；沿所述两个半导体衬底中的每一个半导体衬底的所述第一表面接合所述两个半导体衬底。
通过使用在用于实现半导体衬底中的连接结构的方法中获得的两个衬底来实现3D集成，根据本发明的实施方式，能够实现两个衬底之间的连接，该连接即使在3D集成处理期间存在错位时也能够防止半导体材料的非期望的扩散。
在一些实施方式中，所述接合两个半导体衬底的步骤可以包括以下步骤：将两个半导体衬底彼此接合特别是键合到一起。
通过将两个衬底键合到一起，可以确保稳固的连接，并且可以防止连接区域的进一步错位。
根据本发明的另一实施方式的半导体系统至少可以包括：第一衬底和第二衬底，至少所述第一衬底包括连接结构，其中所述第一衬底至少具有第一表面并且沿所述第一表面与所述第二衬底3D集成，其中所述3D集成在至少一个维度上具有横向错位，该横向错位具有错位值(M)；并且所述连接结构包括用于防止导电层的元素扩散到所述衬底的材料中的扩散阻挡结构，其特征在于，所述扩散阻挡结构被构造为使得所述扩散阻挡结构的第一端面在所述横向错位的方向上具有依赖于所述错位值的长度(L)，所述第一端面是所述扩散阻挡结构的沿与所述第一表面垂直并从所述衬底向着所述第一表面的方向与所述第一表面大体平行的最外侧表面，其中，选择所述扩散阻挡结构的所述长度(L)，使得所述第二衬底的导电层的元素的扩散被防止。
通过以这种方式实现半导体系统，即使在3D集成期间存在错位时也能够在3D集成处理期间实现第一衬底和第二衬底的对应连接结构之间的稳定电连接。通过将错位值考虑在内，可以确定扩散阻挡结构的大小以补偿错位并防止导电元素扩散。
在一些实施方式中，所述长度可以至少与所述横向错位值相同。
通过选择扩散阻挡结构的长度使得该长度至少是错位值，即使在最大错位的情况下也可以确保防止导电元素扩散。
在一些实施方式中，所述长度可以至少与所述第二衬底的所述导电层的沿错位的方向的长度相同。
通过选择扩散阻挡结构的长度使得该长度至少与第二衬底的导电层的沿错位的方向的长度相同，只要实现第一衬底的导电层和第二衬底的导电层之间接触，就可以确保防止导电元素扩散。
在一些实施方式中，所述连接结构还可以至少包括导电层，使得所述导电层至少被所述扩散阻挡结构从所述第一衬底分隔开。
通过利用扩散阻挡结构从衬底分隔导电元素，能够使用扩散阻挡结构来防止第一衬底的连接结构的导电元素扩散到第一衬底中以及防止第二衬底的连接结构的导电元素扩散到第一衬底中。
在一些实施方式中，所述扩散阻挡结构可以包括扩散阻挡层。
通过使用扩散阻挡层作为扩散阻挡结构，可以精确地控制生长扩散阻挡结构的过程。另外，通过使用扩散阻挡层作为扩散阻挡结构，生长扩散阻挡结构仅需要单个制造步骤。
在一些实施方式中，所述扩散阻挡结构可以包括扩散阻挡层和位于所述扩散阻挡层上的第二层，该第二层的生长速度高于所述扩散阻挡层的生长速度。
通过使用两个层来生长扩散阻挡结构，能够采用一个具有较慢生长速度的较薄的扩散阻挡层以及具有较快生长速度的第二层。在这种情况下，能够使用同一组掩膜来淀积两个层。然而，由于第二层的更快的生长速度，可以获得更迅速的生产。
在一些实施方式中，所述扩散阻挡层可以是钽(Ta)、氮化钽(TaN)、氮化硅(Si3N4)中的任一种。
通过在这些元素之间选择扩散阻挡层，可以获得防止导电材料扩散的最优效果。
附图说明
附图被包括在说明书中并形成说明书的一部分以例示本发明的多个实施方式。这些附图与说明书一起用于解释本发明的特征、优点和原理。附图仅仅是为了例示如何实施和使用本发明的优选示例和另选示例，而不意在将本发明解释为将本发明仅限制为例示和描述的实施方式。从以下对本发明的各实施方式的更具体的描述，其他特征和优点将变得明显，如附图中所例示的，其中类似的附图标记表示相似元素，其中：
图1是例示本发明的实施方式中使用的用于3D集成的两个衬底的示意图；
图2是例示根据本发明的第一实施方式的实现连接结构的方法的示意图；
图3A是例示经历了根据本发明实施方式的3D集成的方法的两个衬底的示意图；
图3B是例示根据本发明实施方式的两个衬底的3D集成的结果的示意图；
图4是例示根据本发明的第二实施方式的实现连接结构的方法的示意图；
图5是例示根据本发明的第三实施方式的实现连接结构的方法的示意图；
图6A和图6B是例示根据本发明的第四实施方式的实现连接结构的方法的示意图；
图7A和图7B是例示根据本发明的第五个实施方式的包括两个衬底的3D系统的示意图；
图8A是例示经历根据现有技术的3D集成的方法的两个衬底的示意图；
图8B是例示根据现有技术的两个衬底的3D集成的结果的示意图，其中不存在集成错位；
图8C是例示根据现有技术的两个衬底的3D集成的结果的示意图，其中存在集成错位。
具体实施方式
在以下描述中，为了说明的目的，阐述了具体细节以提供对本发明的彻底理解。然而明显地是，本发明的实施可以不需要这些具体细节。
从图8可见，第一半导体管芯8000的连接结构8200的导电层8220和扩散阻挡层8211沿与第一表面8100相对应的表面的形状可以与第二半导体管芯8700的连接结构8200的导电层8220和扩散阻挡层8211沿与第一表面8710相对应的表面的形状大致相同。
导电层8220可以用于承载电信号，并且可以利用具有适于传播这种信号的电气性能的材料来实现。扩散阻挡层可以用于防止导电层8220的材料扩散到第一半导体管芯8000或者第二半导体管芯8700中。
对准意味着可以按照使第一半导体管芯8000的连接结构8200的导电层8220的表面与第二半导体管芯8700的连接结构8200的导电层8220的表面沿包括方向1900并且垂直于方向1800的平面占据大致相同的区域的方式，沿方向1900布置第一半导体管芯8000。同时，对准意味着可以按照使第一半导体管芯8000的连接结构8200的扩散阻挡层8220的表面与第二半导体管芯8700的连接结构8200的扩散阻挡层8220的表面沿包括方向1900并且垂直于方向1800的平面占据大致相同区域的方式，沿方向1900布置第一半导体管芯8000。图8B例示了这种情形。
然而，由于技术限制而可能不能得到如图8B中例示的情形，所以必须获得这样一种结构，在该结构中，即使存在错位，也可以防止导电材料在半导体衬底中的扩散。
图1例示了经历3D集成的第一半导体衬底1000和第二半导体衬底1700。3D集成可以包括键合处理。
第一半导体衬底1000至少具有第一表面1100，并且第二半导体衬底1700至少具有第一表面1710。半导体衬底1000和1700两者都可以包括诸如晶体管、二极管、电容器、金属导线和通孔等以标号1600标示的多个电路。第一半导体衬底1000和第二半导体衬底1700均可以附加地包括图1中未例示的其它模块，例如，光学模块、生物模块、存储器和/或电源模块。此外，第一半导体衬底1000和第二半导体衬底1700中的一方或全部可以包括硅晶片、绝缘体上硅晶片、玻璃衬底或更一般的衬底中的任一种。
通过在箭头1150指示的预定环境中使第一半导体衬底1000和第二半导体衬底1700沿方向1800彼此接近并在预定温度施加预定量的压力以将它们沿与第一表面1100和第一表面1710相对应的表面键合起来，可以集成第一半导体衬底1000和第二半导体衬底1700。
键合可以具体地对应于在US 6,962,835中公开的技术，或者更优选地对应于DiCioccio和Al(IITC 2009)的“Enabling 3D Interconnects with Metal Direct Bonding”中公开的技术。还可以是例如外部热压键合(thermo compression bonding)的其它技术。
另外，第一半导体衬底1000和第二半导体衬底1700两者都包括被布置在沿包括方向1900并且垂直于方向1800的平面的大致相似的位置的连接结构1200，使得当这两个半导体衬底沿方向1800彼此接近时，第一半导体衬底1000的连接结构1200与对应的第二半导体衬底1700的连接结构1200发生接触。例如，第一半导体衬底1000的连接结构1201将接触到第二半导体衬底1700的连接结构1202。尽管图1仅例示了两个连接结构，但是无疑可以存在更多个连接结构。
图2是例示根据本发明的第一实施方式的实现连接结构的方法的示意图。更具体地，图2例示了实现诸如第一半导体衬底1000的连接结构1201和/或第二半导体衬底1700的连接结构1202和/或图1的任何连接结构1200的连接结构2200的方法。
半导体衬底2000A包括孔2300，从图2可见。通过步骤S20(通过执行例如光刻或者刻蚀)，可以从半导体衬底开始获得孔2300。可以按照半导体制造领域已知的方式来控制孔2300的大小、形状、深度和位置。
通过执行淀积和/或生长步骤S21，在半导体衬底2000A的顶部获得了扩散阻挡层2211，以获得半导体衬底2000B。可以按照诸如淀积和/或生长(包括例如化学气相沉积(CVD)、物理气相沉积(PVD)、外延或者其它技术)已知的半导体衬底制造方法来执行扩散阻挡层2211的获得。扩散阻挡层可以是例如具有阻挡诸如例如钽(TA)、氮化钽(TAN)或氮化硅(SI3N4)的金属原子的扩散的属性的材料层。
随后，通过步骤S22A(可包含导电层2221的籽晶淀积)，获得了半导体衬底2000C。可以利用诸如PVD籽晶或者CVD籽晶的本领域已知技术来进行籽晶淀积处理。导电层2221可以是例如铜、银、金或者具有导电性的任何其它材料。
随后，通过步骤S22B(包含导电层2222的淀积)，获得了半导体衬底2000D。步骤S22B可以包含电化学淀积(ECD)。导电层2222可以是与导电层2221相同的材料，这可以帮助导电层2222键合在导电层2221上。另选地，导电层2222可以是与导电层2221不同的材料，这可以加速生长过程，或者可以提供更好的导电性，或者可以降低生产成本。
随后，半导体衬底2000D可以经历化学机械抛光(CMP)步骤S23，以获得半导体衬底2000E。
由于本方法，实现了如在半导体衬底2000E中例示的连接结构2200。
连接结构2200包括扩散阻挡层2211和导电层2220。另外，扩散阻挡层2211具有与半导体衬底2000E的第一表面2100大致平行的表面2230。在本实施方式中，端面2230的大小大体上由在步骤S21中形成了沉积的扩散阻挡层2211的材料的厚度d决定。因此，通过在步骤S21期间控制淀积材料的量，有可能至少沿方向1900控制端面2230的长度L。
在半导体衬底2000E中，扩散阻挡层2211的表面2230可以用作扩散阻挡结构，由此即使在存在错位时也防止第二半导体衬底的导电层的元素扩散到半导体衬底2000E中。
图3A是例示经历根据本发明的第一实施方式的3D集成处理的两个衬底的示意图。更具体地，图3A例示了沿方向1800经历3D集成的第一半导体衬底1000和第二半导体衬底1700。
从图3A可见，第一半导体衬底1000可以沿方向1900与第二半导体衬底1700具有横向错位。沿方向1900的横向错位可以具有值M(例如，大致20nm到大致1μm，或甚至大于1μm)。第一半导体衬底1000和第二半导体衬底1700都包括通过图2的方法而实现的连接结构2200。连接结构2200因而具有用作扩散阻挡结构的表面2230，表面2230在方向1900上具有与值L相对应的长度，该长度通常在20nm到大致1μm。
图3B是例示根据本发明的实施方式的两个衬底的3D集成的结果的示意图。更具体地，图3B例示了通过第一半导体衬底1000和第二半导体衬底1700的3D集成而获得的半导体系统。
在一个另选实施方式中，在方向1900上，第一半导体衬底1000的表面2230的长度L可以比第二半导体衬底1700的导电层2220的长度长。通过这样选择长度L，只要实现了第一半导体衬底1000的导电层2220和第二半导体衬底1700的导电层2220之间接触，就能够确保防止扩散。
从图3B可见，第一半导体衬底1000的连接结构2200与第二半导体衬底1700的连接结构2200错位。然而，由于第一半导体衬底1000的连接结构2200的扩散阻挡层2211，可以防止第二半导体衬底1700的连接结构2200的导电层2220扩散到第一半导体衬底1000中。因此，与图8C中示出的导电材料可通过区域8500扩散的现有技术不同，第二半导体衬底1700的导电层2220总是被布置在包括第一半导体衬底1000的导电层2220的区域上或者被布置在包括第一半导体衬底的导电层2220和表面2230的区域上。由此，可以防止构成导电层2200的材料扩散到半导体衬底1000中。
更具体地，从图3A可见，第一半导体衬底1000的连接结构2200的扩散阻挡层2211可以具有端面2230，端面2230在错位的方向1900上具有长度L。通过将长度值L选择为至少与错位值M一样大，可以获得图3B例示的结果。更具体地，通过将表面2230在方向1900上的长度L选择为至少对应于方向1900上的错位值M，确保了第二半导体衬底1700的连接结构2200的导电层2220仅被布置在第一半导体衬底1000的连接结构2200的导电层2220上或者被布置在第一半导体衬底1000的连接结构2200的扩散阻挡层2211的表面2230上。换句话说，通过将表面2230的长度L选择为至少与错位值M一样大，可以防止第二半导体衬底1700的连接结构2200的导电材料2220扩散到第一半导体衬底1000中。
另选地或者另外，例如，可以将表面2230的长度L设定为连续3D集成中的最大错位值M或者连续3D集成中的平均错位值M的函数。由此，可以确保按照绝对值计算或者按平均值计算，错位将不造成半导体衬底1000和/或1700中的导电材料2200扩散。
另选地或者另外，可以将第一半导体衬底1000中的表面2230的长度L设定为至少与第二半导体衬底1700的连接结构的导电材料2220的长度一样大。由此，保证了只要第一半导体衬底1000的导电材料2220和第二半导体衬底1700的导电材料2220发生接触，就将防止扩散。在错位值未知而第二半导体衬底1700的连接结构的导电材料2220的长度已知的情况下，这是有利的。
另外，对于半导体衬底1000的不同位置来说，错位值M可以不同。例如，除了制造公差或者操作机所引起的错位以外，可能存在由于施加在半导体衬底上的压力而引起的错位，或者存在由于基板上的温度梯度而引起的错位。在整个晶片上的错位值M不恒定的情况下，当针对位于晶片的不同部分中的不同连接结构2200而选择表面2230的值L时，可以将此考虑在内。
图4是例示根据本发明的第二实施方式的实现连接结构4200的方法的示意图。更具体地，图4例示了实现诸如第一半导体衬底1000的连接结构1201和/或第二半导体衬底1700的连接结构1202和/或图1的任何连接结构1200的连接结构4200的方法。
从图4可见，通过步骤S40，可以获得半导体衬底4000A，半导体衬底4000A具有第一孔4320和朝向表面4100环绕第一孔的第二孔4310。通过步骤S40(通过执行例如光刻或者刻蚀)，可以从半导体衬底开始获得第一孔4320。可以按照半导体制造领域已知的方式来控制第一孔4320的大小、形状、深度和位置。通过步骤S40(通过执行例如光刻或者刻蚀的已知处理)，可以从半导体衬底开始获得第二孔4310。可以按照半导体制造领域已知的方式来控制第二孔4310的大小、形状、深度和位置。另选地或者另外，可以在单个光刻步骤中获得第一孔4320和第二孔4310。
可以将第二孔4310至少在方向1900上的长度选择为与期望长度L相对应。
随后，经过步骤S41，在半导体衬底4000A上淀积了扩散阻挡层4211，以获得半导体衬底4000B。进行步骤S41所用的技术可以与进行图2中的步骤S21所用的技术大致相似。另外，扩散阻挡层4211可以与图2中的扩散阻挡层2211大致相似。
随后，经过步骤S42A和S42B，在半导体衬底4000B上淀积了导电层4221和导电层4222，以分别获得半导体衬底4000C和4000D。步骤S42A和S42B可以与图2中的步骤S22A和S22B大致相似。另外，导电层4221和导电层4222可以分别与图2中的导电层2221和导电层2222大致相似。
最后，经过步骤S43，获得了半导体衬底4000E。步骤S43可以与图2中的步骤S23大致相似。在步骤S43之后，保留在第二孔4310中的扩散阻挡层4211的材料至少在方向1900上至少在表面4100的表面区域4230中具有与期望值L相对应的长度，因而即使在3D结构中存在错位的情况下也在3D结构中充当扩散阻挡结构。
由于在图4概括的方法，可以实现包括导电元素4220和扩散阻挡层4211的连接结构4200。导电元素4220可以与图2中的导电元素2220大致相同。在另一方面，由于第二孔4310，扩散阻挡层4211在体积上可以大致比图2的扩散阻挡层2211更薄。尽管更薄，但是在孔4310中淀积的扩散阻挡层4211仍然提供与图2的表面2230大致相似的表面4230。因此，通过图4的连接结构4200，可以获得与图2的连接结构2200相同的优点。另外，由于在步骤S41中生长扩散阻挡层4211可以是相对长的操作，因此在生长更薄的层4211的同时仍然获得具有期望长度L的大表面4230的可能性在降低成本方面和减少处理时间方面都是有利的。
在半导体衬底4000E中，扩散阻挡层4211的表面4230可用作扩散阻挡结构，由此即使在存在错位的情况下也防止第二半导体衬底的导电层的元素扩散到半导体衬底4000E中。
图5是例示根据本发明的第三实施方式的实现连接结构5200的方法的示意图。更具体地，图5例示了实现诸如图1中的第一半导体衬底1000的连接结构1201和/或第二半导体衬底1700的连接结构1202和/或任何连接结构1200的连接结构5200的方法。
图5例示了通过步骤S52获得的具有导电层5220和扩散阻挡层5212的半导体衬底5000A。进行步骤S52所用的技术可以与进行图2中的步骤S22A和S22B所用的技术大致相似。
随后，通过步骤S50，获得了半导体衬底5000B，半导体衬底5000B具有在扩散阻挡层5212上围绕导电层5220或者靠近表面5100的孔5310。可以按照半导体制造领域已知的方式来控制孔5310的大小、形状、深度和位置。进行步骤S50所用的技术可以与进行图2中的步骤S20所用的技术大致相似。
随后，经过步骤S51，在半导体衬底5000B上淀积扩散阻挡层5211，以获得半导体衬底5000C。进行步骤S51所用的技术可以与进行图2中的步骤S21所用的技术大致相似。另外，扩散阻挡层5211可以与图2中的扩散阻挡层2211大致相似。在此步骤期间，至少孔5310被填充阻挡层材料。
最后，经过步骤S53，获得了半导体衬底5000D。步骤S53可以是与图2中的步骤S23大致相似的CMP，以去除过多的材料。在步骤S43之后，至少在方向1900上，保留在孔5310中的扩散阻挡层5211的材料可以至少在表面5230中具有与期望值L相对应的长度，来充当扩散阻挡结构。
通过执行图5中描述的方法，在淀积了导电材料之后，能够获得扩散阻挡层5211。另外，能够获得具有期望长度L的表面5230，并且扩散阻挡层5211较薄。这具有提高制造速度并因而降低成本的优点。
在半导体衬底5000D中，扩散阻挡层5211的表面5230可以充当扩散阻挡结构，由此即使在存在错位时也防止第二半导体衬底的导电层的元素扩散到半导体衬底5000D中。
图6A和图6B是例示根据本发明的第四实施方式的实现连接结构6200的方法的示意图。更具体地，图6A和图6B例示了实现诸如图1中的第一半导体衬底1000的连接结构1201和/或第二半导体衬底1700的连接结构1202和/或任何连接结构1200的连接结构6200的方法。
如图6A所示，通过步骤S60，获得了具有第一孔6320的半导体衬底6000A。通过步骤S60，从大块半导体衬底开始获得了第一孔6320。进行步骤S60所用的技术可以与进行图2中的步骤S20所用的技术大致相似。
随后，经过步骤S61A，在半导体衬底6000A上淀积了扩散阻挡层6211，以获得半导体衬底6000B。进行步骤S61A所用的技术可以与进行图2中的步骤S21所用的技术大致相似。另外，扩散阻挡层6211可以与图2中的扩散阻挡层2211大致相似。
随后，经过步骤S61B，在半导体衬底6000B上淀积了第二层6213，以获得半导体衬底6000C。第二层6213淀积在扩散阻挡层6211上。第二层6213还充当扩散阻挡层并且可以是例如TiN，并且第二层6213的生长速度大于扩散阻挡层6211的生长速度。
由于淀积第二层6213时的工作状况，第二层6213的生长速度可以比扩散阻挡层6211的生长速度快。也就是说，扩散阻挡层6211的生长速度能够受到扩散阻挡层6211是淀积在半导体衬底6000A上的这个事实的影响，而由于第二层6213能够淀积在扩散阻挡层6211上的这个事实，第二层6213的生长速度可以更快。换句话说，由于对在具有良好特性以及没有孔的半导体衬底6000A上实现扩散阻挡层6211的淀积的约束，扩散阻挡层6211的淀积可能很慢。在另一方面，由于淀积在扩散阻挡层6211上而不是淀积在半导体衬底6000A上，第二层6213可以以更快的生长速度淀积。
另选地，在针对第二层6213和扩散阻挡层6211而描述的材料中，可以使用相同材料来获得第二层6213和扩散阻挡层6211，并且在淀积期间可以仅提高材料的生长速度，以利用较慢的生长速度在第一部分的淀积中获得较高质量的层，并且利用较快的生长速度在第二部分的淀积中获得较快速生长的层。
随后，经过步骤S62A和S62B，在半导体衬底6000C的第二层6213上淀积了导电层6221和6222，以分别获得半导体衬底6000D和6000E。步骤S62A和S62B可以与图2中的步骤S22A和S22B大致相似。另外，导电层6221和导电层6222可以分别与图2中的导电层2221和导电层2222大致相似。
在本实施方式以及先前的实施方式中，籽晶导电层6221可以不是必需的，可以不淀积导电层6221和导电层6222而只单独地执行导电层6222的淀积。
最后，经过步骤S63，获得了半导体衬底6000F。用于去除材料的步骤63可以是与图2中的步骤23大致相似的CMP方法。在步骤S63之后，组合的扩散阻挡层6211和6123提供了充当扩散阻挡结构的表面6230。
通过执行图6A和图6B概述的方法，与获得在方向1900上具有可比长度的扩散阻挡层所需要的时间相比，利用表面6230在相对较短的时间内获得了至少在方向1900上具有长度L的扩散阻挡结构。这样，与图2中的可以淀积较厚的扩散阻挡层2211的步骤S21相比，具有表面6230的扩散阻挡层6211、6213可以花费较少的时间。因此，可以降低制造成本。
在半导体衬底6000F中，扩散阻挡层6211和6213的表面6230可以充当扩散阻挡结构，从而即使在存在错位时也防止第二半导体衬底的导电层的元素扩散到半导体衬底6000F中。
图7A和图7B例示了根据本发明的第五实施方式的半导体系统7000。图7A是沿垂直于两个半导体衬底的平面截取的系统的截面图。图7B是沿垂直于图7A的平面截取的系统的顶视图。半导体系统7000是通过集成(3D集成)第一半导体衬底1000和第二半导体衬底1700而获得的。第一半导体衬底1000和第二半导体衬底1700两者都包括至少一个连接结构2200。可以利用先前实施方式中限定的任何方法来实现连接结构2200。附图标记2211A指示第一半导体衬底1000的扩散阻挡层，而附图标记2211B指示第二半导体衬底1700的扩散阻挡层。
另外，如从图7B的顶视图可见，第一半导体衬底1000可以沿着方向1800和沿着方向1900与第二半导体衬底1700错位。这两个方向上的错位值分别是M1800和M1900。在这种情况下，可以如下地选择扩散阻挡层2211A的尺寸7810、7820、7910、7920。
-尺寸7810，在方向1800上，可以是任意值，优选地至少是可被制造的值；
-尺寸7910，在方向1900上，可以是任意值，优选地至少是可被制造的值；
-尺寸7820，在方向1800上，可以将尺寸7820选择为按照先前实施方式描述的方式校正错位M1800。例如，可以选择为至少对应于错位值M1800；
-尺寸7920，在方向1900上，可以将尺寸7920选择为按照先前实施方式描述的方式校正错位M1900。例如，可以选择为至少对应于错位值M1900。
另选地或者另外，可以将尺寸7810选择为对应于尺寸7820，另选地或者另外，可以将尺寸7910选择为对应于尺寸7920，以简化设计和制造。
另选地或者另外，假定M1800大于M1900，可以将尺寸7810、7910、7920选择为对应于尺寸7820，以进一步简化设计过程。
通过如上所述地获得半导体系统7000，第一半导体衬底1000的导电区域2220A和第二半导体衬底1700的导电区域2220B可以至少部分地交叠，并且导电区域2220B可以仅交叠第一半导体衬底1000的包括导电区域2220A和扩散阻挡层2211A的区域。这样，可以防止导电区域2220B的导电元素扩散到半导体衬底1000中。
尽管在某些先前的实施方式中，仅涉及了用于获得第一半导体衬底1000的连接结构的方法和第一半导体衬底1000的连接结构的尺寸，但相同教导无疑也可以应用于第二半导体衬底1700。
在本发明的一些实施方式中，集成连接结构(包括例如连接结构100、1201、1202、4200、5200、6200)的半导体衬底(例如半导体衬底1000、1700、2000E、4000E、5000D、6000F)可以经历沿与包含方向1900并垂直于方向1800的表面大致平行的平面转移层结构的层转移处理。转移处理可以通过离子注入衬底进行以在内部形成预定的弱化层来进行，并且可以包括加热衬底以沿着注入了离子的弱化层分离要转移的层的步骤。也可以通过机械动作来实现分离。另选地，可以通过研磨和/或刻蚀超过被转移层的材料来进行转移处理。可以在获得连接结构之前或者之后进行转移处理。而且，可以在3D集成处理之前或者之后进行转移处理。
在本发明的一些实施方式中，集成连接结构的半导体衬底(例如半导体衬底1000、1700、2000E、4000E、5000D、6000F)可以是任意种类的半导体晶片，诸如，例如硅(Si)晶片、砷化镓(GaAs)晶片、绝缘体上硅(SOI)晶片、锗(Ge)晶片。
在经历3D集成的处理的两个衬底的上下文中描述了本发明。术语衬底可以对应于半导体晶片，例如200mm或者300mm硅晶片或SOI晶片。衬底也可以对应于管芯，即，划片为多个部分之后的一块晶片。在其它方面中，本发明的概念可以应用于在晶片级别或管芯级别进行的3D集成。
在以上描述中，术语生长、沉积、实现被可互换地使用以指示半导体制造领域的已知技术，诸如，例如化学气相沉积(CVD)、外延、物理气相沉积(PVD)、溅射沉积、印刷技术中的任一种。

Claims (18)

1.一种实现半导体衬底(1000)中的连接结构(1200、2200、4200、5200、6200)的方法，所述半导体衬底至少具有第一表面(1100)并且将沿所述第一表面与第二衬底(1700)3D集成，其中所述3D集成经受至少一个维度上的横向错位，该横向错位具有错位值(M)；该方法包括生长扩散阻挡结构(2211、4211、5211、6211、6213)以防止导电层的元素扩散到所述半导体衬底的其余部分的步骤(S21、S41、S51、S61A、S61B)，
其特征在于，
所述扩散阻挡结构的第一端面(2230、4230、5230、6230)在所述横向错位的方向上具有依赖于所述横向错位值的长度(L)，所述第一端面是所述扩散阻挡结构的沿垂直于所述第一表面并且从所述衬底向第一表面的方向(1800)的大致与所述第一表面平行的最外侧表面，
其中，所述扩散阻挡结构的所述长度(L)被选择为使得在3D集成结构中防止所述第二衬底的导电层的元素在集成状态下扩散。
2.根据权利要求1所述的实现连接结构的方法，其中，所述长度至少与所述横向错位值(M)相同。
3.根据权利要求1所述的实现连接结构的方法，其中，所述长度至少与所述第二衬底的所述导电层在所述错位的方向上的长度相同。
4.根据权利要求1至3中任一项所述的实现连接结构的方法，该方法还包括在生长完所述扩散阻挡结构之后，至少生长导电层(2220、4220、6220)，使得所述导电层被至少所述扩散阻挡结构从所述半导体衬底分隔开的步骤(S22A、S22B、S42A、S42B、S62A、S62B)。
5.根据权利要求1至3中任一项所述的实现连接结构的方法，该方法还包括在生长所述扩散阻挡结构之前至少生长导电层(5220)的步骤(S52)。
6.根据权利要求1至5中任一项所述的实现连接结构的方法，其中，所述生长所述扩散阻挡结构的步骤包括生长扩散阻挡层(2211、4211、5211)的步骤(S21、S41、S51)。
7.根据权利要求1至5中任一项所述的实现连接结构的方法，其中，所述生长所述扩散阻挡结构的步骤还包括在所述扩散阻挡层上生长第二层(6213)的步骤(S61B)，所述第二层(6213)的生长速度大于所述扩散阻挡层的生长速度。
8.根据权利要求1至7中任一项所述的实现连接结构的方法，其中，所述生长所述扩散阻挡层的步骤包括生长钽(Ta)、氮化钽(TaN)、氮化硅(Si3N4)中的至少一种的层。
9.根据权利要求1至7中任一项所述的实现连接结构的方法，其中，所述扩散阻挡结构的所述长度(L)介于20nm到1μm之间。
10.一种实现至少两个半导体衬底的3D集成的方法，该方法包括以下步骤：
根据权利要求1至9所述的方法在所述两个半导体衬底中的至少一个半导体衬底但优选地在每一个半导体衬底中实现连接结构；以及
沿所述两个半导体衬底中的每一个半导体衬底的第一表面接合所述两个半导体衬底。
11.根据权利要求10所述的实现至少两个半导体衬底的3D集成的方法，其中，所述接合所述两个半导体衬底的步骤包括将所述两个半导体衬底彼此接合特别是键合的步骤。
12.一种半导体系统，该半导体系统至少包括第一衬底(1000)和第二衬底(1700)或层，至少所述第一衬底包括连接结构(1200、2200、4200、5200、6200)，其中，所述第一衬底至少具有第一表面(1100)并且将沿所述第一表面与第二衬底(1700)或层3D集成，其中所述3D集成经受至少一个维度上的横向错位，所述横向错位具有错位值(M)；并且所述连接结构包括扩散阻挡结构(2211、4211、5211、6211、6213)以防止导电层的元素扩散到所述衬底的材料中，
其特征在于，
所述扩散阻挡结构被构造成使得所述扩散阻挡结构的第一端面(2230、4230、5230、6230)在所述横向错位的方向上具有依赖于所述错位值的长度(L)，所述第一端面是所述扩散阻挡结构的沿垂直于所述第一表面且从所述衬底向第一表面的方向(1800)的与所述第一表面大致平行的最外侧表面，
其中，所述扩散阻挡结构的长度(L)被选择为使得防止所述第二衬底的导电层的元素的扩散。
13.根据权利要求12所述的半导体系统，其中，所述长度至少与所述横向错位值(M)相同。
14.根据权利要求12所述的半导体系统，其中，所述长度至少与所述第二衬底的所述导电层在所述错位的方向上的长度相同。
15.根据权利要求12至14中任一项所述的半导体系统，其中，所述连接结构还至少包括导电层(2220、4220、5220、6220)，使得所述导电层至少被所述扩散阻挡结构从所述第一衬底分隔开。
16.根据权利要求12至15中任一项所述的半导体系统，其中，所述扩散阻挡结构包括扩散阻挡层(2211、4211、5211)。
17.根据权利要求12至15中任一项所述的半导体系统，其中，所述扩散阻挡结构包括扩散阻挡层(6211)和位于所述扩散阻挡层上的第二层(6213)，所述第二层的生长速度高于所述扩散阻挡层的生长速度。
18.根据权利要求12至17中任一项所述的半导体系统，其中，所述扩散阻挡层是钽(Ta)、氮化钽(TaN)、氮化硅(Si3N4)中的任一种。
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CN105486333A (zh) * 2015-11-19 2016-04-13 业成光电（深圳）有限公司 改善窄线距接合垫压合错位之感测器结构
CN105486333B (zh) * 2015-11-19 2018-08-24 业成光电（深圳）有限公司 改善窄线距接合垫压合错位之感测器结构

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KR20120038897A (ko) 2012-04-24
EP2445000A2 (en) 2012-04-25
SG180074A1 (en) 2012-05-30
JP2012084881A (ja) 2012-04-26
JP5536731B2 (ja) 2014-07-02
TW201234522A (en) 2012-08-16
CN102456587B (zh) 2015-04-22
EP2445000A3 (en) 2013-06-05
US9224704B2 (en) 2015-12-29
FR2966283B1 (fr) 2012-11-30
FR2966283A1 (fr) 2012-04-20
KR101300811B1 (ko) 2013-08-26
TWI426581B (zh) 2014-02-11

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