CN102412184A - 离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法 - Google Patents
离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法 Download PDFInfo
- Publication number
- CN102412184A CN102412184A CN2011101336196A CN201110133619A CN102412184A CN 102412184 A CN102412184 A CN 102412184A CN 2011101336196 A CN2011101336196 A CN 2011101336196A CN 201110133619 A CN201110133619 A CN 201110133619A CN 102412184 A CN102412184 A CN 102412184A
- Authority
- CN
- China
- Prior art keywords
- fleet plough
- isolation structure
- plough groove
- groove isolation
- ion injects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 92
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 238000005468 ion implantation Methods 0.000 title abstract 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 34
- 238000002360 preparation method Methods 0.000 claims description 32
- 239000011241 protective layer Substances 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 239000008393 encapsulating agent Substances 0.000 claims description 8
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 238000012856 packing Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000011049 filling Methods 0.000 abstract description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 4
- 150000004706 metal oxides Chemical class 0.000 abstract 4
- 238000003825 pressing Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开了一种离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,包括以下步骤:步骤a、于一半导体衬底上形成一层保护层;步骤b、于所述半导体衬底及保护层上形成用于隔离PMOS有源区和NMOS有源区的沟槽;步骤c、于所述沟槽内形成填充材料层,使所述沟槽为所述填充材料层充满,形成浅沟槽隔离结构;步骤d、去除所述保护层表面多余的填充材料。本发明的有益效果是:对采用HARP工艺做浅槽隔离的器件,对PMOS周围的隔离氧化物采用离子注入调整应力从受拉变为受压,从而使PMOS沟道区域应力状态改变,性能提高,工艺简单可行,有效克服选择性浅槽填充的工艺复杂性。
Description
技术领域
本发明涉及一种浅沟槽隔离结构的制备方法,尤其是一种用于半导体制造领域的离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法。
背景技术
亚常压化学汽相淀积(SA-CAD)和高浓度等离子体化学汽相淀积(HDP-CVD)工艺已广泛地用于半导体产业中,应用之一就是浅沟槽隔离(Shallow Trench Isolation, STI),即用高质量二氧化硅(SiO2)来隔离有源区(Active Areas, AA)。对小于90nm的技术节点,这两种CVD技术表现出一些差异,但SA-CVD所具有的填充能力强、SiO2膜应力可调及不存在对底层材料造成损坏等方面的优点使其成为70nm节点以下半导体器件的优选STI填充方案。由于未来技术节点的降低而不断提高STI纵宽比,所以HDP-CVD SiO2工艺的发展空间越来越小,人们开始采用SA-CVD工艺,即在540℃温度下的O3/TEOS 化学组分的高深宽比工艺(HARP)。在STI应用中,采用HARP取代HDP的主要优点是能够保持优良的STI填充能力并可拓展到45nm技术节点和更低的节点上。HARP填充的STI具有拉伸应力,该拉伸应力将会缓冲NMOS源漏极掺杂所引起的压缩应力,从而减小NMOS导电沟道和源漏极的缺陷,大大提高NMOS的性能。但该STI的拉伸应力会与PMOS源漏极掺杂所引起的向PMOS中部拉伸的拉伸应力产生竞争,导致拉伸应力较大的STI将PMOS向两侧拉伸,从而造成PMOS内部缺陷增多,如此将降低PMOS的性能。
中国专利可提高半导体器件性能的沟槽隔离结构制作方法(CN200710047357.5)公开了一种提出一种通过HDPCVD和HARP的混合型空隙填充方案,分别运用与NMOS和PMOS,从而一起提高器件的性能。但是此种工艺需要两次化学机械研磨,两次空隙填充,非常复杂,成品率低。
发明内容
针对上述存在的问题,本发明提供一种离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,以简单的工艺达到调整STI应力的技术效果,从而起到改善器件性能的目的。
本发明实现其技术目的所采用的技术手段为:
一种离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,包括以下步骤:
步骤a、于一半导体衬底上形成一层保护层;
步骤b、于所述半导体衬底及保护层上形成用于隔离PMOS有源区和NMOS有源区的沟槽;
步骤c、于所述沟槽内形成填充材料层,使所述沟槽为所述填充材料层充满,形成浅沟槽隔离结构;
步骤d、去除所述保护层表面多余的填充材料;
步骤e、于所述保护层上形成一光阻材料层,在所有所述浅沟槽隔离结构中除用于隔离NMOS有源区的所述浅沟槽隔离结构以外,其他所述浅沟槽隔离结构均通过所述光阻材料层中形成窗口予以暴露;
步骤f、向步骤e中形成的窗口中暴露的所述浅沟槽隔离结构实施离子注入;
步骤g、移除所述光阻材料层。
上述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,所述半导体衬底为单晶硅
上述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,所述步骤a形成的所述保护层为氮化硅薄膜。
上述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,所述步骤a形成所述保护层的方法为化学汽相淀积法或者物理汽相淀积法。
上述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,所述步骤b形成所述沟槽的方法为:形成图案化硬掩膜层覆于所述步骤a中形成的保护层上,利用所述图案化硬掩膜层进行干法刻蚀以形成沟槽。
上述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,所述步骤c形成所述填充材料层采用高深宽比填充工艺。
上述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,所述步骤d中去除多余填充材料的方法为化学机械研磨。
上述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,所述步骤e形成所述光阻材料层地方法为光阻旋涂。
上述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,所述步骤e于所述光阻材料层形成窗口的方法为光刻。
上述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,所述步骤f实施离子注入采用重掺杂。
上述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,所述步骤f实施离子注入所采用的离子可择自氩、锗、硅或氧。
上述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其中,所述步骤g移除所述光阻材料层的方法为清洗。
本发明的有益效果是:对采用HARP工艺做浅槽隔离的器件,对PMOS周围的隔离氧化物采用离子注入调整应力从受拉变为受压,从而使PMOS沟道区域应力状态改变,性能提高,工艺简单可行,有效克服选择性浅槽填充的工艺复杂性。
附图说明
图1为本发明离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法的流程框图;
图2为本发明离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法实施后的状态结构图。
具体实施方式
下面结合附图和具体实施例对本发明作进一步说明,但不作为本发明的限定。
如图1、图2所示,本发明离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法包括以下步骤:
步骤a、于一半导体衬底1上形成一层保护层2,此处半导体衬底为单晶硅,保护层2为化学汽相淀积法或者物理汽相淀积法形成的氮化硅薄膜。
步骤b、于半导体衬底1及保护层2上形成用于隔离PMOS有源区11的沟槽31和隔离NMOS有源区12的沟槽32,此处形成沟槽31和沟槽32的方法例如先形成图案化硬掩膜层覆于步骤a中形成的保护层上2,利用图案化硬掩膜层进行干法刻蚀以形成沟槽31和沟槽32。
步骤c、于沟槽31和沟槽32内形成填充材料层,使沟槽31和沟槽32为填充材料层充满,形成浅沟槽隔离结构,此处采用亚常压化学气相淀积高深宽比工艺进行填充。
步骤d、去除保护层2表面多余的填充材料,此处可采用化学机械研磨去除多余的填充材料。
步骤e、与保护层2上形成一个光阻材料层4,使除用于隔离NMOS有源区12的浅沟槽隔离结构暴露,此处采用光阻旋涂形成光阻材料层,并采用光刻手段形成窗口5以暴露浅沟槽隔离结构。也即仅用于隔离PMOS有源区11的浅沟槽隔离结构均通过光阻材料层4中形成的窗口5予以暴露,而同时用于隔离NMOS有源区12和PMOS有源区11的浅沟槽隔离结构(例如NMOS有源区12和PMOS有源区11交界处的浅沟槽隔离结构)被光阻材料层5所覆盖并不暴露。
步骤f、向步骤e中形成的窗口5暴露的所述浅沟槽隔离结构实施离子注入,注入离子采用重掺杂,离子可择自氩、锗、硅或氧。
步骤g、通过清洗的方式移除光阻材料层4。
后续还可以通过热处理来加强调整应力的效果。
本发明离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法维持了HARP工艺对NMOS的性能提高,同时通过对PMOS周围的STI实施离子注入,调整应力从受拉变为受压,从而使PMOS沟道区域应力状态改变,克服了HARP工艺对PMOS的性能影响,从而提高了器件的整体性能。在NMOS与PMOS交界区的STI结构由于为相邻的NMOS和PMOS共用,为不影响NMOS器件的性能所以不对共用的STI进行离子注入,虽然在交界区与NMOS相邻的PMOS沟道内没有形成受压力,但是也可以通过非共用一侧的STI由离子注入产生的推力平衡共用STI一侧带来的拉力,PMOS性能提升虽不如其他区域明显但也可得到明显改善。
以上所述仅为本发明较佳的实施例,并非因此限制本发明的申请专利范围,所以凡运用本发明说明书及图示内容所作出的等效结构变化、利用公知的与本发明中提到具等同作用的物质进行代替,利用公知的与本发明中提到的手段方法具等同作用的手段方法进行替换,所得到的实施方式或者实施结果均包含在本发明的保护范围内。
Claims (12)
1.一种离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其特征在于,包括以下步骤:
步骤a、于一半导体衬底上形成一层保护层;
步骤b、于所述半导体衬底及保护层上形成用于隔离PMOS有源区和NMOS有源区的沟槽;
步骤c、于所述沟槽内形成填充材料层,使所述沟槽为所述填充材料层充满,形成浅沟槽隔离结构;
步骤d、去除所述保护层表面多余的填充材料;
步骤e、于所述保护层上形成一光阻材料层,在所有所述浅沟槽隔离结构中除用于隔离NMOS有源区的所述浅沟槽隔离结构以外,其他所述浅沟槽隔离结构均通过所述光阻材料层中形成窗口予以暴露;
步骤f、向步骤e中形成的窗口中暴露的所述浅沟槽隔离结构实施离子注入;
步骤g、移除所述光阻材料层。
2.如权利要求1所述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其特征在于,所述半导体衬底为单晶硅。
3.如权利要求1所述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其特征在于,所述步骤a形成的所述保护层为氮化硅薄膜。
4.如权利要求1所述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其特征在于,所述步骤a形成所述保护层的方法为化学汽相淀积法或者物理汽相淀积法。
5.如权利要求1所述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其特征在于,所述步骤b形成所述沟槽的方法为:形成图案化硬掩膜层覆于所述步骤a中形成的保护层上,利用所述图案化硬掩膜层进行干法刻蚀以形成沟槽。
6.如权利要求1所述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其特征在于,所述步骤c形成所述填充材料层采用高深宽比填充工艺。
7.如权利要求1所述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其特征在于,所述步骤d中去除多余填充材料的方法为化学机械研磨。
8.如权利要求1所述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其特征在于,所述步骤e形成所述光阻材料层地方法为光阻旋涂。
9.如权利要求1所述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其特征在于,所述步骤e于所述光阻材料层形成窗口的方法为光刻。
10.如权利要求1所述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其特征在于,所述步骤f实施离子注入采用重掺杂。
11.如权利要求1所述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其特征在于,所述步骤f实施离子注入所采用的离子可择自氩、锗、硅或氧。
12.如权利要求1所述离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法,其特征在于,所述步骤g移除所述光阻材料层的方法为清洗。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110133619.6A CN102412184B (zh) | 2011-05-23 | 2011-05-23 | 离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法 |
US13/339,404 US20120302038A1 (en) | 2011-05-23 | 2011-12-29 | Method for preparing a shallow trench isolation structure with the stress of its isolation oxide being tuned by ion implantation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110133619.6A CN102412184B (zh) | 2011-05-23 | 2011-05-23 | 离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102412184A true CN102412184A (zh) | 2012-04-11 |
CN102412184B CN102412184B (zh) | 2014-03-12 |
Family
ID=45914196
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110133619.6A Active CN102412184B (zh) | 2011-05-23 | 2011-05-23 | 离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20120302038A1 (zh) |
CN (1) | CN102412184B (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102820266A (zh) * | 2012-04-16 | 2012-12-12 | 上海华力微电子有限公司 | 一种前金属介电质层应力调配方法 |
CN104795412A (zh) * | 2014-01-20 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
CN106409679A (zh) * | 2015-07-21 | 2017-02-15 | 台湾积体电路制造股份有限公司 | 具有掺杂的隔离绝缘层的鳍式场效应晶体管 |
WO2018161643A1 (zh) * | 2017-03-06 | 2018-09-13 | 清华大学 | 应力调控方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102916024B (zh) | 2012-10-08 | 2015-12-02 | 上海华力微电子有限公司 | 一种形成双深度隔离沟槽的方法 |
US9087870B2 (en) * | 2013-05-29 | 2015-07-21 | GlobalFoundries, Inc. | Integrated circuits including FINFET devices with shallow trench isolation that includes a thermal oxide layer and methods for making the same |
FR3012665A1 (zh) | 2013-10-31 | 2015-05-01 | St Microelectronics Crolles 2 | |
FR3012667A1 (zh) * | 2013-10-31 | 2015-05-01 | St Microelectronics Crolles 2 | |
FR3012666A1 (zh) | 2013-10-31 | 2015-05-01 | St Microelectronics Crolles 2 | |
CN109037144A (zh) * | 2018-08-01 | 2018-12-18 | 武汉新芯集成电路制造有限公司 | 改善扩散长度效应及制作mos晶体管的方法 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1359145A (zh) * | 2000-12-09 | 2002-07-17 | 三星电子株式会社 | 集成电路及其形成方法 |
US6514833B1 (en) * | 1999-09-24 | 2003-02-04 | Advanced Micro Devices, Inc. | Method of inhibiting lateral diffusion between adjacent wells by introducing carbon or fluorine ions into bottom of STI groove |
CN1471173A (zh) * | 2002-06-24 | 2004-01-28 | ������������ʽ���� | 半导体器件及其制造方法 |
CN1797736A (zh) * | 2004-12-03 | 2006-07-05 | 台湾积体电路制造股份有限公司 | 调整晶体管的浅沟渠隔离结构应力的方法 |
CN1949472A (zh) * | 2005-10-14 | 2007-04-18 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
CN101123253A (zh) * | 2006-08-10 | 2008-02-13 | 国际商业机器公司 | 集成电路以及制作集成电路的方法 |
US7482245B1 (en) * | 2006-06-20 | 2009-01-27 | Novellus Systems, Inc. | Stress profile modulation in STI gap fill |
CN101419942A (zh) * | 2007-10-24 | 2009-04-29 | 中芯国际集成电路制造(上海)有限公司 | 一种可提高半导体器件性能的沟槽隔离结构制作方法 |
CN101740456A (zh) * | 2008-11-17 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | 浅沟槽结构制造方法及快闪存储器 |
CN101930946A (zh) * | 2009-06-19 | 2010-12-29 | 新加坡格罗方德半导体制造私人有限公司 | 具有高电压晶体管的集成电路系统及其制造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7968960B2 (en) * | 2006-08-18 | 2011-06-28 | Micron Technology, Inc. | Methods of forming strained semiconductor channels |
US20090315115A1 (en) * | 2008-06-23 | 2009-12-24 | Chartered Semiconductor Manufacturing, Ltd. | Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement |
US7851328B2 (en) * | 2008-09-22 | 2010-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI stress modulation with additional implantation and natural pad sin mask |
-
2011
- 2011-05-23 CN CN201110133619.6A patent/CN102412184B/zh active Active
- 2011-12-29 US US13/339,404 patent/US20120302038A1/en not_active Abandoned
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6514833B1 (en) * | 1999-09-24 | 2003-02-04 | Advanced Micro Devices, Inc. | Method of inhibiting lateral diffusion between adjacent wells by introducing carbon or fluorine ions into bottom of STI groove |
CN1359145A (zh) * | 2000-12-09 | 2002-07-17 | 三星电子株式会社 | 集成电路及其形成方法 |
CN1471173A (zh) * | 2002-06-24 | 2004-01-28 | ������������ʽ���� | 半导体器件及其制造方法 |
CN1797736A (zh) * | 2004-12-03 | 2006-07-05 | 台湾积体电路制造股份有限公司 | 调整晶体管的浅沟渠隔离结构应力的方法 |
CN1949472A (zh) * | 2005-10-14 | 2007-04-18 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
US7482245B1 (en) * | 2006-06-20 | 2009-01-27 | Novellus Systems, Inc. | Stress profile modulation in STI gap fill |
CN101123253A (zh) * | 2006-08-10 | 2008-02-13 | 国际商业机器公司 | 集成电路以及制作集成电路的方法 |
CN101419942A (zh) * | 2007-10-24 | 2009-04-29 | 中芯国际集成电路制造(上海)有限公司 | 一种可提高半导体器件性能的沟槽隔离结构制作方法 |
CN101740456A (zh) * | 2008-11-17 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | 浅沟槽结构制造方法及快闪存储器 |
CN101930946A (zh) * | 2009-06-19 | 2010-12-29 | 新加坡格罗方德半导体制造私人有限公司 | 具有高电压晶体管的集成电路系统及其制造方法 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102820266A (zh) * | 2012-04-16 | 2012-12-12 | 上海华力微电子有限公司 | 一种前金属介电质层应力调配方法 |
CN104795412A (zh) * | 2014-01-20 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
CN104795412B (zh) * | 2014-01-20 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
CN106409679A (zh) * | 2015-07-21 | 2017-02-15 | 台湾积体电路制造股份有限公司 | 具有掺杂的隔离绝缘层的鳍式场效应晶体管 |
US10192985B2 (en) | 2015-07-21 | 2019-01-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET with doped isolation insulating layer |
CN106409679B (zh) * | 2015-07-21 | 2021-04-13 | 台湾积体电路制造股份有限公司 | 具有掺杂的隔离绝缘层的鳍式场效应晶体管 |
WO2018161643A1 (zh) * | 2017-03-06 | 2018-09-13 | 清华大学 | 应力调控方法 |
CN108525609A (zh) * | 2017-03-06 | 2018-09-14 | 清华大学 | 应力调控方法 |
CN108525609B (zh) * | 2017-03-06 | 2020-11-06 | 清华大学 | 应力调控方法 |
Also Published As
Publication number | Publication date |
---|---|
US20120302038A1 (en) | 2012-11-29 |
CN102412184B (zh) | 2014-03-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102412184B (zh) | 离子注入调整隔离氧化物应力的浅沟槽隔离结构制备方法 | |
CN104299970B (zh) | 具有减少的面的外延区的mos器件 | |
CN1762056B (zh) | 具有拉伸应变基片的半导体及其制备方法 | |
CN104299909A (zh) | 热调整半导体器件中的应力 | |
CN106653751B (zh) | 半导体器件及其制造方法 | |
CN103137624A (zh) | 高栅极密度器件和方法 | |
CN103390644A (zh) | 半导体器件及其制造方法 | |
CN109148278A (zh) | 半导体结构及其形成方法 | |
US8546241B2 (en) | Semiconductor device with stress trench isolation and method for forming the same | |
CN1956221A (zh) | 具有介质应力产生区的晶体管及其制造方法 | |
CN103531455B (zh) | 半导体器件及其制造方法 | |
CN104752202B (zh) | 一种半导体器件的制造方法 | |
CN102369598A (zh) | 缩减在半导体装置的接点等级中图案化两个不同应力诱发层的期间所产生与地貌相关的不平整 | |
CN103280459B (zh) | 具有深槽结构的图形化应变nmos器件及其制作方法 | |
US20190027602A1 (en) | Fabricating method of fin structure with tensile stress and complementary finfet structure | |
CN106158651A (zh) | Ldmos晶体管的形成方法及ldmos晶体管 | |
CN106298665A (zh) | 半导体器件的制造方法 | |
CN106328501A (zh) | 半导体器件的制造方法 | |
CN105845573A (zh) | 一种FinFET器件及其制造方法、电子装置 | |
CN103367226B (zh) | 半导体器件制造方法 | |
CN107689329A (zh) | 鳍式场效应晶体管及其制造方法 | |
CN105097698A (zh) | 一种半导体器件及其制造方法 | |
CN204706565U (zh) | 一种半导体器件 | |
CN102610530B (zh) | 一种具有高锗组分的锗硅沟道pmos的制备方法 | |
CN102723336A (zh) | 一种双多晶SOI应变SiGe回型沟道BiCMOS集成器件及制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |