CN101123253A - 集成电路以及制作集成电路的方法 - Google Patents

集成电路以及制作集成电路的方法 Download PDF

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CN101123253A
CN101123253A CNA200710109611XA CN200710109611A CN101123253A CN 101123253 A CN101123253 A CN 101123253A CN A200710109611X A CNA200710109611X A CN A200710109611XA CN 200710109611 A CN200710109611 A CN 200710109611A CN 101123253 A CN101123253 A CN 101123253A
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silicon layer
fet
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CN100544001C (zh
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杨海宁
托马斯·W.·戴尔
李伟健
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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International Business Machines Corp
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Abstract

集成电路以及制作集成电路的方法。披露了一种在分离的硅层上引入应变MOSFETs的IC的制作方法和结构。N型沟道场效应晶体管(nFET)和P型沟道场效应晶体管(pFET)分别形成于分离的硅层上。因此可以形成紧邻nFETs和pFETs的浅槽隔离(STI)区以将不同的应力引入各自nFETs和pFETs的沟道区。结果，通过STI应力可以提高nFETs和pFETs的性能。此外，由于两个硅层的位置彼此相对垂直，IC的面积也可以被降低。

Description

集成电路以及制作集成电路的方法
技术领域
[0001]本发明主要涉及集成电路(IC)，以及更具体而言，涉及在分离的硅层上引入应变MOSFETs的IC的制作方法和结构。
背景技术
[0002]随着半导体技术尺寸的降低，浅槽隔离(STI)已成为电隔离的更可取的选择。正如目前的研究所显示的，STI应力对互补金属氧化物半导体(CMOS)器件性能具有显著的影响。例如，STI应力可以造成相邻器件(称为应变器件)沟道区域内的应变，以致于将改变器件的电特性。在本领域已知道，增强一种类型器件，例如N型沟道场效应晶体管(nFET)的STI应力会使其他类型的器件，例如P型沟道场效应晶体管(pFET)退化。例如，拉伸的STI应力将通过增加电子迁移率增加nFET的开态电流(Ion)。然而，通过降低空穴迁移率和由此降低pFET的开态电流，拉伸的STI应力将对附近的pFET产生相反的影响。在传统的CMOS电路中，例如，图1的电路10，nFET12和pFET14通过相同硅层(基片)18上的STI16被分离。同样，STI16应力对传统CMOS电路10的影响总是被混在一起，即，增强一种类型的器件例如nFET12，同时使其他类型的器件例如pFET14退化，不管是什么应力类型。
[0003]另外，已知不同类型的衬垫应力对FET性能具有不同的影响。解决上述问题的一个办法提出了双应力衬垫以提高nFET和pFET的性能。然而，双应力衬垫的形成需要多次沉积，以及在有硅化物存在的情况下，将衬垫薄膜从FETs刻蚀掉，这可能严重地影响硅化物表面电阻值。
[0004]鉴于前面所述，在本领域内对于解决以上明确的问题以及充分利用应变MOSFETs的方法有着需求。
发明内容
[0005]本发明披露了在分离的硅层上引入应变MOSFETs的IC的制作方法和结构。N型沟道场效应晶体管(nFET)和P型FETs(pFET)分别形成于分离的硅层上。因此，可以形成紧邻nFETs和pFETs的浅槽隔离(STI)区以将不同的应力引入到各自的nFETs和pFETs的沟道区域。结果，通过STI应力可以提高nFETs和pFETs的性能。此外，由于两个硅层的位置彼此相对垂直，IC的面积也可以被降低。
[0006]本发明的第一方面包括一种集成电路(IC)，其包括：通过电介质层分离开的两个硅层，两个硅层中的一个位于另一个的上方；形成于两个硅层中的一个之上的N型沟道场效应晶体管(nFET)，以及形成于两个硅层中的另一个之上的P型沟道场效应晶体管(pFET)；紧邻nFET的第一浅槽隔离(STI)，和紧邻pFET的第二STI，其中第一STI和第二STI分别在nFET的沟道区域以及pFET的沟道区域诱发不同的应力。
[0007]本发明的第二方面包括制作集成电路的方法，该方法包括：在第一硅层上形成第一场效应晶体管(FET)和第一浅槽隔离(STI)，该第一FET和第一STI彼此紧邻；对第一FET进行硅化；在第一FET上沉积第一电介质层；通过第一电介质层形成与第一FET的接触；在第一电介质层上沉积第二电介质层；在第二电介质层上形成第二硅层；在第二硅层上形成第二FET和第二STI，第二FET和第二STI彼此紧邻；对第二FET进行硅化；在第二FET上沉积第三电介质层；以及形成到第二FET的接触，并通过第三电介质层将该接触延伸到第一FET。
[0008]本发明的第三方面包括一种集成电路(IC)，其包括：位于第一硅层上的N型沟道场效应晶体管(nFET)；与第一硅层上的nFET紧邻的第一浅槽隔离(STI)，第一STI包括nFET沟道区域上的拉伸应力；位于第二硅层上的P型沟道FET(pFET)；以及位于第二硅层上与pFET紧邻的第二STI，第二STI包括pFET沟道区域上的压缩应力；其中第一硅层和第二硅层的位置彼此不同地相对垂直。
[0009]本发明的说明性的方面力图解决此处所描述的问题以及会被熟练的技术工人发现的没有讨论的其他问题。
附图说明
[0010]结合描述本发明的各实施例的附图，从下列对本发明各个方面的详细描述，将更加容易地理解本发明的上述和其他特征，其中：
[0011]图1显示了具有STI的传统互补金属氧化物半导体(CMOS)。
[0012]图2-8显示了形成包括分离的硅层上的应变MOSFETs的集成电路的方法的一个实施例，图8显示了根据本发明的IC的一个实施例。
[0013]要指出的是本发明的附图不是按比例的。附图旨在仅描述本发明的典型方面，因此不应当被看作限制本发明的范畴。在附图中，类似的编号代表附图之间的类似的元件。
具体实施方式
[0014]下列的详细描述实际上仅是代表性的并不旨在限制本发明或本发明的应用和使用。另外，无意被呈现在前述技术领域、背景、概述或下列详细描述中的任何已表达的或暗含的理论所限制。
[0015]本发明的一个实施例包括，如图8所示，IC100，其在分离的和叠层的硅层120、122上分别具有应变nFET112和应变pFET114器件。硅层120和122的位置彼此相对差异性地垂直，尤其是，被电介质层124例如硅氧化物层124以及夹层电介质层(ILD)160所分开并隔离。图8中，出于说明性的目的，硅层122(上硅层)被显示位于硅层120(下硅层)之上，需要理解的是该具体实施例不限制本发明的范畴。例如，nFETs112所处的硅层120可以位于硅层122之上。根据一个实施例，硅层120、122可以分别具有不同的晶向，例如<100>和<110>。尽管说明了两个特定的晶向<100>和<110>，只要它们彼此不同，也可以使用其他的晶向。此外，应当认识到的是硅层120、122可以具有相同的晶向。
[0016]浅槽隔离(STI)区125位于硅层120内并紧邻nFETs112。根据一个实施例，STI125包括在nFET112的沟道区(体)126内诱发拉伸应力的高拉伸应力材料。应当认识到是本发明的范畴不限于STI125的具体类型的STI材料。例如，如果需要，STI125可以含有压应力材料。
[0017]STI128位于紧邻pFET114的硅层122内。根据一个实施例，STI128包括不同于STI125的应力特征，例如，STI125和STI128分别在nFET112沟道区126和pFET114沟道区130内诱发不同的应力。例如，在STI125包括高拉伸应力填充材料情况中，STI128可以包括在pFET114的沟道区(体)内诱发压应力的高压应力材料。应当认识到的是本发明的范畴不限于具体类型的STI特征或STI128的填充材料。例如，STI128可以含有拉伸应力材料。
[0018]衬垫层132、134分别位于nFETs112和pFET114之上并覆盖后二者。根据一个实施例，衬垫层132和134包括不同的应力特征，例如衬垫层132和134分别在nFET112沟道区126和pFET114沟道区130内诱发不同的应力。例如，衬垫层132可以是在nFET112沟道区126内诱发拉伸应力以增强电子迁移率的拉伸应力衬垫。衬垫134可以是在pFET114沟道区130内诱发压应力的压应力衬垫层。要认识到是衬垫层132、134可以包括任何类型的材料并且都包括在本发明中。例如，衬垫层132、134可以包括氮化硅(Si3N4)，可以用于说明性目的而被称为氮化物衬垫层。
[0019]根据一个实施例，STI128和器件(例如，nFET112)在下硅层(此处为120)上的位置，被设计成：与下硅层上的器件的接触140延伸穿过STI128，以避免与上硅层122的硅和器件(例如pFET114)的电短路，即隔离。应当认识到的是本发明也包括将上硅层122上的器件与下硅层120上的器件隔离的其他方法。
[0020]根据一个实施例，nFET112的硅化物和pFET114的硅化物含有不同的硅化物应力，这将在后续进行描述。
[0021]图2-8显示了根据本发明一个实施例形成图8的IC100的方法。参照图2，该工艺可以开始于具有晶向<100>的第一硅(下)层120。然后，可以在硅层120上和内部形成nFETs112和STI125，STI125和nFETs112彼此紧邻。要认识到的是可以使用任何现在已知或将来出现的方法以形成nFETs112和STI125，并且都包括在本发明中。例如，STI125填充材料(STI填充)可以包括利用高密度等离子(HDP)或基于臭氧(O3)/四乙基原硅酸盐(TEOS，Si(OC2H5)4)的热化学气相沉积(CVD)方法沉积的二氧化硅(SiO2)。根据一个实施例，STI125填充材料含有高拉伸应力。任何方法可以用于控制STI填充材料沉积工艺以获得STI125的应力特征，例如拉伸应力。例如，可以控制STI材料的沉积温度以获得期望的STI应力特征。对于使用CVD方法进行沉积的情况，当沉积温度足够高，例如高于大约900℃时，或者足够低，例如，低于大约室温时，SiO2的STI125填充材料可以含有压应力；而如果沉积温度介于上述温度之间，例如，600℃，SiO2的STI125填充材料可以含有拉伸应力。
[0022]接下来，利用金属在按nFETs112要求特别选择的参数(例如，退火温度)下，对nFETs112的栅极150和/或扩散区域154进行硅化。尤其是，可以控制nFETs112硅化物的硅化物应力以增强nFETs112的性能，例如，电子迁移率。可以使用任何方法控制nFETs112的硅化物应力，都包括在本发明中。例如，可以控制nFETs112的硅化沉积参数以调节硅化物应力。对于另一实例，也可以控制nFETs112的硅化物薄膜的结构和成份以获得期望的硅化物应力。
[0023]转到图3，利用任何已知的或将来出现的方法在nFETs112上沉积拉伸氮化物衬垫(覆盖)层132并覆盖nFETs112。继拉伸氮化物衬垫层132之后，在拉伸氮化物衬垫层132上沉积例如二氧化硅的夹层电介质(ILD)层160。应当认识到的是ILD层160(以及本发明的其他ILDs)可以包括任何材料，例如，氮化硅(Si3N4)、二氧化硅(SiO2)、氟化二氧化硅(FSG)、氢化硅碳氧化物(SiCOH)，以及多孔SiCOH。
[0024]转到图4，通过ILD层160和拉伸氮化物衬垫132形成接触140以接触nFET112的栅极150和/或扩散区域154。在形成接触140时，可以使用任何方法，都包括在本发明中。
[0025]转到图5，利用任何方法在ILD层160上形成另一个，例如二氧化硅的ILD层124。继ILD层124之后，利用任何方法，例如键合，在ILD层124上形成第二硅层(上)122。根据一个实施例，第二硅层122具有不同于第一硅层120的晶向。例如，第二硅层122的晶向为<110>。
[0026]转到图6，pFET114和STI128形成于第二硅层122之上或之内。跟据一个实施例，STI128的形成完全穿过第二硅层122直达ILD层124。根据一个实施例，STI128在接触140上形成使得接触140(到第一/下硅层120)上的nFET112，如果被延伸穿过第二硅层122，将延伸穿过STI128，使得接触140将与第二硅层122的硅隔离开来。
[0027]根据一个实施例，控制STI128填充材料的沉积和STI125填充材料的沉积使得STI125和STI128含有不同的STI应力特征。例如，STI128含有在pFET114的沟道(体)区域130(图8)内诱发压应力的高压应力。其他实施例都可能并被包括在本发明中。
[0028]接下来，利用金属在按pFET114要求特别选择的参数(例如退火温度)下，对pFET114的栅极152和/或扩散区域156进行硅化。尤其是，可以控制pFET的硅化物应力以特别地增强pFET114的性能，例如电子迁移率。同样，nFET112的硅化和pFET114的硅化可以产生含有不同硅化物应力的硅化物。
[0029]转到图7，利用任何方法形成压缩氮化物衬垫层134以覆盖pFET114。同样，在本发明中，可以控制nFET112上衬垫层的沉积(例如，拉伸氮化物衬垫层132)以及pFET114上的衬垫层(例如，压缩氮化物衬垫层134)，使得衬垫层132和衬垫层134含有不同的应力特征，例如，分别诱发拉伸应力和压应力。继压缩氮化物衬垫层134之后，在层134上沉积ILD层162。
[0030]转到图8，形成了到pFET114的接触142(例如，扩散区156)并且到nFET112的接触140被延伸穿过ILD124、第二硅层122(STI128)、压缩氮化物衬垫134以及ILD162。
[0031]这样，IC100令人满意地解决了以上被明确的现有工艺状况技术的问题，并可以充分利用STI应力、衬垫应力和硅化物应力以提高nFETs和pFETs的性能。此外，由于nFETs112和pFETs114位于彼此相对差异性地垂直(叠层)布置的分离的硅层120、122之上，IC的面积也可以被降低。
[0032]以上描述的结构被用于集成电路芯片中。所产生的集成电路芯片可以以未加工过的晶片形式(即，作为具有多个未封装芯片的单一晶片)、作为裸单元片，或以封装的形式被制造商配销出去。在后面的情况中，芯片被安装在单一的芯片封装内(例如塑料载体，具有固定在母板或其他更高层次载体的引脚)或者多芯片封装内(例如陶瓷载体具有表面互连或埋式互连，或两者都有)。然后，在任何一种情况下，上述芯片被与其他芯片、离散电路元件、和/或其他信号处理器件集成在一起，作为(a)中间产品，例如母板，或(b)终端产品的一部分。上述终端产品可以是包括集成电路芯片的任何产品，范围从玩具和其他低端应用到具有显示器、键盘或其他输入器件、以及中央处理器的高级计算机产品。
[0033]出于说明和描述目的，已经给与了本发明各方面的前述描述。不是想详尽描述或将本发明限制在所披露的精确形式，很明显，许多修改和变更是可能的。在附带的权利要求所定义的本发明的范畴内，打算包括对本领域中技术人员来说显而易见的上述修改和变更。

Claims (20)

1.集成电路(IC)，包括：
通过电介质层被分离的两个硅层，两个硅层中的一个位于另一个之上；
在两个硅层中的一个之上形成的N型沟道场效应晶体管(nFET)，以及在在两个硅层中的另一个之上形成的P型沟道场效应晶体管(pFET)；以及
紧邻nFET的第一浅槽隔离(STI)，以及紧邻pFET的第二STI，其中第一STI和第二STI分别在nFET的沟道区和pFET的沟道区中诱发不同的应力。
2.权利要求1的集成电路，其中第一STI诱发拉伸应力，第二STI诱发压缩应力。
3.权利要求1的集成电路，进一步包括nFET上的第一衬垫层和pFET上的第二衬垫层，其中第一衬垫层和第二衬垫层分别在nFET的沟道区和pFET的沟道区中诱发不同的应力。
4.权利要求3的集成电路，其中第一衬垫层诱发拉伸应力，第二衬垫层诱发压缩应力。
5.权利要求1的集成电路，其中nFET的硅化物和pFET的硅化物诱发不同的硅化物应力。
6.权利要求1的集成电路，其中第一和第二硅层具有不同的晶向。
7.权利要求1的集成电路，其中到上述硅层的下硅层上的器件的接触延伸穿过上述硅层的上硅层并与所述硅层的上硅层的硅隔离开来。
8.权利要求7的集成电路，其中所述接触延伸穿过所述硅层的上硅层上的STI。
9.制作集成电路的方法，该方法包括：
在第一硅层上形成第一场效应晶体管(FET)和第一浅槽隔离(STI)，第一FET与第一STI彼此紧邻；
对第一FET进行硅化；
在第一FET上沉积第一电介质层；
穿过第一电介质层形成到第一FET的接触；
在第一电介质层上沉积第二电介质层；
在第二电介质层上形成第二硅层；
在第二硅层上形成第二FET和第二STI，第二FET和第二STI彼此紧邻；
对第二FET进行硅化；
在第二FET上沉积第三电介质层；以及
形成到第二FET的接触并穿过第三电介质层将接触延伸到第一FET。
10.权利要求9的方法，其中第一FET硅化和第二FET硅化产生含有不同硅化物应力的硅化物。
11.权利要求9的方法，其中控制第一STI填充材料的沉积和第二STI填充材料的沉积，使得第一STI和第二STI含有不同的STI应力特征。
12.权利要求11的方法，其中第一STI和第二STI中的一个诱发拉伸应力，而另一个诱发压缩应力。
13.权利要求9的方法，进一步包括：
沉积第一衬垫层以覆盖第一FET；沉积第二衬垫层以覆盖第二FET；其中控制第一衬垫层的沉积和第二衬垫层的沉积，使得第一衬垫层和第二衬垫层含有不同的应力特征。
14.权利要求13的方法，其中第一衬垫层和第二衬垫层中的一个诱发拉伸应力，而另一个诱发压应力。
15.权利要求9的方法，其中第二STI形成于到第一FET的接触之上，使得到第一FET的接触的延伸延伸穿过第二STI。
16.权利要求9的方法，其中第一硅层和第二硅层具有不同的晶向。
17.集成电路(IC)，包括：
位于第一硅层上的N型沟道场效应晶体管(nFET)；
紧邻第一硅层上的nFET的第一浅槽隔离(STI)，第一STI在nFET的沟道区诱发拉伸应力；
位于第二硅层上的P型沟道场效应晶体管(pFET)；以及
紧邻第二硅层上的pFET的第二STI，第二STI在pFET的沟道区诱发压缩应力；
其中第一硅层和第二硅层被彼此相对不同地、垂直地布置。
18.权利要求17的集成电路，进一步包括覆盖nFET的拉伸衬垫层。
19.权利要求17的集成电路，进一步包括覆盖pFET的压缩衬垫层。
20.权利要求17的集成电路，其中nFET的硅化物和pFET的硅化物含有不同的硅化物应力。
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